Steve Kim
mbed library sources(for async_print)
Fork of
mbed-src
by 
mbed official
Revision 532:fe11edbda85c, committed 2015-04-30
- Comitter:
- mbed_official
- Date:
- Thu Apr 30 13:45:11 2015 +0100
- Parent:
- 531:47d2b67c511f
- Child:
- 533:589848968e4d
- Commit message:
- Synchronized with git revision 8c95d60d0a0c337e8161211fd1eded577e79e00b
Full URL: https://github.com/mbedmicro/mbed/commit/8c95d60d0a0c337e8161211fd1eded577e79e00b/
Stm32cubef4 update
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.s Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.s Thu Apr 30 13:45:11 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f401xc.s * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief STM32F401xCxx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,4777 @@
+/**
+ ******************************************************************************
+ * @file stm32f401xc.h
+ * @author MCD Application Team
+ * @version V2.3.0
+ * @date 02-March-2015
+ * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f401xc
+ * @{
+ */
+
+#ifndef __STM32F401xC_H
+#define __STM32F401xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F401xC_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xe.h Thu Apr 30 13:00:08 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,4752 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f401xe.h
- * @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
- * @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
- *
- * This file contains:
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f401xe
- * @{
- */
-
-#ifndef __STM32F401xE_H
-#define __STM32F401xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum
-{
-/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
- __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
- __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
- __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
- __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
- __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
- __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
- __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
- __IO uint32_t CDR; /*!< ADC common regular data register for dual
- AND triple modes, Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
- __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
- __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
- __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
- __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
- __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
- __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
- __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
- __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
- __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< Reserved, 0x1C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
- uint32_t RESERVED2; /*!< Reserved, 0x3C */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
- uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, 0x5C */
- __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
- uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
- __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
- __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
-
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
- uint32_t RESERVED7; /*!< Reserved, 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
- uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
- __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
- __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
- __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
- __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
- __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief __USB_OTG_Core_register
- */
-typedef struct
-{
- __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
- __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
- __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
- __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
- __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
- __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
- __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
- __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
- __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
- __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
- __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
- __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
- uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
- __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
- __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
- uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
- __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
-}
-USB_OTG_GlobalTypeDef;
-
-
-
-/**
- * @brief __device_Registers
- */
-typedef struct
-{
- __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
- __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
- __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
- uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
- __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
- __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
- __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
- __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
- uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
- uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
- __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
- __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
- __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
- __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
- __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
- __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
- uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
- __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
- uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
- __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
-}
-USB_OTG_DeviceTypeDef;
-
-
-/**
- * @brief __IN_Endpoint-Specific_Register
- */
-typedef struct
-{
- __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
- __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
- __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
- __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
- uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-}
-USB_OTG_INEndpointTypeDef;
-
-
-/**
- * @brief __OUT_Endpoint-Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
- uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
- __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
- uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
- __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
- __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
- uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-}
-USB_OTG_OUTEndpointTypeDef;
-
-
-/**
- * @brief __Host_Mode_Register_Structures
- */
-typedef struct
-{
- __IO uint32_t HCFG; /* Host Configuration Register 400h*/
- __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
- __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
- uint32_t Reserved40C; /* Reserved 40Ch*/
- __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
- __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
- __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
-}
-USB_OTG_HostTypeDef;
-
-
-/**
- * @brief __Host_Channel_Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t HCCHAR;
- __IO uint32_t HCSPLT;
- __IO uint32_t HCINT;
- __IO uint32_t HCINTMSK;
- __IO uint32_t HCTSIZ;
- __IO uint32_t HCDMA;
- uint32_t Reserved[2];
-}
-USB_OTG_HostChannelTypeDef;
-
-
-/**
- * @brief Peripheral_memory_map
- */
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
-#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
-#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
-#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
-
-/* Legacy defines */
-#define SRAM_BASE SRAM1_BASE
-#define SRAM_BB_BASE SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0xE0042000)
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
-
-#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
-#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
-#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
-#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
-#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
-#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
-
-/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
-#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
-#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
-
-/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
-#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
-#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
-#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
-#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
-
-/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
-#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
-#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
-#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-
-/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
-#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
-#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
-#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
-#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
-#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
-#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
-#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
-
-/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
-
-/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
-
-/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
-
-/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
-
-/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
-
-/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
-
-/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-
-/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
-#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
-#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
-#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
-#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
-#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
-
-/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
-#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
-#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
-#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
-#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
-#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
-#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
-#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
-
-/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-
-/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
-
-/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
-
-/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
-
-/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
-#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
-
-/******************* Bit definition for ADC_CSR register ********************/
-#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
-#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
-#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
-#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
-#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
-#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
-#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
-#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
-#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
-#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
-#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
-#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
-#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
-#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
-#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
-#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
-#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
-#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
-
-/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
-#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
-#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
-#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
-#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
-#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
-#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
-#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
-#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
-
-/******************* Bit definition for ADC_CDR register ********************/
-#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
-#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit */
-/* */
-/******************************************************************************/
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
-
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
-
-/******************************************************************************/
-/* */
-/* Debug MCU */
-/* */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* DMA Controller */
-/* */
-/******************************************************************************/
-/******************** Bits definition for DMA_SxCR register *****************/
-#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
-#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK ((uint32_t)0x00100000)
-#define DMA_SxCR_CT ((uint32_t)0x00080000)
-#define DMA_SxCR_DBM ((uint32_t)0x00040000)
-#define DMA_SxCR_PL ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
-#define DMA_SxCR_EN ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_SxCNDTR register **************/
-#define DMA_SxNDT ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0 ((uint32_t)0x00000001)
-#define DMA_SxNDT_1 ((uint32_t)0x00000002)
-#define DMA_SxNDT_2 ((uint32_t)0x00000004)
-#define DMA_SxNDT_3 ((uint32_t)0x00000008)
-#define DMA_SxNDT_4 ((uint32_t)0x00000010)
-#define DMA_SxNDT_5 ((uint32_t)0x00000020)
-#define DMA_SxNDT_6 ((uint32_t)0x00000040)
-#define DMA_SxNDT_7 ((uint32_t)0x00000080)
-#define DMA_SxNDT_8 ((uint32_t)0x00000100)
-#define DMA_SxNDT_9 ((uint32_t)0x00000200)
-#define DMA_SxNDT_10 ((uint32_t)0x00000400)
-#define DMA_SxNDT_11 ((uint32_t)0x00000800)
-#define DMA_SxNDT_12 ((uint32_t)0x00001000)
-#define DMA_SxNDT_13 ((uint32_t)0x00002000)
-#define DMA_SxNDT_14 ((uint32_t)0x00004000)
-#define DMA_SxNDT_15 ((uint32_t)0x00008000)
-
-/******************** Bits definition for DMA_SxFCR register ****************/
-#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
-
-/******************** Bits definition for DMA_LISR register *****************/
-#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_HISR register *****************/
-#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_LIFCR register ****************/
-#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
-
-/******************** Bits definition for DMA_HIFCR register ****************/
-#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
-
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller */
-/* */
-/******************************************************************************/
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-
-/******************* Bit definition for EXTI_EMR register *******************/
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-
-/****************** Bit definition for EXTI_RTSR register *******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-
-/****************** Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-
-/****************** Bit definition for EXTI_SWIER register ******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-
-/******************* Bit definition for EXTI_PR register ********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
-
-/******************************************************************************/
-/* */
-/* FLASH */
-/* */
-/******************************************************************************/
-/******************* Bits definition for FLASH_ACR register *****************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
-#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
-
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
-
-/******************* Bits definition for FLASH_SR register ******************/
-#define FLASH_SR_EOP ((uint32_t)0x00000001)
-#define FLASH_SR_SOP ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
-#define FLASH_SR_BSY ((uint32_t)0x00010000)
-
-/******************* Bits definition for FLASH_CR register ******************/
-#define FLASH_CR_PG ((uint32_t)0x00000001)
-#define FLASH_CR_SER ((uint32_t)0x00000002)
-#define FLASH_CR_MER ((uint32_t)0x00000004)
-#define FLASH_CR_SNB ((uint32_t)0x000000F8)
-#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
-#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
-#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
-#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
-#define FLASH_CR_STRT ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK ((uint32_t)0x80000000)
-
-/******************* Bits definition for FLASH_OPTCR register ***************/
-#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
-
-#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
-#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
-
-/****************** Bits definition for FLASH_OPTCR1 register ***************/
-#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
-#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
-#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
-#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
-#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
-#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
-#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
-#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
-#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
-#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
-#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
-#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
-
-/******************************************************************************/
-/* */
-/* General Purpose I/O */
-/* */
-/******************************************************************************/
-/****************** Bits definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
-
-#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
-
-#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
-
-#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
-
-#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
-
-#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
-
-#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
-
-#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
-
-#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
-
-#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
-
-#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
-
-#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
-
-#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
-
-#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
-
-#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
-
-#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
-
-/****************** Bits definition for GPIO_OTYPER register ****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
-
-/****************** Bits definition for GPIO_OSPEEDR register ***************/
-#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
-
-#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
-
-#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
-
-#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
-
-#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
-
-#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
-
-#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
-
-#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
-
-#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
-
-#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
-
-#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
-
-#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
-
-#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
-
-#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
-
-#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
-
-#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
-
-/****************** Bits definition for GPIO_PUPDR register *****************/
-#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
-
-#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
-
-#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
-
-#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
-
-#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
-
-#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
-
-#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
-
-#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
-
-#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
-
-#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
-
-#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
-
-#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
-
-#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
-
-#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
-
-#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
-
-#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
-
-/****************** Bits definition for GPIO_IDR register *******************/
-#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
-
-/****************** Bits definition for GPIO_ODR register *******************/
-#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
-
-/****************** Bits definition for GPIO_BSRR register ******************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface */
-/* */
-/******************************************************************************/
-/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
-#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
-#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
-#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
-#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
-#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
-#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
-#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
-#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
-#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
-#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
-#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
-
-/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-
-#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
-#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
-
-/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
-
-#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
-#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
-#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
-
-#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
-
-/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
-#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
-
-/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
-
-/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
-#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
-#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
-#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
-#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
-#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
-#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
-#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
-#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
-#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
-#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
-
-/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
-#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
-#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
-#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
-#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
-
-/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
-#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
-
-/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/****************** Bit definition for I2C_FLTR register *******************/
-#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
-#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG */
-/* */
-/******************************************************************************/
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
-#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
-#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
-
-
-/******************************************************************************/
-/* */
-/* Power Control */
-/* */
-/******************************************************************************/
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
-#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
-#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
-#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
-#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
-
-/* Legacy define */
-#define PWR_CR_PMODE PWR_CR_VOS
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
-#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
-#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
-#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
-#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001)
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
-
-#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
-#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
-#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
-#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
-#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
-#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
-
-#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
-#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
-#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
-#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
-#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
-#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
-#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
-#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
-#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
-
-#define RCC_CR_HSEON ((uint32_t)0x00010000)
-#define RCC_CR_HSERDY ((uint32_t)0x00020000)
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
-#define RCC_CR_CSSON ((uint32_t)0x00080000)
-#define RCC_CR_PLLON ((uint32_t)0x01000000)
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
-#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
-#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
-
-/******************** Bit definition for RCC_PLLCFGR register ***************/
-#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
-#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
-#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
-#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
-#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
-#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
-#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
-
-#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
-#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
-#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
-#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
-#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
-#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
-#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
-#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
-#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
-#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
-
-#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
-#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
-#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
-
-#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
-#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
-#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
-
-#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
-#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
-#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
-#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
-#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
-
-/******************** Bit definition for RCC_CFGR register ******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
-#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
-#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
-#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
-#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
-#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
-
-/*!< MCO1 configuration */
-#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
-#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
-#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
-
-#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
-
-#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
-#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
-#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
-#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
-
-#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
-#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
-#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
-#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
-
-#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
-#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
-#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
-
-/******************** Bit definition for RCC_CIR register *******************/
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
-#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
-
-#define RCC_CIR_CSSF ((uint32_t)0x00000080)
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
-#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
-
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
-#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
-
-#define RCC_CIR_CSSC ((uint32_t)0x00800000)
-
-/******************** Bit definition for RCC_AHB1RSTR register **************/
-#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
-#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
-#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
-#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
-#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
-#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
-#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
-#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
-#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
-
-/******************** Bit definition for RCC_AHB2RSTR register **************/
-#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
-
-/******************** Bit definition for RCC_AHB3RSTR register **************/
-
-/******************** Bit definition for RCC_APB1RSTR register **************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
-#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
-#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
-#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
-#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
-
-/******************** Bit definition for RCC_APB2RSTR register **************/
-#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
-#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
-#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
-#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
-#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
-#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
-#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
-#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
-
-/******************** Bit definition for RCC_AHB1ENR register ***************/
-#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
-#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
-#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
-#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
-#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
-#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
-#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
-#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
-#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
-#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
-#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
-
-/******************** Bit definition for RCC_AHB2ENR register ***************/
-#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
-
-/******************** Bit definition for RCC_AHB3ENR register ***************/
-
-/******************** Bit definition for RCC_APB1ENR register ***************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
-#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
-#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
-#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
-#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
-
-/******************** Bit definition for RCC_APB2ENR register ***************/
-#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
-#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
-#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
-#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
-#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
-#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
-#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
-
-/******************** Bit definition for RCC_AHB1LPENR register *************/
-#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
-#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
-#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
-#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
-#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
-#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
-#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
-#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
-#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
-#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
-#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
-#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
-#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
-
-/******************** Bit definition for RCC_AHB2LPENR register *************/
-#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
-
-/******************** Bit definition for RCC_AHB3LPENR register *************/
-
-/******************** Bit definition for RCC_APB1LPENR register *************/
-#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
-#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
-#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
-#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
-#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
-#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
-#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
-#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
-#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
-#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
-#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
-#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
-#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
-
-/******************** Bit definition for RCC_APB2LPENR register *************/
-#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
-#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
-#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
-#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
-#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
-#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
-#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
-#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
-#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
-#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
-#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
-
-/******************** Bit definition for RCC_BDCR register ******************/
-#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
-#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
-#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
-
-#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
-#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
-#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
-
-#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
-#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
-
-/******************** Bit definition for RCC_CSR register *******************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001)
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
-#define RCC_CSR_RMVF ((uint32_t)0x01000000)
-#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
-#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
-#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
-
-/******************** Bit definition for RCC_SSCGR register *****************/
-#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
-#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
-#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
-#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
-
-/******************** Bit definition for RCC_PLLI2SCFGR register ************/
-#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
-#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
-#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
-#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
-#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
-#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
-#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
-#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
-#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
-#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
-
-#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
-#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
-#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
-#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock (RTC) */
-/* */
-/******************************************************************************/
-/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000)
-#define RTC_TR_HT ((uint32_t)0x00300000)
-#define RTC_TR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TR_HU ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TR_MNT ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TR_MNU ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TR_ST ((uint32_t)0x00000070)
-#define RTC_TR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TR_SU ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0 ((uint32_t)0x00100000)
-#define RTC_DR_YT_1 ((uint32_t)0x00200000)
-#define RTC_DR_YT_2 ((uint32_t)0x00400000)
-#define RTC_DR_YT_3 ((uint32_t)0x00800000)
-#define RTC_DR_YU ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0 ((uint32_t)0x00010000)
-#define RTC_DR_YU_1 ((uint32_t)0x00020000)
-#define RTC_DR_YU_2 ((uint32_t)0x00040000)
-#define RTC_DR_YU_3 ((uint32_t)0x00080000)
-#define RTC_DR_WDU ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_DR_MT ((uint32_t)0x00001000)
-#define RTC_DR_MU ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0 ((uint32_t)0x00000100)
-#define RTC_DR_MU_1 ((uint32_t)0x00000200)
-#define RTC_DR_MU_2 ((uint32_t)0x00000400)
-#define RTC_DR_MU_3 ((uint32_t)0x00000800)
-#define RTC_DR_DT ((uint32_t)0x00000030)
-#define RTC_DR_DT_0 ((uint32_t)0x00000010)
-#define RTC_DR_DT_1 ((uint32_t)0x00000020)
-#define RTC_DR_DU ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0 ((uint32_t)0x00000001)
-#define RTC_DR_DU_1 ((uint32_t)0x00000002)
-#define RTC_DR_DU_2 ((uint32_t)0x00000004)
-#define RTC_DR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000)
-#define RTC_CR_OSEL ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
-#define RTC_CR_POL ((uint32_t)0x00100000)
-#define RTC_CR_COSEL ((uint32_t)0x00080000)
-#define RTC_CR_BCK ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H ((uint32_t)0x00010000)
-#define RTC_CR_TSIE ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
-#define RTC_CR_TSE ((uint32_t)0x00000800)
-#define RTC_CR_WUTE ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE ((uint32_t)0x00000100)
-#define RTC_CR_DCE ((uint32_t)0x00000080)
-#define RTC_CR_FMT ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
-
-/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
-#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
-#define RTC_ISR_TSF ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
-#define RTC_ISR_INIT ((uint32_t)0x00000080)
-#define RTC_ISR_INITF ((uint32_t)0x00000040)
-#define RTC_ISR_RSF ((uint32_t)0x00000020)
-#define RTC_ISR_INITS ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
-
-/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CALIBR register ***************/
-#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
-
-/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_ALRMBR register ***************/
-#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF)
-
-/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
-
-/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000)
-#define RTC_TSTR_HT ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TSTR_HU ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TSTR_ST ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TSTR_SU ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_TSDR_MT ((uint32_t)0x00001000)
-#define RTC_TSDR_MU ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
-#define RTC_TSDR_DT ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
-#define RTC_TSDR_DU ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSSSR register ****************/
-#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CAL register *****************/
-#define RTC_CALR_CALP ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
-#define RTC_CALR_CALM ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
-
-/******************** Bits definition for RTC_TAFCR register ****************/
-#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_ALRMBSSR register *************/
-#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP5R register ****************/
-#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP6R register ****************/
-#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP7R register ****************/
-#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP8R register ****************/
-#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP9R register ****************/
-#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP10R register ***************/
-#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP11R register ***************/
-#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP12R register ***************/
-#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP13R register ***************/
-#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP14R register ***************/
-#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP15R register ***************/
-#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP16R register ***************/
-#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP17R register ***************/
-#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP18R register ***************/
-#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP19R register ***************/
-#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
-
-
-
-/******************************************************************************/
-/* */
-/* SD host Interface */
-/* */
-/******************************************************************************/
-/****************** Bit definition for SDIO_POWER register ******************/
-#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
-#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
-
-/****************** Bit definition for SDIO_CLKCR register ******************/
-#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
-#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
-#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
-#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
-
-#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
-
-/******************* Bit definition for SDIO_ARG register *******************/
-#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
-
-/******************* Bit definition for SDIO_CMD register *******************/
-#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
-
-#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
-#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
-
-#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
-#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
-
-/***************** Bit definition for SDIO_RESPCMD register *****************/
-#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
-
-/****************** Bit definition for SDIO_RESP0 register ******************/
-#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP1 register ******************/
-#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP2 register ******************/
-#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP3 register ******************/
-#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_RESP4 register ******************/
-#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
-
-/****************** Bit definition for SDIO_DTIMER register *****************/
-#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
-
-/****************** Bit definition for SDIO_DLEN register *******************/
-#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
-
-/****************** Bit definition for SDIO_DCTRL register ******************/
-#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
-#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
-#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
-#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
-
-#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
-#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
-#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
-#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
-
-/****************** Bit definition for SDIO_DCOUNT register *****************/
-#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
-
-/****************** Bit definition for SDIO_STA register ********************/
-#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
-#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
-#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
-#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
-#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
-#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
-#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
-#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
-#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
-#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
-#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
-#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
-#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
-
-/******************* Bit definition for SDIO_ICR register *******************/
-#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
-
-/****************** Bit definition for SDIO_MASK register *******************/
-#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/***************** Bit definition for SDIO_FIFOCNT register *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
-
-/****************** Bit definition for SDIO_FIFO register *******************/
-#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface */
-/* */
-/******************************************************************************/
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
-#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
-#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
-
-#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
-
-#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
-#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
-#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
-#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
-#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
-#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
-#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
-#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
-#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
-#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
-#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
-#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
-#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
-
-#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-
-#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
-
-/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/* */
-/* SYSCFG */
-/* */
-/******************************************************************************/
-/****************** Bit definition for SYSCFG_MEMRMP register ***************/
-#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
-#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
-#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
-
-/****************** Bit definition for SYSCFG_PMC register ******************/
-#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
-
-/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
-/**
- * @brief EXTI0 configuration
- */
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
-
-/**
- * @brief EXTI1 configuration
- */
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
-
-/**
- * @brief EXTI2 configuration
- */
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
-
-/**
- * @brief EXTI3 configuration
- */
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
-/**
- * @brief EXTI4 configuration
- */
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
-
-/**
- * @brief EXTI5 configuration
- */
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
-
-/**
- * @brief EXTI6 configuration
- */
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
-
-/**
- * @brief EXTI7 configuration
- */
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
-
-
-/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
-
-/**
- * @brief EXTI8 configuration
- */
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
-
-/**
- * @brief EXTI9 configuration
- */
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
-
-/**
- * @brief EXTI10 configuration
- */
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
-
-/**
- * @brief EXTI11 configuration
- */
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
-/**
- * @brief EXTI12 configuration
- */
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
-
-/**
- * @brief EXTI13 configuration
- */
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
-
-/**
- * @brief EXTI14 configuration
- */
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
-
-/**
- * @brief EXTI15 configuration
- */
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
-
-/****************** Bit definition for SYSCFG_CMPCR register ****************/
-#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/* */
-/* TIM */
-/* */
-/******************************************************************************/
-/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
-#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
-
-/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
-
-#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
-#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
-#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
-#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
-
-/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
-
-/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
-
-/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
-
-/******************* Bit definition for TIM_OR register *********************/
-#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
-#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
-
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/* */
-/******************************************************************************/
-/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
-#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
-#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
-#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
-#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
-#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
-#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
-#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
-#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
-#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
-
-/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
-#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
-#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
-#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
-#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
-#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
-#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
-#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
-#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
-#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
-#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
-#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
-#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
-#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
-
-#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
-#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
-
-#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
-#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
-#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
-#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
-#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
-#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
-#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
-#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
-#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
-#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
-#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
-#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
-#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
-#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
-#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
-
-#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG */
-/* */
-/******************************************************************************/
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
-#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
-#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
-#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
-#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
-#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
-#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
-
-#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
-#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
-#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
-#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
-#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
-#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
-#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
-
-#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/* */
-/* DBG */
-/* */
-/******************************************************************************/
-/******************** Bit definition for DBGMCU_IDCODE register *************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
-
-/******************** Bit definition for DBGMCU_CR register *****************/
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
-
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
-
-/******************** Bit definition for DBGMCU_APB1_FZ register ************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
-#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
-#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
-#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
-#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
-#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/******************** Bit definition for DBGMCU_APB2_FZ register ************/
-#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
-#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
-
-/******************************************************************************/
-/* */
-/* USB_OTG */
-/* */
-/******************************************************************************/
-/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
-#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
-
-/******************** Bit definition forUSB_OTG_HCFG register ********************/
-
-#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
-
-/******************** Bit definition forUSB_OTG_DCFG register ********************/
-
-#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
-#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
-
-#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
-
-#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-
-/******************** Bit definition forUSB_OTG_PCGCR register ********************/
-#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
-
-/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
-#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
-
-/******************** Bit definition forUSB_OTG_DCTL register ********************/
-#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
-
-/******************** Bit definition forUSB_OTG_HFIR register ********************/
-#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
-
-/******************** Bit definition forUSB_OTG_HFNUM register ********************/
-#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
-
-/******************** Bit definition forUSB_OTG_DSTS register ********************/
-#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
-
-/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
-#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
-
-#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
-
-/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
-
-#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
-
-/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
-#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
-
-#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
-
-/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
-#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
-
-/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
-
-#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
-
-/******************** Bit definition forUSB_OTG_HAINT register ********************/
-#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
-
-/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
-#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
-
-/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
-#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
-
-/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
-#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
-
-/******************** Bit definition forUSB_OTG_DAINT register ********************/
-#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
-
-/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
-#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
-
-/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
-#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
-
-/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
-#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
-
-/******************** Bit definition for OTG register ********************/
-
-#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
-#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
-
-#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
-#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
-#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
-
-#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
-#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
-#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
-
-/******************** Bit definition for OTG register ********************/
-
-#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
-#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
-
-#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
-#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
-#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
-
-#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
-#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
-
-#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
-#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
-#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
-#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
-
-/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
-#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
-
-/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
-
-/******************** Bit definition for OTG register ********************/
-#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
-
-/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
-
-/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
-
-/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
-
-/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
-#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
-
-/******************** Bit definition forUSB_OTG_GCCFG register ********************/
-#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
-
-/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
-
-/******************** Bit definition forUSB_OTG_CID register ********************/
-#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
-
-/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
-
-/******************** Bit definition forUSB_OTG_HPRT register ********************/
-#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
-#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
-
-#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-
-/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
-
-/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
-
-/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
-#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
-
-/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
-#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
-
-#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
-
-/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
-
-#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
-
-/******************** Bit definition forUSB_OTG_HCINT register ********************/
-#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
-#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
-
-/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
-#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
-
-/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
-#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
-
-/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
-/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
-
-/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
-#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
-
-/******************** Bit definition forUSB_OTG_HCDMA register ********************/
-#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
-
-/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
-
-/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
-
-/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
-
-/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
-#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
-
-/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
-
-/******************** Bit definition for PCGCCTL register ********************/
-#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_macros
- * @{
- */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
- ((INSTANCE) == DMA1_Stream1) || \
- ((INSTANCE) == DMA1_Stream2) || \
- ((INSTANCE) == DMA1_Stream3) || \
- ((INSTANCE) == DMA1_Stream4) || \
- ((INSTANCE) == DMA1_Stream5) || \
- ((INSTANCE) == DMA1_Stream6) || \
- ((INSTANCE) == DMA1_Stream7) || \
- ((INSTANCE) == DMA2_Stream0) || \
- ((INSTANCE) == DMA2_Stream1) || \
- ((INSTANCE) == DMA2_Stream2) || \
- ((INSTANCE) == DMA2_Stream3) || \
- ((INSTANCE) == DMA2_Stream4) || \
- ((INSTANCE) == DMA2_Stream5) || \
- ((INSTANCE) == DMA2_Stream6) || \
- ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE) || \
- ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
- ((INSTANCE) == I2C2) || \
- ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
- ((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == SPI4))
-
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
- ((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM9) || \
- ((INSTANCE) == TIM10) || \
- ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM9) || \
- ((INSTANCE) == TIM10) || \
- ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
- ((((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM2) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM3) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM4) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM5) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM9) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))) \
- || \
- (((INSTANCE) == TIM10) && \
- (((CHANNEL) == TIM_CHANNEL_1))) \
- || \
- (((INSTANCE) == TIM11) && \
- (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
- ((((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART6))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F401xE_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -80,9 +87,11 @@
STM32F439NI, STM32F429IG and STM32F429II Devices */
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
- /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
-#define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ #define STM32F401xC /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -139,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,406 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 13-March-2015
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.s Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.s Thu Apr 30 13:45:11 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f429xx.s * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief STM32F429xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f429xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -598,8 +598,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -1940,72 +1939,128 @@
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -3463,6 +3518,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3485,6 +3543,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3507,6 +3568,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3529,6 +3593,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3551,6 +3618,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3573,6 +3643,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3984,6 +4057,12 @@
#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4023,6 +4102,12 @@
#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@@ -4062,6 +4147,12 @@
#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4101,6 +4192,12 @@
#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4665,7 +4762,7 @@
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@@ -5572,7 +5669,7 @@
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -5879,7 +5976,11 @@
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@@ -6320,16 +6421,17 @@
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
-#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
-#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/
-#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@@ -8590,14 +8692,14 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
@@ -8885,6 +8987,20 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+
/******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,27 +63,35 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
-
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
-#define STM32F429xx /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ #define STM32F429xx /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
STM32F439NI, STM32F429IG and STM32F429II Devices */
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -95,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -140,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,406 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 13-March-2015
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,19 +2,19 @@
******************************************************************************
* @file stm32f411xe.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheralâs registers hardware
+ * - Macros to access peripherals registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -45,12 +45,12 @@
* @{
*/
-/** @addtogroup stm32f411xe
+/** @addtogroup stm32f401xe
* @{
*/
-#ifndef __STM32F411xE_H
-#define __STM32F411xE_H
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
#ifdef __cplusplus
extern "C" {
@@ -291,8 +291,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -1427,6 +1426,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1449,6 +1451,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1471,6 +1476,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1493,6 +1501,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1515,6 +1526,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1537,6 +1551,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4531,17 +4548,17 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/
@@ -4754,6 +4771,14 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -82,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
-#define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -139,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,405 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 26-December-2014
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f405xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -454,8 +454,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -1688,72 +1687,128 @@
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -3008,6 +3063,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3030,6 +3088,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3052,6 +3113,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3074,6 +3138,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3096,6 +3163,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3118,6 +3188,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3497,6 +3570,12 @@
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -3532,6 +3611,12 @@
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@@ -3567,6 +3652,12 @@
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -3602,6 +3693,12 @@
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4510,11 +4607,9 @@
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
@@ -4727,7 +4822,7 @@
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
@@ -7034,14 +7129,14 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@@ -7312,6 +7407,20 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+
/******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,15 +63,21 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
-
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
-#define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
+ #define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
@@ -83,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -95,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -140,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,407 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 13-March-2015
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 0 /* The prefetch will be enabled in SystemClock_Config(), depending on the used
+ STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s Thu Apr 30 13:45:11 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f411xe.s * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,19 +2,19 @@
******************************************************************************
* @file stm32f411xe.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheralâs registers hardware
+ * - Macros to access peripherals registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -45,12 +45,12 @@
* @{
*/
-/** @addtogroup stm32f411xe
+/** @addtogroup stm32f401xe
* @{
*/
-#ifndef __STM32F411xE_H
-#define __STM32F411xE_H
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
#ifdef __cplusplus
extern "C" {
@@ -291,8 +291,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -1427,6 +1426,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1449,6 +1451,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1471,6 +1476,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1493,6 +1501,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1515,6 +1526,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1537,6 +1551,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4531,17 +4548,17 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/
@@ -4754,6 +4771,14 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -82,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
-#define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -139,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,405 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 26-December-2014
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.s Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.s Thu Apr 30 13:45:11 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f401xe.s * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief STM32F401xExx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f401xe.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -290,8 +290,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -1423,6 +1422,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1445,6 +1447,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1467,6 +1472,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1489,6 +1497,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1511,6 +1522,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1533,6 +1547,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4511,14 +4528,14 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -4728,6 +4745,14 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -81,8 +88,10 @@
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
-#define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ #define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -139,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,405 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 26-December-2014
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s Thu Apr 30 13:45:11 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f411xe.s * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,19 +2,19 @@
******************************************************************************
* @file stm32f411xe.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheralâs registers hardware
+ * - Macros to access peripherals registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -45,12 +45,12 @@
* @{
*/
-/** @addtogroup stm32f411xe
+/** @addtogroup stm32f401xe
* @{
*/
-#ifndef __STM32F411xE_H
-#define __STM32F411xE_H
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
#ifdef __cplusplus
extern "C" {
@@ -291,8 +291,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -1427,6 +1426,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1449,6 +1451,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1471,6 +1476,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1493,6 +1501,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1515,6 +1526,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1537,6 +1551,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4531,17 +4548,17 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/
@@ -4754,6 +4771,14 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -82,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
-#define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -139,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,405 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 26-December-2014
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.s Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.s Thu Apr 30 13:45:11 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f407xx.s * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief STM32F407xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f407xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -549,8 +549,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -1790,72 +1789,128 @@
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -3164,6 +3219,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3186,6 +3244,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3208,6 +3269,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3230,6 +3294,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3252,6 +3319,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3274,6 +3344,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3653,6 +3726,12 @@
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -3688,6 +3767,12 @@
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@@ -3723,6 +3808,12 @@
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -3758,6 +3849,12 @@
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4666,11 +4763,9 @@
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
@@ -4884,7 +4979,7 @@
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -7638,14 +7733,14 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@@ -7916,6 +8011,20 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+
/******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0RC2
- * @date 14-May-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,17 +63,23 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
-
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
- #define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ #define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
@@ -83,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -95,20 +103,20 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0RC2
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x02) /*!< [7:0] release candidate */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
- |(__CMSIS_DEVICE_HAL_VERSION_RC))
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_DEVICE_VERSION))
/**
* @}
@@ -140,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,407 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 13-March-2015
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 0 /* The prefetch will be enabled in SystemClock_Config(), depending on the used
+ STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0RC2 - * @date 14-May-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s Thu Apr 30 13:45:11 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32f439xx.s * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -567,4 +567,4 @@ - \ No newline at end of file +
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f439xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -599,8 +599,7 @@
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -2015,72 +2014,128 @@
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -3592,6 +3647,9 @@
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3614,6 +3672,9 @@
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3636,6 +3697,9 @@
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3658,6 +3722,9 @@
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3680,6 +3747,9 @@
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3702,6 +3772,9 @@
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4113,6 +4186,12 @@
#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4152,6 +4231,12 @@
#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@@ -4191,6 +4276,12 @@
#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4230,6 +4321,12 @@
#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@@ -4794,7 +4891,7 @@
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@@ -5744,7 +5841,7 @@
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -6059,7 +6156,11 @@
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@@ -6500,16 +6601,17 @@
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
-#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
-#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/
-#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@@ -8770,14 +8872,14 @@
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3) || \
- ((INSTANCE) == I2S2ext) || \
- ((INSTANCE) == I2S3ext))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
@@ -9065,6 +9167,20 @@
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+
/******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 19-June-2014
+ * @version V2.3.0
+ * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,14 +63,20 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
-
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -79,11 +85,13 @@
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
STM32F439NI, STM32F429IG and STM32F429II Devices */
-#define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ #define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -95,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
-#define USE_HAL_DRIVER
+ #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
+ * @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -140,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx_hal_conf.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,406 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 13-March-2015
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h Thu Apr 30 13:00:08 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h Thu Apr 30 13:45:11 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); - /** * @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,2307 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE ((uint32_t)0x00000000)
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR ((uint32_t)0x00000100)
+#define ETH_MMCRIR ((uint32_t)0x00000104)
+#define ETH_MMCTIR ((uint32_t)0x00000108)
+#define ETH_MMCRIMR ((uint32_t)0x0000010C)
+#define ETH_MMCTIMR ((uint32_t)0x00000110)
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
+#define ETH_MMCTGFCR ((uint32_t)0x00000168)
+#define ETH_MMCRFCECR ((uint32_t)0x00000194)
+#define ETH_MMCRFAECR ((uint32_t)0x00000198)
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+#define IS_PWR_REGULATOR_VOLTAGE IS_PWR_VOLTAGE_SCALING_RANGE
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
+#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
+#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,18 +57,21 @@
* @{
*/
-/** @defgroup HAL
+/** @defgroup HAL HAL
* @brief HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Constants
+ * @{
+ */
/**
- * @brief STM32F4xx HAL Driver version number V1.1.0
- */
+ * @brief STM32F4xx HAL Driver version number V1.3.0
+ */
#define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24)\
@@ -83,26 +86,35 @@
/* --- MEMRMP Register ---*/
/* Alias word address of UFB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
-#define UFB_MODE_BitNumber ((uint8_t)0x8)
-#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
+#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
+#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4))
/* --- CMPCR Register ---*/
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
-#define CMP_PD_BitNumber ((uint8_t)0x00)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
+#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
+#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Private_Variables
+ * @{
+ */
static __IO uint32_t uwTick;
-
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Functions
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
-/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -150,7 +162,6 @@
* @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
@@ -184,26 +195,25 @@
/**
* @brief This function de-Initializes common part of the HAL and stops the systick.
* This function is optional.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
- __APB1_FORCE_RESET();
- __APB1_RELEASE_RESET();
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
- __APB2_FORCE_RESET();
- __APB2_RELEASE_RESET();
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
- __AHB1_FORCE_RESET();
- __AHB1_RELEASE_RESET();
+ __HAL_RCC_AHB1_FORCE_RESET();
+ __HAL_RCC_AHB1_RELEASE_RESET();
- __AHB2_FORCE_RESET();
- __AHB2_RELEASE_RESET();
+ __HAL_RCC_AHB2_FORCE_RESET();
+ __HAL_RCC_AHB2_RELEASE_RESET();
- __AHB3_FORCE_RESET();
- __AHB3_RELEASE_RESET();
+ __HAL_RCC_AHB3_FORCE_RESET();
+ __HAL_RCC_AHB3_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
@@ -214,7 +224,6 @@
/**
* @brief Initializes the MSP.
- * @param None
* @retval None
*/
__weak void HAL_MspInit(void)
@@ -226,7 +235,6 @@
/**
* @brief DeInitializes the MSP.
- * @param None
* @retval None
*/
__weak void HAL_MspDeInit(void)
@@ -268,7 +276,7 @@
* @}
*/
-/** @defgroup HAL_Group2 HAL Control functions
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
@@ -298,7 +306,6 @@
* in Systick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval None
*/
__weak void HAL_IncTick(void)
@@ -310,7 +317,6 @@
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
@@ -324,7 +330,7 @@
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
- * @note ThiS function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @retval None
@@ -342,11 +348,10 @@
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval None
*/
__weak void HAL_SuspendTick(void)
@@ -359,11 +364,10 @@
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval None
*/
__weak void HAL_ResumeTick(void)
@@ -374,7 +378,6 @@
/**
* @brief Returns the HAL revision
- * @param None
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
@@ -384,7 +387,6 @@
/**
* @brief Returns the device revision identifier.
- * @param None
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
@@ -394,7 +396,6 @@
/**
* @brief Returns the device identifier.
- * @param None
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
@@ -404,60 +405,54 @@
/**
* @brief Enable the Debug Module during SLEEP mode
- * @param None
* @retval None
*/
-void HAL_EnableDBGSleepMode(void)
+void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
- * @param None
* @retval None
*/
-void HAL_DisableDBGSleepMode(void)
+void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
- * @param None
* @retval None
*/
-void HAL_EnableDBGStopMode(void)
+void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
- * @param None
* @retval None
*/
-void HAL_DisableDBGStopMode(void)
+void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
- * @param None
* @retval None
*/
-void HAL_EnableDBGStandbyMode(void)
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
- * @param None
* @retval None
*/
-void HAL_DisableDBGStandbyMode(void)
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -58,102 +58,119 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
-#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_FREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_FREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_FREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_FREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_FREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_UNFREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_UNFREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_UNFREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_UNFREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_UNFREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
/** @brief Main Flash memory mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
/** @brief System Flash memory mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+ }while(0);
/** @brief Embedded SRAM mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
+ }while(0);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+ * @}
+ */
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
@@ -163,23 +180,45 @@
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
-void HAL_EnableDBGSleepMode(void);
-void HAL_DisableDBGSleepMode(void);
-void HAL_EnableDBGStopMode(void);
-void HAL_DisableDBGStopMode(void);
-void HAL_EnableDBGStandbyMode(void);
-void HAL_DisableDBGStandbyMode(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
void HAL_EnableMemorySwappingBank(void);
void HAL_DisableMemorySwappingBank(void);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
+/**
+ * @}
+ */
/**
* @}
- */
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@@ -36,35 +36,56 @@
##### How to use this driver #####
==============================================================================
- [..]
- (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
- (##) Enable the ADC interface clock using __ADC_CLK_ENABLE()
+ [..]
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
- __GPIOx_CLK_ENABLE()
+ __HAL_RCC_GPIOx_CLK_ENABLE()
(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams stream for managing data
transfer from peripheral to memory (output stream)
- (+++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
- (#) Configure the ADC Prescaler, conversion resolution and data alignment
- using the HAL_ADC_Init() function.
-
- (#) Configure the ADC regular channels group features, use HAL_ADC_Init()
- and HAL_ADC_ConfigChannel() functions.
-
- (#) Three operation modes are available within this driver :
-
+ *** Configuration of ADC, groups regular/injected, channels parameters ***
+ ==============================================================================
+ [..]
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the injected group parameters (conversion trigger,
+ sequencer, ..., of injected group)
+ and the channels for injected group parameters (channel number,
+ channel rank into sequencer, ..., into injected group)
+ using function HAL_ADCEx_InjectedConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
+
+ (#) Optionally, for devices with several ADC instances: configure the
+ multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
+
+ *** Execution of ADC conversions ***
+ ==============================================================================
+ [..]
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
*** Polling mode IO operation ***
=================================
[..]
@@ -80,10 +101,10 @@
(+) Start the ADC peripheral using HAL_ADC_Start_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
(+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ErrorCallback
- (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
*** DMA mode IO operation ***
==============================
@@ -91,9 +112,9 @@
(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
(+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
*** ADC HAL driver macros list ***
@@ -108,16 +129,42 @@
(+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
(+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
(+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
- (+) __HAL_ADC_GET_RESOLUTION: Return resolution bits in CR1 register
+ (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
[..]
- (@) You can refer to the ADC HAL driver header file for more useful macros
-
+ (@) You can refer to the ADC HAL driver header file for more useful macros
+
+ *** Deinitialization of ADC ***
+ ==============================================================================
+ [..]
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
+ (++) ADC clock disable using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA using function HAL_DMA_DeInit().
+ (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -151,7 +198,7 @@
* @{
*/
-/** @defgroup ADC
+/** @defgroup ADC ADC
* @brief ADC driver modules
* @{
*/
@@ -159,21 +206,26 @@
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void ADC_Init(ADC_HandleTypeDef* hadc);
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and de-initialization functions
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -217,16 +269,22 @@
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ }
if(hadc->State == HAL_ADC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
}
@@ -313,7 +371,7 @@
* @}
*/
-/** @defgroup ADC_Group2 IO operation functions
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -341,7 +399,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -363,24 +421,29 @@
}
/* Check if ADC peripheral is disabled in order to enable it and wait during
- Tstab time the ADC's stabilization */
+ Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
-
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
- if(hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -389,16 +452,13 @@
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if((hadc->Instance == ADC1) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -427,6 +487,14 @@
/**
* @brief Poll for regular conversion complete
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function.
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param Timeout: Timeout value in millisecond.
@@ -436,6 +504,24 @@
{
uint32_t tickstart = 0;
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and polling for end of each conversion. */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
+ HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
/* Get tick */
tickstart = HAL_GetTick();
@@ -477,8 +563,8 @@
* the configuration information for the specified ADC.
* @param EventType: the ADC event type.
* This parameter can be one of the following values:
- * @arg AWD_EVENT: ADC Analog watch Dog event.
- * @arg OVR_EVENT: ADC Overrun event.
+ * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
+ * @arg ADC_OVR_EVENT: ADC Overrun event.
* @param Timeout: Timeout value in millisecond.
* @retval HAL status
*/
@@ -509,7 +595,7 @@
}
/* Check analog watchdog flag */
- if(EventType == AWD_EVENT)
+ if(EventType == ADC_AWD_EVENT)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_AWD;
@@ -539,7 +625,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -570,10 +656,12 @@
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
@@ -583,11 +671,14 @@
/* Enable the ADC end of conversion interrupt for regular group */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
- /* if no externel trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -596,16 +687,13 @@
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if ((hadc->Instance == (ADC_TypeDef*)0x40012000) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
+
/* Return function status */
return HAL_OK;
}
@@ -627,7 +715,7 @@
/* Disable the ADC end of conversion interrupt for injected group */
__HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
- /* Enable the Periphral */
+ /* Enable the Peripheral */
__HAL_ADC_DISABLE(hadc);
/* Change ADC state */
@@ -669,9 +757,9 @@
hadc->State = HAL_ADC_STATE_EOC_REG;
}
- if((hadc->Init.ContinuousConvMode == DISABLE) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
- if(hadc->Init.EOCSelection == EOC_SEQ_CONV)
+ if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
/* DISABLE the ADC end of conversion interrupt for regular group */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
@@ -784,7 +872,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -813,7 +901,10 @@
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
-
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -821,23 +912,22 @@
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
/* if no external trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= ADC_CR2_SWSTART;
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -850,7 +940,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
- /* Disable the Periphral */
+ /* Disable the Peripheral */
__HAL_ADC_DISABLE(hadc);
/* Disable ADC overrun interrupt */
@@ -937,7 +1027,7 @@
* @}
*/
-/** @defgroup ADC_Group3 Peripheral Control functions
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -964,6 +1054,8 @@
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
+ __IO uint32_t counter = 0;
+
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
@@ -976,46 +1068,46 @@
if (sConfig->Channel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
- hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
/* Set the new sample time */
- hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
- hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
/* Set the new sample time */
- hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
{
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->SQR3 &= ~__HAL_ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
+ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
/* Set the SQx bits for the selected rank */
- hadc->Instance->SQR3 |= __HAL_ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
+ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
{
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->SQR2 &= ~__HAL_ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
+ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
/* Set the SQx bits for the selected rank */
- hadc->Instance->SQR2 |= __HAL_ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
+ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->SQR1 &= ~__HAL_ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
+ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
/* Set the SQx bits for the selected rank */
- hadc->Instance->SQR1 |= __HAL_ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
+ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
@@ -1030,6 +1122,17 @@
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
+
+ if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
+ {
+ counter--;
+ }
+ }
}
/* Process unlocked */
@@ -1059,7 +1162,7 @@
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
#ifdef USE_FULL_ASSERT
- tmp = __HAL_ADC_GET_RESOLUTION(hadc);
+ tmp = ADC_GET_RESOLUTION(hadc);
assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
#endif /* USE_FULL_ASSERT */
@@ -1094,7 +1197,7 @@
hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
/* Set the Analog watchdog channel */
- hadc->Instance->CR1 |= AnalogWDGConfig->Channel;
+ hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -1107,7 +1210,7 @@
* @}
*/
-/** @defgroup ADC_Group4 ADC Peripheral State functions
+/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
* @brief ADC Peripheral State functions
*
@verbatim
@@ -1150,6 +1253,10 @@
* @}
*/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
/**
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct without initializing the ADC MSP.
@@ -1159,7 +1266,6 @@
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
-
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
@@ -1167,7 +1273,7 @@
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
- hadc->Instance->CR1 |= __HAL_ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
+ hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
@@ -1177,19 +1283,33 @@
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
hadc->Instance->CR2 |= hadc->Init.DataAlign;
- /* Select external trigger to start conversion */
- hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
- hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
-
- /* Select external trigger polarity */
- hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
- hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
+
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ }
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
- hadc->Instance->CR2 |= __HAL_ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
+ hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
- if (hadc->Init.DiscontinuousConvMode != DISABLE)
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
@@ -1198,7 +1318,7 @@
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
- hadc->Instance->CR1 |= __HAL_ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
+ hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
}
else
{
@@ -1208,15 +1328,15 @@
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
- hadc->Instance->SQR1 |= __HAL_ADC_SQR1(hadc->Init.NbrOfConversion);
+ hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
- hadc->Instance->CR2 |= __HAL_ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
+ hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
- hadc->Instance->CR2 |= __HAL_ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
+ hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
}
/**
@@ -1241,7 +1361,7 @@
hadc->State = HAL_ADC_STATE_EOC_REG;
}
- HAL_ADC_ConvCpltCallback(hadc);
+ HAL_ADC_ConvCpltCallback(hadc);
}
/**
@@ -1252,9 +1372,9 @@
*/
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_ADC_ConvHalfCpltCallback(hadc);
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
}
/**
@@ -1265,13 +1385,16 @@
*/
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hadc->State= HAL_ADC_STATE_ERROR;
- /* Set ADC error code to DMA error */
- hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
- HAL_ADC_ErrorCallback(hadc);
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hadc->State= HAL_ADC_STATE_ERROR;
+ /* Set ADC error code to DMA error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+ HAL_ADC_ErrorCallback(hadc);
}
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,9 +55,12 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
/**
- * @brief HAL State structures definition
+ * @brief HAL State structures definition
*/
typedef enum
{
@@ -78,7 +81,7 @@
}HAL_ADC_StateTypeDef;
/**
- * @brief ADC Init structure definition
+ * @brief ADC Init structure definition
*/
typedef struct
{
@@ -108,14 +111,18 @@
uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
using the sequencer for regular channel group.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
- This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
- uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
- This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular
+ Note: This parameter can be modified only if there is no conversion is ongoing. */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular
+ Note: This parameter can be modified only if there is no conversion is ongoing. */
}ADC_InitTypeDef;
/**
- * @brief ADC handle Structure definition
+ * @brief ADC handle Structure definition
*/
typedef struct
{
@@ -135,7 +142,7 @@
}ADC_HandleTypeDef;
/**
- * @brief ADC Configuration regular Channel structure definition
+ * @brief ADC Configuration regular Channel structure definition
*/
typedef struct
{
@@ -149,7 +156,7 @@
}ADC_ChannelConfTypeDef;
/**
- * @brief ADC Configuration multi-mode structure definition
+ * @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
@@ -167,18 +174,18 @@
This parameter can be set to ENABLE or DISABLE */
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
}ADC_AnalogWDGConfTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
-
-/** @defgroup ADC_Error_Code
+/** @defgroup ADC_Error_Code ADC Error Code
* @{
- */
-
+ */
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
@@ -187,22 +194,18 @@
*/
-/** @defgroup ADC_ClockPrescaler
+/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
/**
* @}
*/
-/** @defgroup ADC_delay_between_2_sampling_phases
+/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
@@ -221,62 +224,37 @@
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
-
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
/**
* @}
*/
-/** @defgroup ADC_Resolution
+/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
-#define ADC_RESOLUTION12b ((uint32_t)0x00000000)
-#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0)
-#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1)
-#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES)
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
- ((RESOLUTION) == ADC_RESOLUTION10b) || \
- ((RESOLUTION) == ADC_RESOLUTION8b) || \
- ((RESOLUTION) == ADC_RESOLUTION6b))
+#define ADC_RESOLUTION_12B ((uint32_t)0x00000000)
+#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
+#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
+#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
/**
* @}
*/
-/** @defgroup ADC_External_trigger_edge_Regular
+/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
-
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
/**
* @}
*/
-/** @defgroup ADC_External_trigger_Source_Regular
+/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
* @{
- */
+ */
+/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
+/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
@@ -293,40 +271,21 @@
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
-
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
+#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
/**
* @}
*/
-/** @defgroup ADC_data_align
+/** @defgroup ADC_data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT))
/**
* @}
*/
-/** @defgroup ADC_channels
+/** @defgroup ADC_channels ADC Common Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
@@ -349,34 +308,13 @@
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
-#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_16) || \
- ((CHANNEL) == ADC_CHANNEL_17) || \
- ((CHANNEL) == ADC_CHANNEL_18))
+#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
/**
* @}
*/
-/** @defgroup ADC_sampling_times
+/** @defgroup ADC_sampling_times ADC Sampling Times
* @{
*/
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
@@ -387,46 +325,30 @@
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_480CYCLES))
/**
* @}
*/
- /** @defgroup ADC_EOCSelection
+ /** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
-#define EOC_SEQ_CONV ((uint32_t)0x00000000)
-#define EOC_SINGLE_CONV ((uint32_t)0x00000001)
-#define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
-
-#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) || \
- ((EOCSelection) == EOC_SEQ_CONV) || \
- ((EOCSelection) == EOC_SINGLE_SEQ_CONV))
+#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
+#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
+#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
/**
* @}
*/
-/** @defgroup ADC_Event_type
+/** @defgroup ADC_Event_type ADC Event Type
* @{
*/
-#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
-#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
- ((EVENT) == OVR_EVENT))
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
+#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
/**
* @}
*/
-/** @defgroup ADC_analog_watchdog_selection
+/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
* @{
*/
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
@@ -436,33 +358,22 @@
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
-
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
/**
* @}
*/
-/** @defgroup ADC_interrupts_definition
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
* @{
*/
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
-
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
- ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
/**
* @}
*/
-/** @defgroup ADC_flags_definition
+/** @defgroup ADC_flags_definition ADC Flags Definition
* @{
*/
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
@@ -475,69 +386,24 @@
* @}
*/
-/** @defgroup ADC_channels_type
+/** @defgroup ADC_channels_type ADC Channels Type
* @{
*/
-#define ALL_CHANNELS ((uint32_t)0x00000001)
-#define REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
-#define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
-
-#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
- ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
- ((CHANNEL_TYPE) == INJECTED_CHANNELS))
+#define ADC_ALL_CHANNELS ((uint32_t)0x00000001)
+#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
+#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
/**
* @}
*/
-/** @defgroup ADC_thresholds
- * @{
- */
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_length
- * @{
- */
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_rank
- * @{
- */
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_discontinuous_mode_number
- * @{
- */
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
-/**
- * @}
- */
-
-/** @defgroup ADC_range_verification
- * @{
- */
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
-/**
- * @}
- */
-
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
/** @brief Reset ADC handle state
* @param __HANDLE__: ADC handle
@@ -560,88 +426,6 @@
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
/**
- * @brief Set ADC Regular channel sequence length.
- * @param _NbrOfConversion_: Regular channel sequence length.
- * @retval None
- */
-#define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 10 and 18.
- * @param _SAMPLETIME_: Sample time parameter.
- * @param _CHANNELNB_: Channel number.
- * @retval None
- */
-#define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 0 and 9.
- * @param _SAMPLETIME_: Sample time parameter.
- * @param _CHANNELNB_: Channel number.
- * @retval None
- */
-#define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 1 and 6.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @retval None
- */
-#define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 7 and 12.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @retval None
- */
-#define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 13 and 16.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @retval None
- */
-#define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
-
-/**
- * @brief Enable ADC continuous conversion mode.
- * @param _CONTINUOUS_MODE_: Continuous mode.
- * @retval None
- */
-#define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
-
-/**
- * @brief Configures the number of discontinuous conversions for the regular group channels.
- * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
- * @retval None
- */
-#define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
-
-/**
- * @brief Enable ADC scan mode.
- * @param _SCANCONV_MODE_: Scan conversion mode.
- * @retval None
- */
-#define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
-
-/**
- * @brief Enable the ADC end of conversion selection.
- * @param _EOCSelection_MODE_: End of conversion selection mode.
- * @retval None
- */
-#define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
-
-/**
- * @brief Enable the ADC DMA continuous request.
- * @param _DMAContReq_MODE_: DMA continuous request mode.
- * @retval None
- */
-#define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
-
-/**
* @brief Enable the ADC end of conversion interrupt.
* @param __HANDLE__: specifies the ADC Handle.
* @param __INTERRUPT__: ADC Interrupt.
@@ -662,7 +446,7 @@
* @param __INTERRUPT__: specifies the ADC interrupt source to check.
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clear the ADC's pending flags.
@@ -681,22 +465,32 @@
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/**
- * @brief Return resolution bits in CR1 register.
- * @param __HANDLE__: ADC handle
- * @retval None
+ * @}
*/
-#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
/* Include ADC HAL Extension module */
#include "stm32f4xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions ***********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
@@ -707,25 +501,248 @@
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+/** @addtogroup ADC_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral State functions ***************************************************/
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+/* Delay for ADC stabilization time. */
+/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+/* Unit: us */
+#define ADC_STAB_DELAY_US ((uint32_t) 3)
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B))
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT))
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_480CYCLES))
+#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
+ ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
+ ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT))
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
+ ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
+ ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+
+/**
+ * @brief Set ADC Regular channel sequence length.
+ * @param _NbrOfConversion_: Regular channel sequence length.
+ * @retval None
+ */
+#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
+
+/**
+ * @brief Enable ADC scan mode.
+ * @param _SCANCONV_MODE_: Scan conversion mode.
+ * @retval None
+ */
+#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
+
+/**
+ * @brief Enable the ADC end of conversion selection.
+ * @param _EOCSelection_MODE_: End of conversion selection mode.
+ * @retval None
+ */
+#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMAContReq_MODE_: DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
+
+/**
+ * @brief Return resolution bits in CR1 register.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@@ -14,20 +14,20 @@
==============================================================================
[..]
(#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
- (##) Enable the ADC interface clock using __ADC_CLK_ENABLE()
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
- __GPIOx_CLK_ENABLE()
+ __HAL_RCC_GPIOx_CLK_ENABLE()
(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams stream for managing data
transfer from peripheral to memory (output stream)
- (+++) Associate the initilalized DMA handle to the ADC DMA handle
+ (+++) Associate the initialized DMA handle to the ADC DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
@@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -120,7 +120,7 @@
* @{
*/
-/** @defgroup ADCEx
+/** @defgroup ADCEx ADCEx
* @brief ADC Extended driver modules
* @{
*/
@@ -131,19 +131,25 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADCEx_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup ADCEx_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
* @{
- */
+ */
-/** @defgroup ADCEx_Group1 Extended features functions
- * @brief Extended features functions
- *
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -170,7 +176,8 @@
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
{
- uint32_t i = 0, tmp1 = 0, tmp2 = 0;
+ __IO uint32_t counter = 0;
+ uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
@@ -194,10 +201,12 @@
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
@@ -239,7 +248,8 @@
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
- uint32_t i = 0, tmp1 = 0, tmp2 =0;
+ __IO uint32_t counter = 0;
+ uint32_t tmp1 = 0, tmp2 =0;
/* Process locked */
__HAL_LOCK(hadc);
@@ -266,10 +276,12 @@
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
@@ -392,7 +404,7 @@
/* Disable the ADC end of conversion interrupt for injected group */
__HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
- /* Enable the Periphral */
+ /* Enable the Peripheral */
__HAL_ADC_DISABLE(hadc);
/* Change ADC state */
@@ -466,7 +478,7 @@
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- uint16_t counter = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -512,15 +524,17 @@
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; counter <= 540; counter++)
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
/* if no external trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -618,7 +632,7 @@
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
#ifdef USE_FULL_ASSERT
- tmp = __HAL_ADC_GET_RESOLUTION(hadc);
+ tmp = ADC_GET_RESOLUTION(hadc);
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
@@ -629,31 +643,31 @@
if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
- hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
/* Set the new sample time */
- hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
- hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
/* Set the new sample time */
- hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
/*---------------------------- ADCx JSQR Configuration -----------------*/
hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
- hadc->Instance->JSQR |= __HAL_ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+ hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
/* Rank configuration */
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->JSQR &= ~__HAL_ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+ hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Set the SQx bits for the selected rank */
- hadc->Instance->JSQR |= __HAL_ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -1,14 +1,14 @@
/**
******************************************************************************
- * @file stm32f4xx_hal_adc.h
+ * @file stm32f4xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,9 +55,12 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Exported Types
+ * @{
+ */
/**
- * @brief ADC Configuration injected Channel structure definition
+ * @brief ADC Configuration injected Channel structure definition
*/
typedef struct
{
@@ -83,7 +86,7 @@
}ADC_InjectionConfTypeDef;
/**
- * @brief ADC Configuration multi-mode structure definition
+ * @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
@@ -95,14 +98,16 @@
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
}ADC_MultiModeTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup ADCEx_Exported_Constants
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
* @{
*/
-
-/** @defgroup ADCEx_Common_mode
+/** @defgroup ADCEx_Common_mode ADC Common Mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
@@ -118,57 +123,33 @@
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT) || \
- ((MODE) == ADC_DUALMODE_INTERL) || \
- ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
- ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_INTERL) || \
- ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
/**
* @}
*/
-/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
- ((MODE) == ADC_DMAACCESSMODE_1) || \
- ((MODE) == ADC_DMAACCESSMODE_2) || \
- ((MODE) == ADC_DMAACCESSMODE_3))
/**
* @}
*/
-/** @defgroup ADCEx_External_trigger_edge_Injected
+/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
-
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
/**
* @}
*/
-/** @defgroup ADCEx_External_trigger_Source_Injected
+/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000)
@@ -187,7 +168,129 @@
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
+/**
+ * @}
+ */
+/** @defgroup ADCEx_injected_channel_selection ADC Injected Channel Selection
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_channels ADC Specific Channels
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Macros ADC Private Macros
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERL) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
+ ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_INTERL) || \
+ ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((MODE) == ADC_DMAACCESSMODE_1) || \
+ ((MODE) == ADC_DMAACCESSMODE_2) || \
+ ((MODE) == ADC_DMAACCESSMODE_3))
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
@@ -204,43 +307,8 @@
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_injected_channel_selection
- * @{
- */
-#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_injected_length
- * @{
- */
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_injected_rank
- * @{
- */
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
/**
* @brief Set the selected injected Channel rank.
@@ -249,26 +317,20 @@
* @param _JSQR_JL_: Sequence length.
* @retval None
*/
-#define __HAL_ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) \
-((_CHANNELNB_) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
-/* Exported functions --------------------------------------------------------*/
+/**
+ * @}
+ */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Functions ADC Private Functions
+ * @{
+ */
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@@ -17,7 +17,7 @@
==============================================================================
[..]
(#) Enable the CAN controller interface clock using
- __CAN1_CLK_ENABLE() for CAN1 and __CAN1_CLK_ENABLE() for CAN2
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
-@- In case you are using CAN2 only, you have to enable the CAN1 clock.
(#) CAN pins configuration
@@ -26,11 +26,11 @@
(++) Connect and configure the involved CAN pins to AF9 using the
following function HAL_GPIO_Init()
- (#) Initialise and configure the CAN using CAN_Init() function.
+ (#) Initialize and configure the CAN using CAN_Init() function.
(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
- (#) Receive a CAN frame using HAL_CAN_Recieve() function.
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
*** Polling mode IO operation ***
=================================
@@ -72,7 +72,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -106,30 +106,44 @@
* @{
*/
-/** @defgroup CAN
+/** @defgroup CAN CAN
* @brief CAN driver modules
* @{
*/
#ifdef HAL_CAN_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup CAN_Private_Constants
+ * @{
+ */
#define CAN_TIMEOUT_VALUE 10
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup CAN_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @defgroup CAN_Group1 Initialization and de-initialization functions
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -179,6 +193,8 @@
if(hcan->State == HAL_CAN_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CAN_MspInit(hcan);
}
@@ -498,7 +514,7 @@
* @}
*/
-/** @defgroup CAN_Group2 IO operation functions
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -641,7 +657,10 @@
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
-
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_ERROR;
}
@@ -969,6 +988,9 @@
/* Sleep mode status */
if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
{
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_ERROR;
}
@@ -1034,6 +1056,9 @@
}
if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
{
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_ERROR;
}
@@ -1219,7 +1244,7 @@
* @}
*/
-/** @defgroup CAN_Group3 Peripheral State and Error functions
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
@verbatim
@@ -1399,7 +1424,7 @@
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_CAN_MODULE_ENABLED */
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,9 @@
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -56,52 +58,55 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
-/**
- * @brief HAL State structures definition
- */
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
}HAL_CAN_StateTypeDef;
-/**
+/**
* @brief CAN init structure definition
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
-
+
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
+
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
+
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
-
+
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE */
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
@@ -114,33 +119,33 @@
This parameter can be set to ENABLE or DISABLE */
}CAN_InitTypeDef;
-/**
+/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
@@ -151,50 +156,50 @@
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
-
+
uint32_t BankNumber; /*!< Select the start slave bank filter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+
}CAN_FilterConfTypeDef;
-/**
- * @brief CAN Tx message structure definition
+/**
+ * @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
+ This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
+ This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
+
}CanTxMsgTypeDef;
-/**
- * @brief CAN Rx message structure definition
+/**
+ * @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_identifier_type */
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
@@ -202,49 +207,52 @@
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint32_t Data[8]; /*!< Contains the data to be received.
+ uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
+
}CanRxMsgTypeDef;
-/**
- * @brief CAN handle Structure definition
- */
+/**
+ * @brief CAN handle Structure definition
+ */
typedef struct
{
CAN_TypeDef *Instance; /*!< Register base address */
-
+
CAN_InitTypeDef Init; /*!< CAN required parameters */
-
+
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
-
+
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
-
+
HAL_LockTypeDef Lock; /*!< CAN locking object */
-
+
__IO uint32_t ErrorCode; /*!< CAN Error code */
-
+
}CAN_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup CAN_Exported_Constants
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
-/** @defgroup HAL CAN Error Code
+/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */
-#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
+#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */
@@ -255,10 +263,9 @@
#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */
/**
* @}
- */
+ */
-
-/** @defgroup CAN_InitStatus
+/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
@@ -267,38 +274,29 @@
* @}
*/
-/** @defgroup CAN_operating_mode
+/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
/**
* @}
*/
-
-/** @defgroup CAN_synchronisation_jump_width
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
* @{
*/
#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
/**
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_1
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
* @{
*/
#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
@@ -317,13 +315,11 @@
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
/**
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
@@ -334,138 +330,70 @@
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
/**
* @}
*/
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
/**
* @}
*/
-/** @defgroup CAN_filter_scale
+/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
/**
* @}
*/
-/** @defgroup CAN_filter_FIFO
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
/**
* @}
*/
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN
+/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
/**
* @}
*/
-/** @defgroup CAN_Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
- * @{
- */
-#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants
- * @{
- */
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
-#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-
/**
* @}
*/
-/** @defgroup CAN_receive_FIFO_number_constants
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/**
* @}
*/
-/** @defgroup CAN_flags
+/** @defgroup CAN_flags CAN Flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
@@ -490,35 +418,20 @@
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
-
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU))
/**
* @}
*/
-
-/** @defgroup CAN_interrupts
+/** @defgroup CAN_Interrupts CAN Interrupts
* @{
- */
+ */
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
@@ -539,45 +452,28 @@
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
-
-/* Mailboxes definition */
+/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
+ * @{
+ */
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
/** @brief Reset CAN handle state
* @param __HANDLE__: specifies the CAN Handle.
@@ -637,7 +533,6 @@
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
@@ -684,7 +579,7 @@
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
@@ -701,8 +596,6 @@
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-
/**
* @brief Release the specified receive FIFO.
* @param __HANDLE__: CAN handle
@@ -710,7 +603,7 @@
* @retval None
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
@@ -726,24 +619,40 @@
/**
* @brief Enable or disable the DBG Freeze for CAN.
* @param __HANDLE__: CAN Handle
- * @param __NEWSTATE__: new state of the CAN peripheral.
+ * @param __NEWSTATE__: new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
* @retval None
*/
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/* Exported functions --------------------------------------------------------*/
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
-/* Initialization/de-initialization functions ***********************************/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ***********************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+/** @addtogroup CAN_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
@@ -751,17 +660,102 @@
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-
-/* Peripheral State functions ***************************************************/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/** @addtogroup CAN_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ***************************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,1112 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cec.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief CEC HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
+ * Consumer Electronics Control Peripheral (CEC).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The CEC HAL driver can be used as follow:
+
+ (#) Declare a CEC_HandleTypeDef handle structure.
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+ (##) Enable the CEC interface clock.
+ (##) CEC pins configuration:
+ (+) Enable the clock for the CEC GPIOs.
+ (+) Configure these CEC pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ and HAL_CEC_Receive_IT() APIs):
+ (+) Configure the CEC interrupt priority.
+ (+) Enable the NVIC CEC IRQ handle.
+ (@) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
+
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical
+ address and Listen mode in the hcec Init structure.
+
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CEC CEC
+ * @brief HAL CEC module driver
+ * @{
+ */
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
+ | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
+ | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the CEC
+ (+) The following parameters need to be configured:
+ (++) SignalFreeTime
+ (++) Tolerance
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
+ (++) SignalFreeTimeOption (SFT Timer start definition)
+ (++) OwnAddress (CEC device address)
+ (++) ListenMode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle .
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tmpreg = 0x0;
+
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+ assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
+ assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
+
+
+ if(hcec->State == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_CEC_MspInit(hcec);
+ }
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ tmpreg = hcec->Init.SignalFreeTime;
+ tmpreg |= hcec->Init.Tolerance;
+ tmpreg |= hcec->Init.BRERxStop;
+ tmpreg |= hcec->Init.BREErrorBitGen;
+ tmpreg |= hcec->Init.LBPEErrorBitGen;
+ tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
+ tmpreg |= hcec->Init.SignalFreeTimeOption;
+ tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
+ tmpreg |= hcec->Init.ListenMode;
+
+ /* Write to CEC Control Register */
+ MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->State = HAL_CEC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CEC peripheral
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CEC_MspDeInit(hcec);
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->State = HAL_CEC_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief CEC MSP Init
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC MSP DeInit
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspDeInit can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### I/O operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) No-Blocking mode: The communication is performed using Interrupts.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated CEC IRQ when using Interrupt mode.
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ error is detected
+
+ (#) Blocking mode API's are :
+ (+) HAL_CEC_Transmit()
+ (+) HAL_CEC_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_CEC_Transmit_IT()
+ (+) HAL_CEC_Receive_IT()
+ (+) HAL_CEC_IRQHandler()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (+) HAL_CEC_TxCpltCallback()
+ (+) HAL_CEC_RxCpltCallback()
+ (+) HAL_CEC_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send data in blocking mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+ uint8_t temp = 0;
+ uint32_t tempisr = 0;
+ uint32_t tickstart = 0;
+
+ if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if((pData == NULL ) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+
+ hcec->TxXferCount = Size;
+
+ /* case no data to be sent, sender is only pinging the system */
+ if (Size == 0)
+ {
+ /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ while (hcec->TxXferCount > 0)
+ {
+ hcec->TxXferCount--;
+
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart) > Timeout)
+ {
+ hcec->State = HAL_CEC_STATE_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check whether error occured while waiting for TXBR to be set:
+ * has Tx underrun occurred ?
+ * has Tx error occurred ?
+ * has Tx Missing Acknowledge error occurred ?
+ * has Arbitration Loss error occurred ? */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ }
+ /* TXBR to clear BEFORE writing TXDR register */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
+ if (hcec->TxXferCount == 0)
+ {
+ /* if last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ hcec->Instance->TXDR = *pData++;
+
+ /* error check after TX byte write up */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* end while (while (hcec->TxXferCount > 0)) */
+
+
+ /* if no error up to this point, check that transmission is
+ * complete, that is wait until TXEOM is reset */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart) > Timeout)
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Final error check once all bytes have been transmitted */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * @param Timeout: Timeout duration.
+ * Note that the received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0;
+
+ if (hcec->State == HAL_CEC_STATE_READY)
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if (pData == NULL )
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ hcec->RxXferSize = 0;
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+
+ /* Rx loop until CEC_ISR_RXEND is set */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
+ {
+ tickstart = HAL_GetTick();
+ /* Wait for next byte to be received */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart) > Timeout)
+ {
+ hcec->State = HAL_CEC_STATE_TIMEOUT;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ /* any error so far ?
+ * has Rx Missing Acknowledge occurred ?
+ * has Rx Long Bit Period error occurred ?
+ * has Rx Short Bit Period error occurred ?
+ * has Rx Bit Rising error occurred ?
+ * has Rx Overrun error occurred ? */
+ temp = (uint32_t) (hcec->Instance->ISR);
+ if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = temp;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
+
+
+ /* read received data */
+ *pData++ = hcec->Instance->RXDR;
+ temp = (uint32_t) (hcec->Instance->ISR);
+ /* end of message ? */
+ if ((temp & CEC_ISR_RXEND) != 0)
+ {
+ assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+
+ /* clear Rx-Byte Received flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
+ /* increment payload byte counter */
+ hcec->RxXferSize++;
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
+
+ /* if the instructions below are executed, it means RXEND was set when RXBR was
+ * set for the first time:
+ * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
+ * loop has not been executed and this means a single byte has been sent */
+ *pData++ = hcec->Instance->RXDR;
+ /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
+ hcec->RxXferSize = 0;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+{
+ uint8_t temp = 0;
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
+ && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ if((pData == NULL) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->pTxBuffPtr = pData;
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following two CEC Transmission interrupts as
+ * well as the following CEC Transmission Errors interrupts:
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ /* initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* in case of no payload (Size = 0), sender is only pinging the system;
+ * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ if (Size == 0)
+ {
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ return HAL_OK;
+ }
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+ __HAL_LOCK(hcec);
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * Note that the received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
+{
+ if(hcec->State == HAL_CEC_STATE_READY)
+ {
+ if(pData == NULL)
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->RxXferSize = 0;
+ hcec->pRxBuffPtr = pData;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ /* the IP is moving to a ready to receive state */
+ hcec->State = HAL_CEC_STATE_STANDBY_RX;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following CEC Reception Error Interrupts:
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the following two CEC Reception interrupts:
+ * Rx Byte Received IT
+ * End of Reception IT */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
+
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get size of the received frame.
+ * @param hcec: CEC handle
+ * @retval Frame size
+ */
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+{
+ return hcec->RxXferSize;
+}
+
+/**
+ * @brief This function handles CEC interrupt requests.
+ * @param hcec: CEC handle
+ * @retval None
+ */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+ /* save interrupts register for further error or interrupts handling purposes */
+ hcec->ErrorCode = hcec->Instance->ISR;
+ /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC transmit error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX underrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX arbitration error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX overrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX bit rising error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX short bit period error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX long bit period error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)
+ {
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
+ /* CEC RX byte received interrupt ---------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+ /* CEC RX end received interrupt ---------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+
+ /* CEC TX byte request interrupt ------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
+ {
+ /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+
+ /* CEC TX end interrupt ------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
+ {
+ /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC error callbacks
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
+ * @brief CEC control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CEC.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+@endverbatim
+ * @{
+ */
+/**
+ * @brief return the CEC state
+ * @param hcec: CEC handle
+ * @retval HAL state
+ */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+{
+ return hcec->State;
+}
+
+/**
+* @brief Return the CEC error code
+* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC.
+* @retval CEC Error Code
+*/
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+{
+ return hcec->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
+{
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+ __HAL_LOCK(hcec);
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Receive_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tempisr;
+
+ /* Three different conditions are tested to carry out the RX IT processing:
+ * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
+ * the reception of the first byte is starting
+ * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
+ * and a new byte is being received
+ * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
+ * but has been interrupted by a new message reception or discarded due to
+ * arbitration loss: the reception of the first or higher priority message
+ * (the arbitration winner) is starting */
+ if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_TX))
+ {
+ /* reception is starting */
+ hcec->State = HAL_CEC_STATE_BUSY_RX;
+ tempisr = (uint32_t) (hcec->Instance->ISR);
+ if ((tempisr & CEC_FLAG_RXBR) != 0)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ /* read received byte */
+ *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
+ /* if last byte has been received */
+ if ((tempisr & CEC_FLAG_RXEND) != 0)
+ {
+ /* clear IT */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND);
+ /* RX interrupts are not disabled at this point.
+ * Indeed, to disable the IT, the IP must be disabled first
+ * which resets the TXSOM flag. In case of arbitration loss,
+ * this leads to a transmission abort.
+ * Therefore, RX interruptions disabling if so required,
+ * is done in HAL_CEC_RxCpltCallback */
+
+ /* IP state is moved to READY.
+ * If the IP must remain in standby mode to listen
+ * any new message, it is up to HAL_CEC_RxCpltCallback
+ * to move it again to HAL_CEC_STATE_STANDBY_RX */
+ hcec->State = HAL_CEC_STATE_READY;
+
+ /* Call the Process Unlocked before calling the Rx call back API */
+ __HAL_UNLOCK(hcec);
+ HAL_CEC_RxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
+
+ hcec->RxXferSize++;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,681 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cec.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Header file of CEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CEC_H
+#define __STM32F4xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CEC_Exported_Types CEC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
+ It can be one of @ref CEC_Signal_Free_Time
+ and belongs to the set {0,...,7} where
+ 0x0 is the default configuration
+ else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
+
+ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
+ or CEC_EXTENDED_TOLERANCE */
+
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ CEC_RX_STOP_ON_BRE: reception is stopped. */
+
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Bit Rising Error detection.
+ CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
+
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Long Bit Period Error detection.
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ upon an error detected on a broadcast message.
+
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+
+ 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ b) LBPE detection: error-bit generation on the CEC line
+ if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
+
+ 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
+ no error-bit generation in case neither a) nor b) are satisfied. Additionally,
+ there is no error-bit generation in case of Short Bit Period Error detection in
+ a broadcast message while LSTN bit is set. */
+
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+
+ uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
+
+ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ own address (OAR). Messages addressed to different destination are ignored.
+ Broadcast messages are always received.
+
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ address (OAR) with positive acknowledge. Messages addressed to different destination
+ are received, but without interfering with the CEC bus: no acknowledge sent. */
+
+ uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
+
+}CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State structures definition
+ */
+typedef enum
+{
+ HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
+ HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
+ HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
+ HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
+}HAL_CEC_StateTypeDef;
+
+/**
+ * @brief CEC handle Structure definition
+ */
+typedef struct
+{
+ CEC_TypeDef *Instance; /* CEC registers base address */
+
+ CEC_InitTypeDef Init; /* CEC communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
+
+ uint16_t TxXferCount; /* CEC Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
+
+ uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
+ in case error is reported */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ HAL_CEC_StateTypeDef State; /* CEC communication state */
+
+}CEC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+ * @{
+ */
+
+/** @defgroup CEC_Error_Code CEC Error Code
+ * @{
+ */
+#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */
+#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
+#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
+#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
+#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
+#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
+#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
+#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
+#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
+#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
+ * @{
+ */
+#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
+#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
+#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
+#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
+#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
+#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
+#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
+#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Tolerance CEC Receiver Tolerance
+ * @{
+ */
+#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
+ * @{
+ */
+#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
+ * @{
+ */
+#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
+ * @{
+ */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
+ * @{
+ */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
+ * @{
+ */
+#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Listening_Mode CEC Listening mode option
+ * @{
+ */
+#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
+ * @{
+ */
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE
+#define CEC_IT_TXERR CEC_IER_TXERRIE
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE
+#define CEC_IT_TXEND CEC_IER_TXENDIE
+#define CEC_IT_TXBR CEC_IER_TXBRIE
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE
+#define CEC_IT_LBPE CEC_IER_LBPEIE
+#define CEC_IT_SBPE CEC_IER_SBPEIE
+#define CEC_IT_BRE CEC_IER_BREIE
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE
+#define CEC_IT_RXEND CEC_IER_RXENDIE
+#define CEC_IT_RXBR CEC_IER_RXBRIE
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Flags_Definitions CEC Flags definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND CEC_ISR_TXEND
+#define CEC_FLAG_TXBR CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE CEC_ISR_LBPE
+#define CEC_FLAG_SBPE CEC_ISR_SBPE
+#define CEC_FLAG_BRE CEC_ISR_BRE
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND CEC_ISR_RXEND
+#define CEC_FLAG_RXBR CEC_ISR_RXBR
+/**
+ * @}
+ */
+
+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
+ * @{
+ */
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CEC handle state
+ * @param __HANDLE__: CEC handle.
+ * @retval None
+ */
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+
+/** @brief Checks whether or not the specified CEC interrupt flag is set.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the interrupt to check.
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval ITStatus
+ */
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/** @brief Clears the interrupt or status flag when raised (write at 1)
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the interrupt/status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
+
+/** @brief Enables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Checks whether or not the specified CEC interrupt is enabled.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+/** @brief Enables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
+
+/** @brief Disables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
+
+/** @brief Set Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
+
+/** @brief Set Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
+ */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
+
+/** @brief Get Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
+
+/** @brief Get Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
+
+/** @brief Clear OAR register
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
+
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
+ * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
+ * @retval none
+ */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+ * @{
+ */
+
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+
+#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
+ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
+
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
+
+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
+
+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
+
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+
+#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
+ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
+
+#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
+ ((__MODE__) == CEC_FULL_LISTENING_MODE))
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__: CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__: CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__: CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_conf.h Thu Apr 30 13:00:08 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,407 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hal_conf_template.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
- * @brief HAL configuration template file.
- * This file should be copied to the application folder and renamed
- * to stm32f4xx_hal_conf.h.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DCMI_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_DMA2D_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_NAND_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_PCCARD_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_SDRAM_MODULE_ENABLED
-#define HAL_HASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_LTDC_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SAI_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_HCD_MODULE_ENABLED
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief Internal Low Speed oscillator (LSI) value.
- */
-#if !defined (LSI_VALUE)
- #define LSI_VALUE ((uint32_t)40000)
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
-/**
- * @brief External Low Speed oscillator (LSE) value.
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
- * @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
- * frequency, this source is inserted directly through I2S_CKIN pad.
- */
-#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
-#define USE_RTOS 0
-#define PREFETCH_ENABLE 1
-#define INSTRUCTION_CACHE_ENABLE 1
-#define DATA_CACHE_ENABLE 1
-
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/* #define USE_FULL_ASSERT 1 */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2
-#define MAC_ADDR1 0
-#define MAC_ADDR2 0
-#define MAC_ADDR3 0
-#define MAC_ADDR4 0
-#define MAC_ADDR5 0
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS 0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
-
-#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
-#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
-#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
-#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
-#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
-#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
-
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
-#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
-#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
-#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
-#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
-#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
-#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
-
-#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
-#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
-
-#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
-#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
- #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
- #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
- #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -28,11 +28,11 @@
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programing manual for details in how to configure priority.
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest pre-emption priority
+ (+@) Lowest preemption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -104,26 +104,26 @@
* @{
*/
-/** @defgroup CORTEX
+/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Functions
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
-/** @defgroup CORTEX_Group1 Initialization and de-initialization functions
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -140,21 +140,21 @@
/**
- * @brief Sets the priority grouping field (pre-emption priority and subpriority)
+ * @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
@@ -171,8 +171,8 @@
* @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @param PreemptPriority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
@@ -199,11 +199,14 @@
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
@@ -212,18 +215,20 @@
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
- * @param None
* @retval None
*/
void HAL_NVIC_SystemReset(void)
@@ -247,7 +252,7 @@
* @}
*/
-/** @defgroup CORTEX_Group2 Peripheral Control functions
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
*
@verbatim
@@ -265,7 +270,6 @@
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
- * @param None
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
@@ -278,18 +282,18 @@
* @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
@@ -306,12 +310,15 @@
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
@@ -321,12 +328,15 @@
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
@@ -335,11 +345,14 @@
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
@@ -348,12 +361,15 @@
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
@@ -382,7 +398,6 @@
/**
* @brief This function handles SYSTICK interrupt request.
- * @param None
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
@@ -392,7 +407,6 @@
/**
* @brief SYSTICK callback.
- * @param None
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,15 +56,13 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Constants
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
-
-/** @defgroup CORTEX_Preemption_Priority_Group
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
-
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
@@ -75,33 +73,29 @@
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
+/**
+ * @}
+ */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
/**
* @}
*/
-/** @defgroup CORTEX_SysTick_clock_source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
/**
* @}
*/
+
/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+ * @{
+ */
/** @brief Configures the SysTick clock source.
* @param __CLKSRC__: specifies the SysTick clock source.
@@ -119,22 +113,33 @@
else \
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
} while(0)
-
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
-/* Peripheral Control functions *************************************************/
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@@ -144,6 +149,38 @@
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_crc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -18,7 +18,7 @@
[..]
The CRC HAL driver can be used as follows:
- (#) Enable CRC AHB clock using __CRC_CLK_ENABLE();
+ (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(#) Use HAL_CRC_Accumulate() function to compute the CRC value of
a 32-bit data buffer using combination of the previous CRC value
@@ -32,7 +32,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -66,8 +66,7 @@
* @{
*/
-/** @defgroup CRC
- * @brief CRC HAL module driver.
+/** @addtogroup CRC
* @{
*/
@@ -79,15 +78,16 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Private_Functions
+/** @addtogroup CRC_Exported_Functions
* @{
*/
-/** @defgroup CRC_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @addtogroup CRC_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@@ -122,6 +122,8 @@
if(hcrc->State == HAL_CRC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
@@ -197,12 +199,12 @@
/**
* @}
- */
+ */
-/** @defgroup CRC_Group2 Peripheral Control functions
- * @brief management functions.
+/** @addtogroup CRC_Exported_Functions_Group2
+ * @brief Peripheral Control functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
@@ -291,10 +293,11 @@
/**
* @}
- */
+ */
-/** @defgroup CRC_Group3 Peripheral State functions
- * @brief Peripheral State functions.
+
+/** @addtogroup CRC_Exported_Functions_Group3
+ * @brief Peripheral State functions
*
@verbatim
==============================================================================
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_crc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,15 +50,19 @@
* @{
*/
-/** @addtogroup CRC
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
-/**
- * @brief CRC HAL State Structure definition
- */
+/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
+ * @{
+ */
typedef enum
{
HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
@@ -68,9 +72,12 @@
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
}HAL_CRC_StateTypeDef;
+/**
+ * @}
+ */
-/**
- * @brief CRC handle Structure definition
+/** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition
+ * @{
*/
typedef struct
{
@@ -81,11 +88,21 @@
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
}CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
-/** @brief Reset CRC handle state
+/** @brief Resets CRC handle state
* @param __HANDLE__: CRC handle
* @retval None
*/
@@ -101,7 +118,7 @@
/**
* @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param __HANDLE__: CRC handle
- * @param __VALUE: 8-bit value to be stored in the ID register
+ * @param __VALUE__: 8-bit value to be stored in the ID register
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))
@@ -112,21 +129,108 @@
* @retval 8-bit value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
-/* Initialization/de-initialization functions **********************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
-/* Peripheral Control functions ************************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
-/* Peripheral State functions **************************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRC_Private_Types CRC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRC_Private_Defines CRC Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Variables CRC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Constants CRC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -134,8 +238,8 @@
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@@ -23,7 +23,7 @@
The CRYP HAL driver can be used as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
(##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
@@ -33,7 +33,7 @@
(+++) Configure and enable two DMA streams one for managing data transfer from
memory to peripheral (input stream) and another stream for managing data
transfer from peripheral to memory (output stream)
- (+++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -104,7 +104,7 @@
* @{
*/
-/** @defgroup CRYP
+/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
*/
@@ -115,10 +115,20 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_define
+ * @{
+ */
#define CRYP_TIMEOUT_VALUE 1
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions_prototypes
+ * @{
+ */
static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
@@ -131,14 +141,448 @@
static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-
+/**
+ * @}
+ */
+
+
/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Functions
+/** @addtogroup CRYP_Private_Functions
* @{
*/
-/** @defgroup CRYP_Group1 Initialization and de-initialization functions
+
+/**
+ * @brief DMA CRYP Input Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP Output Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ hcryp->State= HAL_CRYP_STATE_READY;
+ HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+ * @brief Writes the Key in Key registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Key: Pointer to Key buffer
+ * @param KeySize: Size of Key
+ * @retval None
+ */
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Key;
+
+ switch(KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ /* Key Initialisation */
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Writes the InitVector/InitCounter in IV registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param InitVector: Pointer to InitVector/InitCounter buffer
+ * @param IVSize: Size of the InitVector/InitCounter
+ * @retval None
+ */
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
+{
+ uint32_t ivaddr = (uint32_t)InitVector;
+
+ switch(IVSize)
+ {
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Process Data: Writes Input data in polling mode and read the output data
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input: Pointer to the Input buffer
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16.
+ * @param Output: Pointer to the returned buffer
+ * @param Timeout: Timeout value
+ * * @retval None
+ */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ uint32_t i = 0;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+ for(i=0; (i < Ilength); i+=16)
+ {
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Process Data: Write Input data in polling mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input: Pointer to the Input buffer
+ * @param Ilength: Length of the Input buffer, must be a multiple of 8
+ * @param Output: Pointer to the returned buffer
+ * @param Timeout: Specify Timeout value
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ uint32_t i = 0;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+ for(i=0; (i < Ilength); i+=8)
+ {
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the DMA configuration and start the DMA transfer
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr: address of the Input buffer
+ * @param Size: Size of the Input buffer, must be a multiple of 16.
+ * @param outputaddr: address of the Output buffer
+ * @retval None
+ */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
+
+ /* Enable In DMA request */
+ hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
+
+ /* Enable the DMA Out DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
+
+ /* Enable Out DMA request */
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+
+}
+
+/**
+ * @brief Sets the CRYP peripheral in DES ECB mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
+
+ /* Set the key */
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @brief Sets the CRYP peripheral in DES CBC mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
+
+ /* Set the key */
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @brief Sets the CRYP peripheral in TDES ECB mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @brief Sets the CRYP peripheral in TDES CBC mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES CBC mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @}
+ */
+
+ /* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRYP_Exported_Functions
+ * @{
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@@ -177,6 +621,8 @@
if(hcryp->State == HAL_CRYP_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRYP_MspInit(hcryp);
}
@@ -226,7 +672,7 @@
hcryp->CrypOutCount = 0;
/* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_CRYP_MspDeInit(hcryp);
@@ -271,7 +717,7 @@
* @}
*/
-/** @defgroup CRYP_Group2 AES processing functions
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
* @brief processing functions.
*
@verbatim
@@ -316,20 +762,20 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -370,16 +816,16 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -427,16 +873,16 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -488,15 +934,15 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -515,18 +961,18 @@
}
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Reset the ALGOMODE bits*/
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -576,15 +1022,15 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -606,16 +1052,16 @@
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -663,16 +1109,16 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -728,60 +1174,60 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Locked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -829,62 +1275,62 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Locked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -932,62 +1378,62 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1038,14 +1484,14 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1064,60 +1510,60 @@
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1168,15 +1614,15 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1195,66 +1641,66 @@
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1303,63 +1749,63 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1405,10 +1851,10 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1460,13 +1906,13 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1518,13 +1964,13 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1578,15 +2024,15 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1605,10 +2051,10 @@
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1662,15 +2108,15 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1689,13 +2135,13 @@
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1748,13 +2194,13 @@
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1779,7 +2225,8 @@
/**
* @}
*/
-/** @defgroup CRYP_Group3 DES processing functions
+
+/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions
* @brief processing functions.
*
@verbatim
@@ -1820,7 +2267,7 @@
CRYP_SetDESECBMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1860,7 +2307,7 @@
CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1900,7 +2347,7 @@
CRYP_SetDESCBCMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1940,7 +2387,7 @@
CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1989,47 +2436,47 @@
CRYP_SetDESECBMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2074,48 +2521,48 @@
CRYP_SetDESCBCMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2160,47 +2607,47 @@
CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2245,47 +2692,47 @@
CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2394,7 +2841,7 @@
* @param pCypherData: Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr;
uint32_t outputaddr;
@@ -2475,7 +2922,7 @@
* @}
*/
-/** @defgroup CRYP_Group4 TDES processing functions
+/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions
* @brief processing functions.
*
@verbatim
@@ -2517,7 +2964,7 @@
CRYP_SetTDESECBMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2558,7 +3005,7 @@
CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Cypher Data and Get Plain Data */
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -2599,7 +3046,7 @@
CRYP_SetTDESCBCMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2640,7 +3087,7 @@
CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Cypher Data and Get Plain Data */
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -2689,47 +3136,47 @@
CRYP_SetTDESECBMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2774,46 +3221,46 @@
CRYP_SetTDESCBCMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2858,46 +3305,46 @@
CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2942,46 +3389,46 @@
CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -3171,7 +3618,7 @@
* @}
*/
-/** @defgroup CRYP_Group5 DMA callback functions
+/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions
* @brief DMA callback functions.
*
@verbatim
@@ -3230,7 +3677,7 @@
* @}
*/
-/** @defgroup CRYP_Group6 CRYP IRQ handler management
+/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management
* @brief CRYP IRQ handler.
*
@verbatim
@@ -3302,11 +3749,11 @@
break;
case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
- HAL_CRYP_AESCTR_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
+ HAL_CRYP_AESCTR_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
- HAL_CRYP_AESCTR_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
+ HAL_CRYP_AESCTR_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
default:
@@ -3318,7 +3765,7 @@
* @}
*/
-/** @defgroup CRYP_Group7 Peripheral State functions
+/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
@@ -3347,424 +3794,6 @@
* @}
*/
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
- in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
- in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE();
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- hcryp->State= HAL_CRYP_STATE_READY;
- HAL_CRYP_ErrorCallback(hcryp);
-}
-
-/**
- * @brief Writes the Key in Key registers.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Key: Pointer to Key buffer
- * @param KeySize: Size of Key
- * @retval None
- */
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Key;
-
- switch(KeySize)
- {
- case CRYP_KEYSIZE_256B:
- /* Key Initialisation */
- CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_192B:
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_128B:
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param InitVector: Pointer to InitVector/InitCounter buffer
- * @param IVSize: Size of the InitVector/InitCounter
- * @retval None
- */
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
-{
- uint32_t ivaddr = (uint32_t)InitVector;
-
- switch(IVSize)
- {
- case CRYP_KEYSIZE_128B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
- break;
- /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
- case CRYP_KEYSIZE_192B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- case CRYP_KEYSIZE_256B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Process Data: Writes Input data in polling mode and read the output data
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the Input buffer
- * @param Ilength: Length of the Input buffer, must be a multiple of 16.
- * @param Output: Pointer to the returned buffer
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- for(i=0; (i < Ilength); i+=16)
- {
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Process Data: Write Input data in polling mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the Input buffer
- * @param Ilength: Length of the Input buffer, must be a multiple of 8
- * @param Output: Pointer to the returned buffer
- * @param Timeout: Specify Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- for(i=0; (i < Ilength); i+=8)
- {
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the DMA configuration and start the DMA transfer
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param inputaddr: address of the Input buffer
- * @param Size: Size of the Input buffer, must be a multiple of 16.
- * @param outputaddr: address of the Output buffer
- * @retval None
- */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
-
- /* Enable In DMA request */
- CRYP->DMACR = (CRYP_DMACR_DIEN);
-
- /* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
-
- /* Enable Out DMA request */
- CRYP->DMACR |= CRYP_DMACR_DOEN;
-
-}
-
-/**
- * @brief Sets the CRYP peripheral in DES ECB mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_ECB | Direction);
-
- /* Set the key */
- CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
-
-/**
- * @brief Sets the CRYP peripheral in DES CBC mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_CBC | Direction);
-
- /* Set the key */
- CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
-
-/**
- * @brief Sets the CRYP peripheral in TDES ECB mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_ECB | Direction);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
-
-/**
- * @brief Sets the CRYP peripheral in TDES CBC mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_CBC | Direction);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,16 +57,21 @@
/* Exported types ------------------------------------------------------------*/
-/**
- * @brief CRYP Configuration Structure definition
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+ * @{
*/
+
+/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
+ * @{
+ */
+
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
+ This parameter can be a value of @ref CRYP CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
- This parameter can be a value of @ref CRYP_Key_Size */
+ This parameter can be a value of @ref CRYP CRYP_Key_Size */
uint8_t* pKey; /*!< The key used for encryption/decryption */
@@ -83,15 +88,21 @@
uint8_t* Header; /*!< The header used in GCM and CCM modes */
- uint16_t HeaderSize; /*!< The size of header buffer in bytes */
+ uint32_t HeaderSize; /*!< The size of header buffer in bytes */
uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
}CRYP_InitTypeDef;
/**
- * @brief HAL CRYP State structures definition
+ * @}
*/
+
+/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
+ * @{
+ */
+
+
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
@@ -102,8 +113,14 @@
}HAL_CRYP_STATETypeDef;
/**
- * @brief HAL CRYP phase structures definition
+ * @}
*/
+
+/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
+ * @{
+ */
+
+
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
@@ -113,10 +130,17 @@
}HAL_PhaseTypeDef;
/**
- * @brief CRYP handle Structure definition
- */
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
+ * @{
+ */
+
typedef struct
{
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+
CRYP_InitTypeDef Init; /*!< CRYP required parameters */
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
@@ -125,7 +149,7 @@
__IO uint16_t CrypInCount; /*!< Counter of inputed data */
- __IO uint16_t CrypOutCount; /*!< Counter of outputed data */
+ __IO uint16_t CrypOutCount; /*!< Counter of outputted data */
HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
@@ -140,45 +164,43 @@
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
}CRYP_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup CRYP_Exported_Constants
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
* @{
*/
-/** @defgroup CRYP_Key_Size
+/** @defgroup CRYP_Exported_Constants_Group1 CRYP CRYP_Key_Size
* @{
*/
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
-
-#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_256B))
-/**
+/**
* @}
*/
-/** @defgroup CRYP_Data_Type
+/** @defgroup CRYP_Exported_Constants_Group2 CRYP CRYP_Data_Type
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
-
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
- ((DATATYPE) == CRYP_DATATYPE_16B) || \
- ((DATATYPE) == CRYP_DATATYPE_8B) || \
- ((DATATYPE) == CRYP_DATATYPE_1B))
-/**
+/**
* @}
*/
-/** @defgroup CRYP_AlgoModeDirection
+/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
* @{
- */
+ */
#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003C)
#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004)
@@ -198,7 +220,7 @@
* @}
*/
-/** @defgroup CRYP_Interrupt
+/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
* @{
*/
#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
@@ -207,10 +229,9 @@
* @}
*/
-/** @defgroup CRYP_Flags
+/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
* @{
*/
-
#define CRYP_FLAG_BUSY ((uint32_t)0x00000010) /*!< The CRYP core is currently
processing a block of data
or a key preparation (for
@@ -232,7 +253,10 @@
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+ * @{
+ */
+
/** @brief Reset CRYP handle state
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
@@ -241,27 +265,29 @@
/**
* @brief Enable/Disable the CRYP peripheral.
- * @param None
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_ENABLE() (CRYP->CR |= CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE() (CRYP->CR &= ~CRYP_CR_CRYPEN)
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
/**
* @brief Flush the data FIFO.
- * @param None
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)
+#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
/**
* @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param MODE: The algorithm mode.
* @retval None
*/
-#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)
+#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
/** @brief Check whether the specified CRYP flag is set or not.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
@@ -274,41 +300,62 @@
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)
-#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
/** @brief Check whether the specified CRYP interrupt is set or not.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Enable the CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP Interrupt.
* @retval None
*/
-#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP interrupt.
* @retval None
*/
-#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
+/**
+ * @}
+ */
+
/* Include CRYP HAL Extension module */
#include "stm32f4xx_hal_cryp_ex.h"
/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions ********************************/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+/** @addtogroup CRYP_Exported_Functions_Group2
+ * @{
+ */
/* AES encryption/decryption using polling ***********************************/
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
@@ -332,7 +379,13 @@
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
+/** @addtogroup CRYP_Exported_Functions_Group3
+ * @{
+ */
/* DES encryption/decryption using polling ***********************************/
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
@@ -347,10 +400,16 @@
/* DES encryption/decryption using DMA ***************************************/
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
+/** @addtogroup CRYP_Exported_Functions_Group4
+ * @{
+ */
/* TDES encryption/decryption using polling **********************************/
HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
@@ -368,22 +427,96 @@
HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* Processing functions ******************************************************/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
-/* Peripheral State functions ************************************************/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-
-/* MSP functions *************************************************************/
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-
-/* CallBack functions ********************************************************/
+/** @addtogroup CRYP_Exported_Functions_Group5
+ * @{
+ */
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+/** @addtogroup CRYP_Exported_Functions_Group6
+ * @{
+ */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group7
+ * @{
+ */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Types CRYP Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
+ * @{
+ */
+#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+ * @{
+ */
+
+#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
+ ((__KEYSIZE__) == CRYP_KEYSIZE_192B) || \
+ ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+
+ /**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@@ -16,7 +16,7 @@
[..]
The CRYP Extension HAL driver can be used as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
(##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
@@ -26,7 +26,7 @@
(+++) Configure and enable two DMA streams one for managing data transfer from
memory to peripheral (input stream) and another stream for managing data
transfer from peripheral to memory (output stream)
- (+++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
@@ -60,13 +60,16 @@
Call those functions after the processing ones (polling, interrupt or DMA).
e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
+ @note: For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
+ @note: The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
+ (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -100,7 +103,7 @@
* @{
*/
-/** @defgroup CRYPEx
+/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
*/
@@ -111,11 +114,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_define
+ * @{
+ */
#define CRYPEx_TIMEOUT_VALUE 1
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
+/** @defgroup CRYPEx_Private_Functions_prototypes CRYP Private Functions Prototypes
+ * @{
+ */
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
@@ -123,14 +136,339 @@
static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-
+/**
+ * @}
+ */
+
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Private_Functions
+/** @addtogroup CRYPEx_Private_Functions
* @{
*/
-/** @defgroup CRYPEx_Group1 Extended AES processing functions
+/**
+ * @brief DMA CRYP Input Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP Output Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hcryp->State= HAL_CRYP_STATE_READY;
+ HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+ * @brief Writes the Key in Key registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Key: Pointer to Key buffer
+ * @param KeySize: Size of Key
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Key;
+
+ switch(KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ /* Key Initialisation */
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Writes the InitVector/InitCounter in IV registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param InitVector: Pointer to InitVector/InitCounter buffer
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
+{
+ uint32_t ivaddr = (uint32_t)InitVector;
+
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
+}
+
+/**
+ * @brief Process Data: Writes Input data in polling mode and read the Output data.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input: Pointer to the Input buffer.
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16
+ * @param Output: Pointer to the returned buffer
+ * @param Timeout: Timeout value
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+ uint32_t i = 0;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+ for(i=0; (i < Ilength); i+=16)
+ {
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the Output block from the OUT FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the header phase
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input: Pointer to the Input buffer.
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16
+ * @param Timeout: Timeout value
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+ uint32_t loopcounter = 0;
+ uint32_t headeraddr = (uint32_t)Input;
+
+ /***************************** Header phase *********************************/
+ if(hcryp->Init.HeaderSize != 0)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4;
+ }
+
+ /* Wait until the complete message has been processed */
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the DMA configuration and start the DMA transfer.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr: Address of the Input buffer
+ * @param Size: Size of the Input buffer, must be a multiple of 16
+ * @param outputaddr: Address of the Output buffer
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
+
+ /* Enable In DMA request */
+ hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
+
+ /* Enable the DMA Out DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
+
+ /* Enable Out DMA request */
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+}
+
+/**
+ * @}
+ */
+
+/* Exported functions---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Exported_Functions
+ * @{
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
* @brief Extended processing functions.
*
@verbatim
@@ -264,26 +602,26 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -309,17 +647,17 @@
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
{
/* Check for the Timeout */
@@ -339,20 +677,20 @@
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -379,13 +717,13 @@
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -435,16 +773,16 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -474,16 +812,16 @@
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -533,16 +871,16 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -571,13 +909,13 @@
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -608,11 +946,11 @@
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)
{
uint32_t tickstart = 0;
- uint32_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
- uint32_t inputlength = Size * 8; /* input length in bits */
+ uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
+ uint64_t inputlength = Size * 8; /* input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
/* Process Locked */
@@ -628,48 +966,48 @@
hcryp->Phase = HAL_CRYP_PHASE_FINAL;
/* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select final phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- CRYP->DR = 0;
- CRYP->DR = __RBIT(headerlength);
- CRYP->DR = 0;
- CRYP->DR = __RBIT(inputlength);
+ hcryp->Instance->DR = __RBIT(headerlength >> 32);
+ hcryp->Instance->DR = __RBIT(headerlength);
+ hcryp->Instance->DR = __RBIT(inputlength >> 32);
+ hcryp->Instance->DR = __RBIT(inputlength);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- CRYP->DR = 0;
- CRYP->DR = __REV(headerlength);
- CRYP->DR = 0;
- CRYP->DR = __REV(inputlength);
+ hcryp->Instance->DR = __REV(headerlength >> 32);
+ hcryp->Instance->DR = __REV(headerlength);
+ hcryp->Instance->DR = __REV(inputlength >> 32);
+ hcryp->Instance->DR = __REV(inputlength);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- CRYP->DR = 0;
- CRYP->DR = __REV16(headerlength);
- CRYP->DR = 0;
- CRYP->DR = __REV16(inputlength);
+ hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);
+ hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);
+ hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);
+ hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
- CRYP->DR = 0;
- CRYP->DR = (uint32_t)(headerlength);
- CRYP->DR = 0;
- CRYP->DR = (uint32_t)(inputlength);
+ hcryp->Instance->DR = (uint32_t)(headerlength >> 32);
+ hcryp->Instance->DR = (uint32_t)(headerlength);
+ hcryp->Instance->DR = (uint32_t)(inputlength >> 32);
+ hcryp->Instance->DR = (uint32_t)(inputlength);
}
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -688,13 +1026,13 @@
}
/* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
}
/* Change the CRYP peripheral state */
@@ -737,27 +1075,27 @@
hcryp->Phase = HAL_CRYP_PHASE_FINAL;
/* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select final phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write the counter block in the IN FIFO */
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
ctraddr+=4;
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
ctraddr+=4;
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
ctraddr+=4;
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -776,10 +1114,10 @@
}
/* Read the Auth TAG in the IN FIFO */
- temptag[0] = CRYP->DOUT;
- temptag[1] = CRYP->DOUT;
- temptag[2] = CRYP->DOUT;
- temptag[3] = CRYP->DOUT;
+ temptag[0] = hcryp->Instance->DOUT;
+ temptag[1] = hcryp->Instance->DOUT;
+ temptag[2] = hcryp->Instance->DOUT;
+ temptag[3] = hcryp->Instance->DOUT;
}
/* Copy temporary authentication TAG in user TAG buffer */
@@ -912,26 +1250,26 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -957,17 +1295,17 @@
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -985,20 +1323,20 @@
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1024,13 +1362,13 @@
/* Reset bit 0 */
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1088,16 +1426,16 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1125,13 +1463,13 @@
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1140,9 +1478,9 @@
if(Size != 0)
{
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
}
else
{
@@ -1154,42 +1492,42 @@
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -1324,26 +1662,26 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1366,17 +1704,17 @@
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1391,20 +1729,20 @@
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1428,10 +1766,10 @@
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1440,9 +1778,9 @@
if(Size != 0)
{
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
}
else
{
@@ -1453,42 +1791,42 @@
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call Input transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -1538,16 +1876,16 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1573,10 +1911,10 @@
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1585,9 +1923,9 @@
if(Size != 0)
{
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
}
else
{
@@ -1600,42 +1938,42 @@
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -1770,26 +2108,26 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1812,17 +2150,17 @@
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1837,20 +2175,20 @@
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1873,60 +2211,60 @@
/* Reset bit 0 */
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -1973,16 +2311,16 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2002,7 +2340,7 @@
}
}
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the header phase */
if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
@@ -2010,13 +2348,13 @@
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2163,26 +2501,26 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2205,17 +2543,17 @@
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2230,20 +2568,20 @@
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2267,10 +2605,10 @@
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2324,13 +2662,13 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2356,10 +2694,10 @@
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2507,26 +2845,26 @@
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
/* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2551,17 +2889,17 @@
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2576,20 +2914,20 @@
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2612,10 +2950,10 @@
/* Reset bit 0 */
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2636,11 +2974,29 @@
}
/**
- * @brief This function handles CRYP interrupt request.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * @}
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management
+ * @brief CRYPEx IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### CRYPEx IRQ handler management #####
+ ==============================================================================
+[..] This section provides CRYPEx IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles CRYPEx interrupt request.
+ * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
+
void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
@@ -2671,339 +3027,6 @@
*/
/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
- in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
- in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hcryp->State= HAL_CRYP_STATE_READY;
- HAL_CRYP_ErrorCallback(hcryp);
-}
-
-/**
- * @brief Writes the Key in Key registers.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Key: Pointer to Key buffer
- * @param KeySize: Size of Key
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Key;
-
- switch(KeySize)
- {
- case CRYP_KEYSIZE_256B:
- /* Key Initialisation */
- CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_192B:
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_128B:
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param InitVector: Pointer to InitVector/InitCounter buffer
- * @param IVSize: Size of the InitVector/InitCounter
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
-{
- uint32_t ivaddr = (uint32_t)InitVector;
-
- switch(IVSize)
- {
- case CRYP_KEYSIZE_128B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
- break;
- /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
- case CRYP_KEYSIZE_192B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- case CRYP_KEYSIZE_256B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Process Data: Writes Input data in polling mode and read the Output data.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the Input buffer.
- * @param Ilength: Length of the Input buffer, must be a multiple of 16
- * @param Output: Pointer to the returned buffer
- * @param Timeout: Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- for(i=0; (i < Ilength); i+=16)
- {
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the OUT FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the header phase
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the Input buffer.
- * @param Ilength: Length of the Input buffer, must be a multiple of 16
- * @param Timeout: Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t loopcounter = 0;
- uint32_t headeraddr = (uint32_t)Input;
-
- /***************************** Header phase *********************************/
- if(hcryp->Init.HeaderSize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-
- for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- }
-
- /* Wait until the complete message has been processed */
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the DMA configuration and start the DMA transfert.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param inputaddr: Address of the Input buffer
- * @param Size: Size of the Input buffer, must be a multiple of 16
- * @param outputaddr: Address of the Output buffer
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
-
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
-
- /* Enable In DMA request */
- CRYP->DMACR = CRYP_DMACR_DIEN;
-
- /* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
-
- /* Enable Out DMA request */
- CRYP->DMACR |= CRYP_DMACR_DOEN;
-}
-
-/**
* @}
*/
#endif /* STM32F437xx || STM32F439xx */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -58,23 +58,24 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Constants
+/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported Constants
* @{
*/
-/** @defgroup CRYPEx_AlgoModeDirection
+/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
* @{
*/
#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000)
#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004)
#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008)
#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000C)
+
/**
* @}
*/
-/** @defgroup CRYPEx_PhaseConfig
- * The phases are relevant only to AES-GCM and AES-CCM
+/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig
+ * @brief The phases are relevant only to AES-GCM and AES-CCM
* @{
*/
#define CRYP_PHASE_INIT ((uint32_t)0x00000000)
@@ -90,24 +91,38 @@
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros
+ * @{
+ */
+
/**
* @brief Set the phase: Init, header, payload, final.
* This is relevant only for GCM and CCM modes.
- * @param PHASE: The phase.
+ * @param __HANDLE__: specifies the CRYP handle.
+ * @param __PHASE__: The phase.
* @retval None
*/
-#define __HAL_CRYP_SET_PHASE(PHASE) do{CRYP->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
- CRYP->CR |= (uint32_t)(PHASE);\
- }while(0)
+#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+ (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+ }while(0)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+ * @{
+ */
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+ * @{
+ */
+
/* AES encryption/decryption using polling ***********************************/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
@@ -124,10 +139,70 @@
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* Processing functions ********************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+ * @{
+ */
+
void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
+ * @{
+ */
+
+ /**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F437xx || STM32F439xx */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -29,17 +29,17 @@
*** DAC Triggers ***
====================
[..]
- Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
[..]
Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
The used pin (GPIOx_Pin9) must be configured in input mode.
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
- (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
- (#) Software using DAC_Trigger_Software
+ (#) Software using DAC_TRIGGER_SOFTWARE
*** DAC Buffer mode feature ***
===============================
@@ -48,7 +48,7 @@
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
- sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
[..]
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
@@ -109,7 +109,7 @@
=================================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start()
- (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
*** DMA mode IO operation ***
@@ -141,7 +141,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -176,30 +176,37 @@
* @{
*/
-/** @defgroup DAC
+/** @defgroup DAC DAC
* @brief DAC driver modules
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DAC_Group1 Initialization and de-initialization functions
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -233,6 +240,8 @@
if(hdac->State == HAL_DAC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
}
@@ -316,7 +325,7 @@
* @}
*/
-/** @defgroup DAC_Group2 IO operation functions
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -346,8 +355,6 @@
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
- uint32_t tmp1 = 0, tmp2 = 0;
-
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -357,32 +364,9 @@
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
- /* Enable the Peripharal */
+ /* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
- if(Channel == DAC_CHANNEL_1)
- {
- tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
- tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
- /* Check if software trigger enabled */
- if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
- {
- /* Enable the selected DAC software conversion */
- hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
- }
- }
- else
- {
- tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
- tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
- /* Check if software trigger enabled */
- if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
- {
- /* Enable the selected DAC software conversion*/
- hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
- }
- }
-
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -410,7 +394,7 @@
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
-
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -534,7 +518,7 @@
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
- /* Enable the Peripharal */
+ /* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Process Unlocked */
@@ -564,7 +548,7 @@
/* Disable the selected DAC channel DMA request */
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
- /* Disable the Peripharal */
+ /* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Disable the DMA Channel */
@@ -579,9 +563,9 @@
}
/* Check if DMA Channel effectively disabled */
- if(status == HAL_ERROR)
+ if(status != HAL_OK)
{
- /* Update ADC state machine to error */
+ /* Update DAC state machine to error */
hdac->State = HAL_DAC_STATE_ERROR;
}
else
@@ -628,13 +612,13 @@
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
- /* Check Overrun flag */
+ /* Check underrun channel 1 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to chanel1 DMA underrun error */
+ /* Set DAC error code to channel1 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
/* Clear the underrun flag */
@@ -646,7 +630,8 @@
/* Error callback */
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
}
- else
+ /* Check underrun channel 2 flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -700,7 +685,7 @@
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ErrorCallback could be implemented in the user file
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
}
@@ -721,7 +706,7 @@
* @}
*/
-/** @defgroup DAC_Group3 Peripheral Control functions
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -763,7 +748,7 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
- tmpreg1 = DAC->CR;
+ tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
/* Configure for the selected DAC channel: buffer output, trigger */
@@ -773,9 +758,9 @@
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
- DAC->CR = tmpreg1;
+ hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
- DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -815,11 +800,11 @@
tmp = (uint32_t)hdac->Instance;
if(Channel == DAC_CHANNEL_1)
{
- tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
else
{
- tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
/* Set the DAC channel1 selected data holding register */
@@ -833,7 +818,7 @@
* @}
*/
-/** @defgroup DAC_Group4 Peripheral State and Errors functions
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -926,7 +911,10 @@
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx
+ */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,9 @@
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -57,9 +59,12 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
/**
- * @brief HAL State structures definition
+ * @brief HAL State structures definition
*/
typedef enum
{
@@ -71,7 +76,7 @@
}HAL_DAC_StateTypeDef;
/**
- * @brief DAC handle Structure definition
+ * @brief DAC handle Structure definition
*/
typedef struct
{
@@ -90,7 +95,7 @@
}DAC_HandleTypeDef;
/**
- * @brief DAC Configuration regular Channel structure definition
+ * @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
@@ -100,10 +105,16 @@
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_ChannelConfTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
-/** @defgroup DAC_Error_Code
+/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
@@ -114,7 +125,7 @@
* @}
*/
-/** @defgroup DAC_trigger_selection
+/** @defgroup DAC_trigger_selection DAC Trigger Selection
* @{
*/
@@ -129,91 +140,64 @@
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
/**
* @}
*/
-/** @defgroup DAC_output_buffer
+/** @defgroup DAC_output_buffer DAC Output Buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
-
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
/**
* @}
*/
-/** @defgroup DAC_Channel_selection
+/** @defgroup DAC_Channel_selection DAC Channel Selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
/**
* @}
*/
-/** @defgroup DAC_data_alignement
+/** @defgroup DAC_data_alignment DAC Data Alignment
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
-/** @defgroup DAC_flags_definition
+/** @defgroup DAC_flags_definition DAC Flags Definition
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
- ((FLAG) == DAC_FLAG_DMAUDR2))
/**
* @}
*/
-/** @defgroup DAC_IT_definition
+/** @defgroup DAC_IT_definition DAC IT Definition
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
- ((IT) == DAC_IT_DMAUDR2))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
/** @brief Reset DAC handle state
* @param __HANDLE__: specifies the DAC handle.
@@ -226,34 +210,14 @@
* @param __DAC_Channel__: specifies the DAC channel
* @retval None
*/
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Disable the DAC channel
* @param __HANDLE__: specifies the DAC handle
* @param __DAC_Channel__: specifies the DAC channel.
* @retval None
*/
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Set DHR12R1 alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
-
-/** @brief Set DHR12R2 alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
-
-/** @brief Set DHR12RD alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Enable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle
@@ -269,39 +233,85 @@
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+/**
+ * @}
+ */
/* Include DAC HAL Extension module */
#include "stm32f4xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions *********************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+/**
+ * @}
+ */
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+/**
+ * @}
+ */
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+/**
+ * @}
+ */
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral State functions *************************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
@@ -311,8 +321,79 @@
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+/**
+ * @}
+ */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -60,27 +60,28 @@
* @{
*/
-/** @defgroup DACEx
+/** @defgroup DACEx DACEx
* @brief DAC driver modules
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DACEx_Group1 Extended features functions
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
@@ -153,7 +154,7 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel;
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -201,7 +202,7 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel;
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -248,7 +249,7 @@
}
tmp = (uint32_t)hdac->Instance;
- tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
@@ -363,7 +364,10 @@
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx
+ */
#endif /* HAL_DAC_MODULE_ENABLED */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,9 @@
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -57,28 +59,12 @@
*/
/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL State structures definition
- */
-
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_wave_generation
+/** @defgroup DACEx_Exported_Constants DAC Exported Constants
* @{
*/
-#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
-#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
- ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
- ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
-/**
- * @}
- */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
@@ -105,7 +91,55 @@
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group1
+ * @{
+ */
+/* Extension features functions ***********************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DACEx_Private_Macros DAC Private Macros
+ * @{
+ */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -134,37 +168,19 @@
* @}
*/
-/** @defgroup DACEx_wave_generation
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DAC Private Functions
* @{
*/
-#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
- ((WAVE) == DAC_WAVE_TRIANGLE))
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -96,14 +96,15 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @defgroup DCMI
+/** @defgroup DCMI DCMI
* @brief DCMI HAL module driver
* @{
*/
#ifdef HAL_DCMI_MODULE_ENABLED
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */
@@ -113,13 +114,13 @@
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup DCMI_Private_Functions
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
* @{
*/
-/** @defgroup DCMI_Group1 Initialization and Configuration functions
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -141,10 +142,10 @@
* the configuration information for DCMI.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+__weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
- if(hdcmi == HAL_NULL)
+ if(hdcmi == NULL)
{
return HAL_ERROR;
}
@@ -161,13 +162,14 @@
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdcmi->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DCMI_MspInit(hdcmi);
}
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
-
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |
@@ -183,6 +185,7 @@
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
+
}
/* Enable the Line interrupt */
@@ -266,7 +269,7 @@
/**
* @}
*/
-/** @defgroup DCMI_Group2 IO operation functions
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -294,7 +297,7 @@
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
- /* Initialise the second memory address */
+ /* Initialize the second memory address */
uint32_t SecondMemAddress = 0;
/* Check function parameters */
@@ -329,7 +332,7 @@
/* Set the DMA memory1 conversion complete callback */
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt;
- /* Initialise transfer parameters */
+ /* Initialize transfer parameters */
hdcmi->XferCount = 1;
hdcmi->XferSize = Length;
hdcmi->pBuffPtr = pData;
@@ -585,7 +588,7 @@
* @}
*/
-/** @defgroup DCMI_Group3 Peripheral Control functions
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -620,9 +623,9 @@
/* Check the parameters */
assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
- assert_param(IS_DCMI_WINDOW_COORDINATE(Y0));
+ assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
- assert_param(IS_DCMI_WINDOW_HEIGHT(YSize));
+ assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
/* Configure CROP */
DCMI->CWSIZER = (XSize | (YSize << 16));
@@ -693,7 +696,7 @@
* @}
*/
-/** @defgroup DCMI_Group4 Peripheral State functions
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -734,7 +737,11 @@
/**
* @}
*/
-
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -805,7 +812,12 @@
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_DCMI_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,21 +43,28 @@
extern "C" {
#endif
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+/* Include DCMI HAL Extended module */
+/* (include on top of file since DCMI structures are defined in extended file) */
+#include "stm32f4xx_hal_dcmi_ex.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @addtogroup DCMI
+/** @addtogroup DCMI DCMI
+ * @brief DCMI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup DCMI_Exported_Types DCMI Exported Types
+ * @{
+ */
/**
* @brief DCMI Error source
*/
@@ -67,46 +74,6 @@
DCMI_OVERRUN = 2, /*!< DCMI Overrun */
}DCMI_ErrorTypeDef;
-/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
- */
-typedef struct
-{
- uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
- uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
- uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
- uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-}DCMI_CodesInitTypeDef;
-
-/**
- * @brief DCMI Init structure definition
- */
-typedef struct
-{
- uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
- This parameter can be a value of @ref DCMI_Synchronization_Mode */
-
- uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
- This parameter can be a value of @ref DCMI_PIXCK_Polarity */
-
- uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_VSYNC_Polarity */
-
- uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_HSYNC_Polarity */
-
- uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
- This parameter can be a value of @ref DCMI_Capture_Rate */
-
- uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
- This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-
- DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
-
- uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
- This parameter can be a value of @ref DCMI_MODE_JPEG */
-
-}DCMI_InitTypeDef;
/**
* @brief HAL DCMI State structures definition
@@ -146,14 +113,16 @@
__IO uint32_t ErrorCode; /*!< DCMI Error code */
}DCMI_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DCMI_Exported_Constants
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
* @{
*/
-/** @defgroup DCMI_Error_Code
+/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
@@ -164,21 +133,18 @@
* @}
*/
-/** @defgroup DCMI_Capture_Mode
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */
-
-#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
- ((MODE) == DCMI_MODE_SNAPSHOT))
/**
* @}
*/
-/** @defgroup DCMI_Synchronization_Mode
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{
*/
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop)
@@ -186,75 +152,62 @@
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
-#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
- ((MODE) == DCMI_SYNCHRO_EMBEDDED))
/**
* @}
*/
-/** @defgroup DCMI_PIXCK_Polarity
+/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
* @{
*/
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
-#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
- ((POLARITY) == DCMI_PCKPOLARITY_RISING))
/**
* @}
*/
-
-/** @defgroup DCMI_VSYNC_Polarity
+
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
* @{
*/
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
-#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_VSPOLARITY_HIGH))
/**
* @}
*/
-/** @defgroup DCMI_HSYNC_Polarity
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
-#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_HSPOLARITY_HIGH))
/**
* @}
*/
-/** @defgroup DCMI_MODE_JPEG
+/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
* @{
*/
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
-#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
- ((JPEG_MODE) == DCMI_JPEG_ENABLE))
/**
* @}
*/
-/** @defgroup DCMI_Capture_Rate
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
* @{
*/
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
-#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
/**
* @}
*/
-/** @defgroup DCMI_Extended_Data_Mode
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
* @{
*/
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
@@ -262,35 +215,29 @@
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
-#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
- ((DATA) == DCMI_EXTEND_DATA_10B) || \
- ((DATA) == DCMI_EXTEND_DATA_12B) || \
- ((DATA) == DCMI_EXTEND_DATA_14B))
/**
* @}
*/
-/** @defgroup DCMI_Window_Coordinate
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{
*/
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
-#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
/**
* @}
*/
-/** @defgroup DCMI_Window_Height
+/** @defgroup DCMI_Window_Height DCMI Window Height
* @{
*/
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */
-#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
/**
* @}
*/
-/** @defgroup DCMI_interrupt_sources
+/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
* @{
*/
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
@@ -298,19 +245,11 @@
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
-
-#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
- ((IT) == DCMI_IT_OVF) || \
- ((IT) == DCMI_IT_ERR) || \
- ((IT) == DCMI_IT_VSYNC) || \
- ((IT) == DCMI_IT_LINE))
/**
* @}
*/
-/** @defgroup DCMI_Flags
+/** @defgroup DCMI_Flags DCMI Flags
* @{
*/
@@ -336,21 +275,6 @@
#define DCMI_FLAG_ERRMI ((uint32_t)0x1004)
#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)
#define DCMI_FLAG_LINEMI ((uint32_t)0x1010)
-#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
- ((FLAG) == DCMI_FLAG_VSYNC) || \
- ((FLAG) == DCMI_FLAG_FNE) || \
- ((FLAG) == DCMI_FLAG_FRAMERI) || \
- ((FLAG) == DCMI_FLAG_OVFRI) || \
- ((FLAG) == DCMI_FLAG_ERRRI) || \
- ((FLAG) == DCMI_FLAG_VSYNCRI) || \
- ((FLAG) == DCMI_FLAG_LINERI) || \
- ((FLAG) == DCMI_FLAG_FRAMEMI) || \
- ((FLAG) == DCMI_FLAG_OVFMI) || \
- ((FLAG) == DCMI_FLAG_ERRMI) || \
- ((FLAG) == DCMI_FLAG_VSYNCMI) || \
- ((FLAG) == DCMI_FLAG_LINEMI))
-
-#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
/**
* @}
*/
@@ -358,9 +282,12 @@
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
+ * @{
+ */
+
/** @brief Reset DCMI handle state
* @param __HANDLE__: specifies the DCMI handle.
* @retval None
@@ -453,15 +380,33 @@
* @retval The state of INTERRUPT.
*/
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
-
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMI_Exported_Functions
+ * @{
+ */
+/** @addtogroup DCMI_Exported_Functions_Group1
+ * @{
+ */
+
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
-
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group2
+ * @{
+ */
+
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
@@ -469,22 +414,94 @@
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
-
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
-
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral State functions *************************************************/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
- */
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Macros DCMI Private Macros
+ * @{
+ */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+ ((MODE) == DCMI_MODE_SNAPSHOT))
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+ ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+ ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+ ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
+ ((DATA) == DCMI_EXTEND_DATA_10B) || \
+ ((DATA) == DCMI_EXTEND_DATA_12B) || \
+ ((DATA) == DCMI_EXTEND_DATA_14B))
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,212 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi_ex.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief DCMI Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of DCMI extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### DCMI peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the DCMI interface for STM32F446xx
+ devices contains the following additional features :
+
+ (+) Support of Black and White cameras
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to manage the Black and White feature
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup DCMI DCMI
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMIEx_Exported_Functions DCMI Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup DCMIEx_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DCMI
+ (+) De-initialize the DCMI
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DCMI according to the specified
+ * parameters in the DCMI_InitTypeDef and create the associated handle.
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Check the DCMI peripheral state */
+ if(hdcmi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+#if defined(STM32F446xx)
+ assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
+ assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
+ assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
+ assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
+#endif
+ if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_DCMI_MspInit(hdcmi);
+ }
+
+ /* Change the DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+ /* Configures the HS, VS, DE and PC polarity */
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
+ DCMI_CR_ESS
+#if defined(STM32F446xx)
+ | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
+ DCMI_CR_LSM | DCMI_CR_OELS
+#endif
+ );
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
+ hdcmi->Init.JPEGMode
+#if defined(STM32F446xx)
+ | hdcmi->Init.ByteSelectMode |\
+ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
+ hdcmi->Init.LineSelectStart
+#endif
+ );
+ if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+ {
+ DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
+
+ }
+
+ /* Enable the Line interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
+
+ /* Enable the VSYNC interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
+
+ /* Enable the Frame capture complete interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+ /* Enable the Synchronization error interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
+
+ /* Enable the Overflow interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
+
+ /* Enable DCMI by setting DCMIEN bit */
+ __HAL_DCMI_ENABLE(hdcmi);
+
+ /* Update error code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,221 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi_ex.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Header file of DCMI Extension HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DCMI_EX_H
+#define __STM32F4xx_HAL_DCMI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCMIEx DCMI Extended
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMIEx_Exported_Types DCMI Extende Exported Types
+ * @{
+ */
+/**
+ * @brief DCMIEx Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
+}DCMI_CodesInitTypeDef;
+
+/**
+ * @brief DCMI Init structure definition
+ */
+typedef struct
+{
+ uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+ This parameter can be a value of @ref DCMI_Capture_Rate */
+
+ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+
+ DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
+
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+#if defined(STM32F446xx)
+ uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */
+
+ uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Start */
+
+ uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
+ This parameter can be a value of @ref DCMIEx_Line_Select_Mode */
+
+ uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMIEx_Line_Select_Start */
+
+#endif /* STM32F446xx */
+}DCMI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+#if defined(STM32F446xx)
+/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants
+ * @{
+ */
+
+/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode
+ * @{
+ */
+#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */
+#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
+#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
+#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start
+ * @{
+ */
+#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */
+#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode
+ * @{
+ */
+#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */
+#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start
+ * @{
+ */
+#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */
+#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros
+ * @{
+ */
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
+ ((MODE) == DCMI_BSM_OTHER) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_4) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_2))
+
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
+ ((POLARITY) == DCMI_OEBS_EVEN))
+
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
+ ((MODE) == DCMI_LSM_ALTERNATE_2))
+
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
+ ((POLARITY) == DCMI_OELS_EVEN))
+#endif /* STM32F446xx */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,6 +46,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
+#include "stm32_hal_legacy.h"
+#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
@@ -70,10 +72,9 @@
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
-#ifndef NULL
+//#ifndef NULL
#define HAL_NULL (void *) 0
-#endif
-
+//#endif
#define HAL_MAX_DELAY 0xFFFFFFFF
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
@@ -85,6 +86,8 @@
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
+#define UNUSED(x) ((void)(x))
+
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
@@ -188,6 +191,22 @@
#endif
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -120,30 +120,40 @@
* @{
*/
-/** @defgroup DMA
+/** @defgroup DMA DMA
* @brief DMA HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+ #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Private_Functions
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
* @{
*/
-/** @defgroup DMA_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
+/** @addtogroup DMA_Exported_Functions_Group1
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -203,11 +213,11 @@
/* Get the CR register value */
tmp = hdma->Instance->CR;
- /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and CT bits */
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
- DMA_SxCR_DIR | DMA_SxCR_CT ));
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
/* Prepare the DMA Stream configuration */
tmp |= hdma->Init.Channel | hdma->Init.Direction |
@@ -244,7 +254,7 @@
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
- /* Initialise the error code */
+ /* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
@@ -301,7 +311,7 @@
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- /* Initialise the error code */
+ /* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
@@ -317,9 +327,8 @@
* @}
*/
-/** @defgroup DMA_Group2 I/O operation functions
- * @brief I/O operation functions
- *
+/** @addtogroup DMA_Exported_Functions_Group2
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -818,9 +827,8 @@
* @}
*/
-/** @defgroup DMA_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
+/** @addtogroup DMA_Exported_Functions_Group3
+ *
@verbatim
===============================================================================
##### State and Errors functions #####
@@ -861,6 +869,14 @@
*/
/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
* @brief Sets the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
@@ -871,6 +887,9 @@
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
+ /* Clear DBM bit */
+ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
@@ -893,11 +912,10 @@
hdma->Instance->M0AR = DstAddress;
}
}
-
/**
* @}
- */
-
+ */
+
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,6 +56,11 @@
/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @brief DMA Exported Types
+ * @{
+ */
+
/**
* @brief DMA Configuration Structure definition
*/
@@ -97,7 +102,7 @@
This parameter can be a value of @ref DMA_FIFO_threshold_level */
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
+ It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref DMA_Memory_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
@@ -109,6 +114,7 @@
@note The burst mode is possible only if the address Increment mode is enabled. */
}DMA_InitTypeDef;
+
/**
* @brief HAL DMA State structures definition
*/
@@ -159,16 +165,22 @@
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
- __IO uint32_t ErrorCode; /*!< DMA Error code */
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
}DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_Exported_Constants
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @brief DMA Exported constants
* @{
*/
-/** @defgroup DMA_Error_Code
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @brief DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
@@ -180,7 +192,8 @@
* @}
*/
-/** @defgroup DMA_Channel_selection
+/** @defgroup DMA_Channel_selection DMA Channel selection
+ * @brief DMA channel selection
* @{
*/
#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
@@ -191,185 +204,134 @@
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
-
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
- ((CHANNEL) == DMA_CHANNEL_1) || \
- ((CHANNEL) == DMA_CHANNEL_2) || \
- ((CHANNEL) == DMA_CHANNEL_3) || \
- ((CHANNEL) == DMA_CHANNEL_4) || \
- ((CHANNEL) == DMA_CHANNEL_5) || \
- ((CHANNEL) == DMA_CHANNEL_6) || \
- ((CHANNEL) == DMA_CHANNEL_7))
/**
* @}
*/
-/** @defgroup DMA_Data_transfer_direction
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @brief DMA data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
/**
* @}
- */
-
-/** @defgroup DMA_Data_buffer_size
- * @{
- */
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/**
- * @}
- */
+ */
-/** @defgroup DMA_Peripheral_incremented_mode
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @brief DMA peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
/**
* @}
*/
-/** @defgroup DMA_Memory_incremented_mode
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @brief DMA memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
/**
* @}
*/
-/** @defgroup DMA_Peripheral_data_size
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @brief DMA peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
/**
* @}
*/
-
-/** @defgroup DMA_Memory_data_size
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @brief DMA memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
/**
* @}
*/
-/** @defgroup DMA_mode
+/** @defgroup DMA_mode DMA mode
+ * @brief DMA mode
* @{
*/
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR) || \
- ((MODE) == DMA_PFCTRL))
/**
* @}
*/
-/** @defgroup DMA_Priority_level
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @brief DMA priority levels
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
-/** @defgroup DMA_FIFO_direct_mode
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+ * @brief DMA FIFO direct mode
* @{
*/
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
- ((STATE) == DMA_FIFOMODE_ENABLE))
/**
* @}
*/
-/** @defgroup DMA_FIFO_threshold_level
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+ * @brief DMA FIFO level
* @{
*/
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
/**
* @}
*/
-/** @defgroup DMA_Memory_burst
+/** @defgroup DMA_Memory_burst DMA Memory burst
+ * @brief DMA memory burst
* @{
*/
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
- ((BURST) == DMA_MBURST_INC4) || \
- ((BURST) == DMA_MBURST_INC8) || \
- ((BURST) == DMA_MBURST_INC16))
/**
* @}
*/
-/** @defgroup DMA_Peripheral_burst
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+ * @brief DMA peripheral burst
* @{
*/
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
- ((BURST) == DMA_PBURST_INC4) || \
- ((BURST) == DMA_PBURST_INC8) || \
- ((BURST) == DMA_PBURST_INC16))
/**
* @}
*/
-/** @defgroup DMA_interrupt_enable_definitions
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @brief DMA interrupts definition
* @{
*/
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
@@ -381,7 +343,8 @@
* @}
*/
-/** @defgroup DMA_flag_definitions
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @brief DMA flag definitions
* @{
*/
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
@@ -407,11 +370,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset DMA handle state
@@ -664,21 +627,128 @@
#include "stm32f4xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
-
-/* Initialization and de-initialization functions *****************************/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @brief DMA Exported functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
-/* IO operation functions *****************************************************/
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+ * @brief I/O operation functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
-/* Peripheral State and Error functions ***************************************/
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @brief DMA private defines and constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA private macros
+ * @{
+ */
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+ ((CHANNEL) == DMA_CHANNEL_1) || \
+ ((CHANNEL) == DMA_CHANNEL_2) || \
+ ((CHANNEL) == DMA_CHANNEL_3) || \
+ ((CHANNEL) == DMA_CHANNEL_4) || \
+ ((CHANNEL) == DMA_CHANNEL_5) || \
+ ((CHANNEL) == DMA_CHANNEL_6) || \
+ ((CHANNEL) == DMA_CHANNEL_7))
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR) || \
+ ((MODE) == DMA_PFCTRL))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+ ((BURST) == DMA_MBURST_INC4) || \
+ ((BURST) == DMA_MBURST_INC8) || \
+ ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+ ((BURST) == DMA_PBURST_INC4) || \
+ ((BURST) == DMA_PBURST_INC8) || \
+ ((BURST) == DMA_PBURST_INC16))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @brief DMA private functions
+ * @{
+ */
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@@ -11,11 +11,11 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
+ *
+ @verbatim
+ ==============================================================================
##### How to use this driver #####
- ==============================================================================
+ ==============================================================================
[..]
(#) Program the required configuration through following parameters:
the Transfer Mode, the output color mode and the output offset using
@@ -87,7 +87,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -120,7 +120,7 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @defgroup DMA2D
+/** @addtogroup DMA2D
* @brief DMA2D HAL module driver
* @{
*/
@@ -129,18 +129,32 @@
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/* Private typedef -----------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup DMA2D_Private_Defines
+ * @{
+ */
#define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */
#define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */
-/* Private macro -------------------------------------------------------------*/
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+/** @addtogroup DMA2D_Private_Functions_Prototypes
+ * @{
+ */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMA2D_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_Exported_Functions
* @{
*/
@@ -184,6 +198,8 @@
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdma2d->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
}
@@ -336,10 +352,10 @@
* the color value if register to memory DMA2D mode is selected.
* @param DstAddress: The destination memory Buffer address.
* @param Width: The width of data to be transferred from source to destination.
- * @param Heigh: The heigh of data to be transferred from source to destination.
+ * @param Height: The height of data to be transferred from source to destination.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Process locked */
__HAL_LOCK(hdma2d);
@@ -348,14 +364,14 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Check the parameters */
- assert_param(IS_DMA2D_LINE(Heigh));
+ assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Disable the Peripheral */
__HAL_DMA2D_DISABLE(hdma2d);
/* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh);
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
@@ -373,10 +389,10 @@
* the color value if register to memory DMA2D mode is selected.
* @param DstAddress: The destination memory Buffer address.
* @param Width: The width of data to be transferred from source to destination.
- * @param Heigh: The heigh of data to be transferred from source to destination.
+ * @param Height: The height of data to be transferred from source to destination.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Process locked */
__HAL_LOCK(hdma2d);
@@ -385,14 +401,14 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Check the parameters */
- assert_param(IS_DMA2D_LINE(Heigh));
+ assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Disable the Peripheral */
__HAL_DMA2D_DISABLE(hdma2d);
/* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh);
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
/* Enable the transfer complete interrupt */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
@@ -417,10 +433,10 @@
* @param SrcAddress2: The source memory Buffer address of the background layer.
* @param DstAddress: The destination memory Buffer address
* @param Width: The width of data to be transferred from source to destination.
- * @param Heigh: The heigh of data to be transferred from source to destination.
+ * @param Height: The height of data to be transferred from source to destination.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Process locked */
__HAL_LOCK(hdma2d);
@@ -429,7 +445,7 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Check the parameters */
- assert_param(IS_DMA2D_LINE(Heigh));
+ assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Disable the Peripheral */
@@ -439,7 +455,7 @@
hdma2d->Instance->BGMAR = SrcAddress2;
/* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh);
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
@@ -455,10 +471,10 @@
* @param SrcAddress2: The source memory Buffer address of the background layer.
* @param DstAddress: The destination memory Buffer address.
* @param Width: The width of data to be transferred from source to destination.
- * @param Heigh: The heigh of data to be transferred from source to destination.
+ * @param Height: The height of data to be transferred from source to destination.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Process locked */
__HAL_LOCK(hdma2d);
@@ -467,7 +483,7 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Check the parameters */
- assert_param(IS_DMA2D_LINE(Heigh));
+ assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Disable the Peripheral */
@@ -477,7 +493,7 @@
hdma2d->Instance->BGMAR = SrcAddress2;
/* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh);
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
/* Enable the configuration error interrupt */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
@@ -1165,10 +1181,10 @@
* @param pdata: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param Width: The width of data to be transferred from source to destination.
- * @param Heigh: The heigh of data to be transferred from source to destination.
+ * @param Height: The height of data to be transferred from source to destination.
* @retval HAL status
*/
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
uint32_t tmp = 0;
uint32_t tmp1 = 0;
@@ -1179,7 +1195,7 @@
tmp = Width << 16;
/* Configure DMA2D data size */
- hdma2d->Instance->NLR = (Heigh | tmp);
+ hdma2d->Instance->NLR = (Height | tmp);
/* Configure DMA2D destination address */
hdma2d->Instance->OMAR = DstAddress;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -51,12 +51,15 @@
* @{
*/
-/** @addtogroup DMA2D
+/** @defgroup DMA2D DMA2D
+ * @brief DMA2D HAL module driver
* @{
- */
-
+ */
+
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
+ * @{
+ */
#define MAX_DMA2D_LAYER 2
/**
@@ -158,23 +161,16 @@
__IO uint32_t ErrorCode; /*!< DMA2D Error code */
} DMA2D_HandleTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA2D_Exported_Constants
- * @{
- */
-
-/** @defgroup DMA2D_Layer
- * @{
- */
-#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
/**
* @}
*/
-/** @defgroup DMA2D_Error_Code
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{
*/
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
@@ -185,21 +181,18 @@
* @}
*/
-/** @defgroup DMA2D_Mode
+/** @defgroup DMA2D_Mode DMA2D Mode
* @{
*/
#define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
-
-#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
- ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
/**
* @}
*/
-/** @defgroup DMA2D_Color_Mode
+/** @defgroup DMA2D_Color_Mode DMA2D Color Mode
* @{
*/
#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
@@ -207,48 +200,36 @@
#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
-
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
- ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
- ((MODE_ARGB) == DMA2D_ARGB4444))
/**
* @}
*/
-/** @defgroup DMA2D_COLOR_VALUE
+/** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
* @{
*/
-
#define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
-
-#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
/**
* @}
*/
-/** @defgroup DMA2D_SIZE
+/** @defgroup DMA2D_SIZE DMA2D SIZE
* @{
*/
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
-
-#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
-#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
/**
* @}
*/
-/** @defgroup DMA2D_Offset
+/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
-
-#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
/**
* @}
*/
-/** @defgroup DMA2D_Input_Color_Mode
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{
*/
#define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
@@ -262,64 +243,47 @@
#define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
#define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
#define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
-
-#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
- ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
- ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
- ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
- ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
- ((INPUT_CM) == CM_A4))
/**
* @}
*/
-/** @defgroup DMA2D_ALPHA_MODE
+/** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
* @{
*/
#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
with original alpha channel value */
-
-#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
- ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
- ((AlphaMode) == DMA2D_COMBINE_ALPHA))
/**
* @}
*/
-/** @defgroup DMA2D_CLUT_CM
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
* @{
*/
#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
-
-#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
/**
* @}
*/
-/** @defgroup DMA2D_Size_Clut
+/** @defgroup DMA2D_Size_Clut DMA2D Size Clut
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
-
-#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
/**
* @}
*/
-/** @defgroup DMA2D_DeadTime
+/** @defgroup DMA2D_DeadTime DMA2D DeadTime
* @{
*/
#define LINE_WATERMARK DMA2D_LWR_LW
-
-#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
/**
* @}
*/
-/** @defgroup DMA2D_Interrupts
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts
* @{
*/
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
@@ -328,15 +292,11 @@
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
-
-#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
- ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
- ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
/**
* @}
*/
-/** @defgroup DMA2D_Flag
+/** @defgroup DMA2D_Flag DMA2D Flag
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
@@ -345,10 +305,6 @@
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
-
-#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
- ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
- ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
@@ -357,6 +313,9 @@
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
+ * @{
+ */
/** @brief Reset DMA2D handle state
* @param __HANDLE__: specifies the DMA2D handle.
@@ -453,9 +412,14 @@
* @retval The state of INTERRUPT.
*/
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
+ * @{
+ */
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
@@ -463,10 +427,10 @@
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
@@ -483,8 +447,93 @@
/* Peripheral State functions ***************************************************/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+/**
+ * @}
+ */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/* Private types -------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Types DMA2D Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Defines DMA2D Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Variables DMA2D Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
+ * @{
+ */
+#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
+ ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
+ ((MODE_ARGB) == DMA2D_ARGB4444))
+#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
+#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
+#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
+ ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
+ ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
+ ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
+ ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
+ ((INPUT_CM) == CM_A4))
+#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
+ ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
+/**
+ * @}
+ */
+
+/* Private functions prototypes ---------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -493,12 +542,13 @@
/**
* @}
*/
-
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_DMA2D_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@@ -27,7 +27,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -61,30 +61,35 @@
* @{
*/
-/** @defgroup DMAEx
+/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Functions
+/** @addtogroup DMAEx_Exported_Functions
* @{
*/
-/** @defgroup DMAEx_Group1 Extended features functions
- * @brief Extended features functions
- *
+/** @addtogroup DMAEx_Exported_Functions_Group1
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -245,6 +250,14 @@
*/
/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
+
+/**
* @brief Set the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,11 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+ * @brief DMAEx Exported types
+ * @{
+ */
+
/**
* @brief HAL DMA Memory definition
*/
@@ -66,10 +70,21 @@
}HAL_DMA_MemoryTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+ * @brief DMAEx Exported functions
+ * @{
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
@@ -78,6 +93,22 @@
/**
* @}
*/
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+ * @brief DMAEx Private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -87,6 +118,6 @@
}
#endif
-#endif /* __STM32F4xx_HAL_DMA_H */
+#endif /*__STM32F4xx_HAL_DMA_EX_H*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_eth.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@@ -26,9 +26,9 @@
(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
(##) Enable the Ethernet interface clock using
- (+++) __ETHMAC_CLK_ENABLE();
- (+++) __ETHMACTX_CLK_ENABLE();
- (+++) __ETHMACRX_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
(##) Initialize the related GPIO clocks
(##) Configure Ethernet pin-out
@@ -63,12 +63,15 @@
(#) Configure the Ethernet DMA after ETH peripheral initialization
HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
+
+ -@- The PTP protocol and the DMA descriptors ring mode are not supported
+ in this driver
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +105,7 @@
* @{
*/
-/** @defgroup ETH
+/** @defgroup ETH ETH
* @brief ETH HAL module driver
* @{
*/
@@ -113,12 +116,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @defgroup ETH_Private_Constants ETH Private Constants
+ * @{
+ */
#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ETH_Private_Functions ETH Private Functions
+ * @{
+ */
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
@@ -131,14 +143,17 @@
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
-/** @defgroup ETH_Private_Functions
+/** @defgroup ETH_Exported_Functions ETH Exported Functions
* @{
*/
-/** @defgroup ETH_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@@ -161,7 +176,7 @@
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
- uint32_t tmpreg = 0, phyreg = 0;
+ uint32_t tmpreg1 = 0, phyreg = 0;
uint32_t hclk = 60000000;
uint32_t tickstart = 0;
uint32_t err = ETH_SUCCESS;
@@ -180,12 +195,14 @@
if(heth->State == HAL_ETH_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ heth->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
}
/* Enable SYSCFG Clock */
- __SYSCFG_CLK_ENABLE();
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
@@ -203,9 +220,9 @@
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
- tmpreg = (heth->Instance)->MACMIIAR;
+ tmpreg1 = (heth->Instance)->MACMIIAR;
/* Clear CSR Clock Range CR[2:0] bits */
- tmpreg &= MACMIIAR_CR_MASK;
+ tmpreg1 &= ETH_MACMIIAR_CR_MASK;
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
@@ -214,31 +231,31 @@
if((hclk >= 20000000)&&(hclk < 35000000))
{
/* CSR Clock Range between 20-35 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
}
else if((hclk >= 35000000)&&(hclk < 60000000))
{
/* CSR Clock Range between 35-60 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
}
else if((hclk >= 60000000)&&(hclk < 100000000))
{
/* CSR Clock Range between 60-100 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else if((hclk >= 100000000)&&(hclk < 150000000))
{
/* CSR Clock Range between 100-150 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
}
else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
{
/* CSR Clock Range between 150-168 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
- (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
+ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
@@ -599,7 +616,7 @@
* @}
*/
-/** @defgroup ETH_Group2 IO operation functions
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -1014,7 +1031,7 @@
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
uint32_t tickstart = 0;
/* Check parameters */
@@ -1029,25 +1046,25 @@
heth->State = HAL_ETH_STATE_BUSY_RD;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII address register value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
- while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
@@ -1060,7 +1077,7 @@
return HAL_TIMEOUT;
}
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Get MACMIIDR value */
@@ -1086,7 +1103,7 @@
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
uint32_t tickstart = 0;
/* Check parameters */
@@ -1101,28 +1118,28 @@
heth->State = HAL_ETH_STATE_BUSY_WR;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII register address value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
- while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
@@ -1135,7 +1152,7 @@
return HAL_TIMEOUT;
}
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Set ETH HAL State to READY */
@@ -1149,7 +1166,7 @@
* @}
*/
-/** @defgroup ETH_Group3 Peripheral Control functions
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -1257,7 +1274,7 @@
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1287,7 +1304,7 @@
assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
- assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
@@ -1301,11 +1318,11 @@
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
- tmpreg |= (uint32_t)(macconf->Watchdog |
+ tmpreg1 |= (uint32_t)(macconf->Watchdog |
macconf->Jabber |
macconf->InterFrameGap |
macconf->CarrierSense |
@@ -1320,13 +1337,13 @@
macconf->DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
@@ -1341,9 +1358,9 @@
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
@@ -1354,11 +1371,11 @@
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
- tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) |
macconf->ZeroQuantaPause |
macconf->PauseLowThreshold |
macconf->UnicastPauseFrameDetect |
@@ -1366,13 +1383,13 @@
macconf->TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
@@ -1380,29 +1397,29 @@
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear FES and DM bits */
- tmpreg &= ~((uint32_t)0x00004800);
+ tmpreg1 &= ~((uint32_t)0x00004800);
- tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
+ tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/* Set the ETH state to Ready */
@@ -1424,7 +1441,7 @@
*/
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1452,11 +1469,11 @@
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
- tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
dmaconf->ReceiveStoreForward |
dmaconf->FlushReceivedFrame |
dmaconf->TransmitStoreForward |
@@ -1467,13 +1484,13 @@
dmaconf->SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
@@ -1487,9 +1504,9 @@
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
@@ -1505,7 +1522,7 @@
* @}
*/
-/** @defgroup ETH_Group4 Peripheral State functions
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -1538,6 +1555,14 @@
/**
* @}
*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Functions
+ * @{
+ */
/**
* @brief Configures Ethernet MAC and DMA with default parameters.
@@ -1550,7 +1575,7 @@
{
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
{
@@ -1585,7 +1610,7 @@
macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
- macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
macinit.HashTableHigh = 0x0;
@@ -1601,9 +1626,9 @@
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
/* Set the WD bit according to ETH Watchdog value */
/* Set the JD: bit according to ETH Jabber value */
/* Set the IFG bit according to ETH InterFrameGap value */
@@ -1617,7 +1642,7 @@
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
- tmpreg |= (uint32_t)(macinit.Watchdog |
+ tmpreg1 |= (uint32_t)(macinit.Watchdog |
macinit.Jabber |
macinit.InterFrameGap |
macinit.CarrierSense |
@@ -1632,13 +1657,13 @@
macinit.DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Set the RA bit according to ETH ReceiveAll value */
@@ -1661,9 +1686,9 @@
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
@@ -1674,9 +1699,9 @@
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
/* Set the PT bit according to ETH PauseTime value */
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
@@ -1684,7 +1709,7 @@
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
- tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) |
macinit.ZeroQuantaPause |
macinit.PauseLowThreshold |
macinit.UnicastPauseFrameDetect |
@@ -1692,13 +1717,13 @@
macinit.TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
@@ -1708,9 +1733,9 @@
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
@@ -1731,9 +1756,9 @@
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
/* Set the RSF bit according to ETH ReceiveStoreForward value */
@@ -1744,7 +1769,7 @@
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
- tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
dmainit.ReceiveStoreForward |
dmainit.FlushReceivedFrame |
dmainit.TransmitStoreForward |
@@ -1755,13 +1780,13 @@
dmainit.SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration ------------------*/
/* Set the AAL bit according to ETH AddressAlignedBeats value */
@@ -1782,9 +1807,9 @@
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
@@ -1811,20 +1836,20 @@
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
- uint32_t tmpreg;
+ uint32_t tmpreg1;
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
- tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+ tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
/* Load the selected MAC address high register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
/* Calculate the selected MAC address low register */
- tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+ tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
/* Load the selected MAC address low register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
}
/**
@@ -1835,16 +1860,16 @@
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1855,16 +1880,16 @@
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1875,16 +1900,16 @@
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1895,16 +1920,16 @@
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1963,16 +1988,16 @@
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
}
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_eth.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,8 +54,322 @@
/** @addtogroup ETH
* @{
*/
+
+/** @addtogroup ETH_Private_Macros
+ * @{
+ */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M))
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+ ((CMD) == ETH_WATCHDOG_DISABLE))
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+ ((CMD) == ETH_JABBER_DISABLE))
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEAll_DISABLE))
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+ ((CMD) == ETH_FIXEDBURST_DISABLE))
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+ ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Defines
+ * @{
+ */
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+
+/* ETHERNET Errors */
+#define ETH_SUCCESS ((uint32_t)0)
+#define ETH_ERROR ((uint32_t)1)
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+ /**
+ * @}
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+ * @{
+ */
/**
* @brief HAL State structures definition
@@ -117,7 +431,7 @@
uint32_t Watchdog; /*!< Selects or not the Watchdog timer
When enabled, the MAC allows no more then 2048 bytes to be received.
When disabled, the MAC can receive up to 16384 bytes.
- This parameter can be a value of @ref ETH_watchdog */
+ This parameter can be a value of @ref ETH_Watchdog */
uint32_t Jabber; /*!< Selects or not Jabber timer
When enabled, the MAC allows no more then 2048 bytes to be sent.
@@ -341,29 +655,26 @@
} ETH_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
-
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
-
-/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+ /**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+ * @{
+ */
-/* ETHERNET Errors */
-#define ETH_SUCCESS ((uint32_t)0)
-#define ETH_ERROR ((uint32_t)1)
-
-/** @defgroup ETH_Buffers_setting
+/** @defgroup ETH_Buffers_setting ETH Buffers setting
* @{
*/
-#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
-#define VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
-#define MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
-#define MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
-#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
+#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
/* Ethernet driver receive buffers are organized in a chained linked-list, when
an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
@@ -418,9 +729,16 @@
#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
+ /**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
+ * @{
+ */
/*
- DMA Tx Desciptor
+ DMA Tx Descriptor
-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-----------------------------------------------------------------------------------------------
@@ -496,9 +814,7 @@
/**
* @}
*/
-
-
-/** @defgroup ETH_DMA_Rx_descriptor
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
* @{
*/
@@ -593,97 +909,81 @@
/* Bit definition of RDES7 register */
#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
-
-
- /** @defgroup ETH_AutoNegotiation
+/**
+ * @}
+ */
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
* @{
*/
#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
- ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+
/**
* @}
*/
-/** @defgroup ETH_Speed
+/** @defgroup ETH_Speed ETH Speed
* @{
*/
#define ETH_SPEED_10M ((uint32_t)0x00000000)
#define ETH_SPEED_100M ((uint32_t)0x00004000)
-#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
- ((SPEED) == ETH_SPEED_100M))
+
/**
* @}
*/
-/** @defgroup ETH_Duplex_Mode
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
* @{
*/
#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
- ((MODE) == ETH_MODE_HALFDUPLEX))
/**
* @}
*/
-/** @defgroup ETH_Rx_Mode
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
* @{
*/
#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
- ((MODE) == ETH_RXINTERRUPT_MODE))
/**
* @}
*/
-/** @defgroup ETH_Checksum_Mode
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
* @{
*/
#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
-#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
- ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
/**
* @}
*/
-/** @defgroup ETH_Media_Interface
+/** @defgroup ETH_Media_Interface ETH Media Interface
* @{
*/
#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
-#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
- ((MODE) == ETH_MEDIA_INTERFACE_RMII))
-
/**
* @}
*/
-/** @defgroup ETH_watchdog
+/** @defgroup ETH_Watchdog ETH Watchdog
* @{
*/
#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
-#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
- ((CMD) == ETH_WATCHDOG_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Jabber
+/** @defgroup ETH_Jabber ETH Jabber
* @{
*/
#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
-#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
- ((CMD) == ETH_JABBER_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Inter_Frame_Gap
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
* @{
*/
#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
@@ -694,334 +994,238 @@
#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
-#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_40BIT))
-
/**
* @}
*/
-/** @defgroup ETH_Carrier_Sense
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
* @{
*/
#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
-#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
-#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
- ((CMD) == ETH_CARRIERSENCE_DISABLE))
-
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
/**
* @}
*/
-/** @defgroup ETH_Receive_Own
+/** @defgroup ETH_Receive_Own ETH Receive Own
* @{
*/
#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
-#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
-#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
- ((CMD) == ETH_RECEIVEOWN_DISABLE))
-
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
/**
* @}
*/
-/** @defgroup ETH_Loop_Back_Mode
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
* @{
*/
#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
- ((CMD) == ETH_LOOPBACKMODE_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Checksum_Offload
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
* @{
*/
#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
- ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Retry_Transmission
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
* @{
*/
#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
-#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
- ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Automatic_Pad_CRC_Strip
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
* @{
*/
#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
- ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Back_Off_Limit
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
* @{
*/
#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
-#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_1))
-
/**
* @}
*/
-/** @defgroup ETH_Deferral_Check
+/** @defgroup ETH_Deferral_Check ETH Deferral Check
* @{
*/
#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
- ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Receive_All
+/** @defgroup ETH_Receive_All ETH Receive All
* @{
*/
#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
- ((CMD) == ETH_RECEIVEAll_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Source_Addr_Filter
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
* @{
*/
#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Pass_Control_Frames
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
* @{
*/
#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
-#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
-
/**
* @}
*/
-/** @defgroup ETH_Broadcast_Frames_Reception
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
* @{
*/
#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
-#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
- ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Destination_Addr_Filter
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
* @{
*/
#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
-#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
- ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
-
/**
* @}
*/
-/** @defgroup ETH_Promiscuous_Mode
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
* @{
*/
-#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
-#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) || \
- ((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
-
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
-/** @defgroup ETH_Multicast_Frames_Filter
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
* @{
*/
#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
-#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
/**
* @}
*/
-/** @defgroup ETH_Unicast_Frames_Filter
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
* @{
*/
#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
/**
* @}
*/
-/** @defgroup ETH_Pause_Time
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
* @{
*/
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
-
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
/**
* @}
*/
-/** @defgroup ETH_Zero_Quanta_Pause
- * @{
- */
-#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
-#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
-#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
- ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
-/**
- * @}
- */
-
-/** @defgroup ETH_Pause_Low_Threshold
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
* @{
*/
#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
-#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
/**
* @}
*/
-/** @defgroup ETH_Unicast_Pause_Frame_Detect
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
* @{
*/
#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
- ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Receive_Flow_Control
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
* @{
*/
#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Transmit_Flow_Control
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
* @{
*/
#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_VLAN_Tag_Comparison
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
* @{
*/
#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
-#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
- ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
-
/**
* @}
*/
-/** @defgroup ETH_MAC_addresses
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
* @{
*/
#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
-#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
- ((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
/**
* @}
*/
-/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
* @{
*/
#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
-#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
- ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
/**
* @}
*/
-/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
* @{
*/
#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
@@ -1030,108 +1234,81 @@
#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
-#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
-
/**
* @}
*/
-/** @defgroup ETH_MAC_Debug_flags
+/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
* @{
*/
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
-
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
-
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
-
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
-
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
-
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
-
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
-
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
-
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
-
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
-
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
-
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
/**
* @}
*/
-/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
* @{
*/
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
-#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
- ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Receive_Store_Forward
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
* @{
*/
#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Flush_Received_Frame
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
* @{
*/
#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
-#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
- ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Transmit_Store_Forward
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
* @{
*/
#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Transmit_Threshold_Control
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
* @{
*/
#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
@@ -1142,93 +1319,67 @@
#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
/**
* @}
*/
-/** @defgroup ETH_Forward_Error_Frames
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
* @{
*/
#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Forward_Undersized_Good_Frames
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
* @{
*/
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Receive_Threshold_Control
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
* @{
*/
#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
/**
* @}
*/
-/** @defgroup ETH_Second_Frame_Operate
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
* @{
*/
#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
- ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Address_Aligned_Beats
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
* @{
*/
#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
- ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Fixed_Burst
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
* @{
*/
#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
- ((CMD) == ETH_FIXEDBURST_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Rx_DMA_Burst_Length
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
* @{
*/
#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
@@ -1243,25 +1394,11 @@
#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
-
-#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
-
/**
* @}
*/
-/** @defgroup ETH_Tx_DMA_Burst_Length
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
* @{
*/
#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
@@ -1276,40 +1413,20 @@
#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+/**
+ * @}
+ */
-#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-
-/** @defgroup ETH_DMA_Enhanced_descriptor_format
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
* @{
*/
#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
-
-#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
- ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
-
/**
* @}
*/
-/**
- * @brief ETH DMA Descriptor SkipLength
- */
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
-
-
-/** @defgroup ETH_DMA_Arbitration
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
*/
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
@@ -1317,211 +1434,70 @@
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
-#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
- ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_descriptor_flags
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
* @{
*/
-#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
- ((FLAG) == ETH_DMATXDESC_IC) || \
- ((FLAG) == ETH_DMATXDESC_LS) || \
- ((FLAG) == ETH_DMATXDESC_FS) || \
- ((FLAG) == ETH_DMATXDESC_DC) || \
- ((FLAG) == ETH_DMATXDESC_DP) || \
- ((FLAG) == ETH_DMATXDESC_TTSE) || \
- ((FLAG) == ETH_DMATXDESC_TER) || \
- ((FLAG) == ETH_DMATXDESC_TCH) || \
- ((FLAG) == ETH_DMATXDESC_TTSS) || \
- ((FLAG) == ETH_DMATXDESC_IHE) || \
- ((FLAG) == ETH_DMATXDESC_ES) || \
- ((FLAG) == ETH_DMATXDESC_JT) || \
- ((FLAG) == ETH_DMATXDESC_FF) || \
- ((FLAG) == ETH_DMATXDESC_PCE) || \
- ((FLAG) == ETH_DMATXDESC_LCA) || \
- ((FLAG) == ETH_DMATXDESC_NC) || \
- ((FLAG) == ETH_DMATXDESC_LCO) || \
- ((FLAG) == ETH_DMATXDESC_EC) || \
- ((FLAG) == ETH_DMATXDESC_VF) || \
- ((FLAG) == ETH_DMATXDESC_CC) || \
- ((FLAG) == ETH_DMATXDESC_ED) || \
- ((FLAG) == ETH_DMATXDESC_UF) || \
- ((FLAG) == ETH_DMATXDESC_DB))
-
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_descriptor_segment
- * @{
- */
-#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
-#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
- ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
* @{
*/
#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-/**
- * @brief ETH DMA Tx Desciptor buffer size
- */
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
-
/**
* @}
*/
-/** @defgroup ETH_DMA_Rx_descriptor_flags
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
* @{
*/
-#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
- ((FLAG) == ETH_DMARXDESC_AFM) || \
- ((FLAG) == ETH_DMARXDESC_ES) || \
- ((FLAG) == ETH_DMARXDESC_DE) || \
- ((FLAG) == ETH_DMARXDESC_SAF) || \
- ((FLAG) == ETH_DMARXDESC_LE) || \
- ((FLAG) == ETH_DMARXDESC_OE) || \
- ((FLAG) == ETH_DMARXDESC_VLAN) || \
- ((FLAG) == ETH_DMARXDESC_FS) || \
- ((FLAG) == ETH_DMARXDESC_LS) || \
- ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
- ((FLAG) == ETH_DMARXDESC_LC) || \
- ((FLAG) == ETH_DMARXDESC_FT) || \
- ((FLAG) == ETH_DMARXDESC_RWT) || \
- ((FLAG) == ETH_DMARXDESC_RE) || \
- ((FLAG) == ETH_DMARXDESC_DBE) || \
- ((FLAG) == ETH_DMARXDESC_CE) || \
- ((FLAG) == ETH_DMARXDESC_MAMPCE))
-
-/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
-#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) || \
- ((FLAG) == ETH_DMAPTPRXDESC_PTPFT) || \
- ((FLAG) == ETH_DMAPTPRXDESC_PTPMT) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPCB) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPPE) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPHE) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPPT))
-
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
/**
* @}
*/
-/** @defgroup ETH_DMA_Rx_descriptor_buffers_
- * @{
- */
-#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
-#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
- ((BUFFER) == ETH_DMARXDESC_BUFFER2))
-
-
-/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
-
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_PMT_Flags
+/** @defgroup ETH_PMT_Flags ETH PMT Flags
* @{
*/
#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
-#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
- ((FLAG) == ETH_PMT_FLAG_MPR))
/**
* @}
*/
-/** @defgroup ETH_MMC_Tx_Interrupts
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
* @{
*/
#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
-
/**
* @}
*/
-/** @defgroup ETH_MMC_Rx_Interrupts
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
* @{
*/
#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
-#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
- ((IT) != 0x00))
-#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
- ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
- ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
/**
* @}
*/
-/** @defgroup ETH_MMC_Registers
- * @{
- */
-#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
-#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
-#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
-#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
-#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
-#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
-#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
-#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
-#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
-#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
-#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
-
-/**
- * @brief ETH MMC registers
- */
-#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
- ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
- ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
- ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
- ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
- ((REG) == ETH_MMCRGUFCR))
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Flags
+/** @defgroup ETH_MAC_Flags ETH MAC Flags
* @{
*/
#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
@@ -1529,21 +1505,18 @@
#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
-#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
- ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
- ((FLAG) == ETH_MAC_FLAG_PMT))
/**
* @}
*/
-/** @defgroup ETH_DMA_Flags
+/** @defgroup ETH_DMA_Flags ETH DMA Flags
* @{
*/
#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
@@ -1560,24 +1533,11 @@
#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
-
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
-#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
- ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
- ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
- ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
- ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
- ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
- ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
- ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
- ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
- ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
- ((FLAG) == ETH_DMA_FLAG_T))
/**
* @}
*/
-/** @defgroup ETH_MAC_Interrupts
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
* @{
*/
#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
@@ -1585,15 +1545,11 @@
#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
-#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
-#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
- ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
- ((IT) == ETH_MAC_IT_PMT))
/**
* @}
*/
-/** @defgroup ETH_DMA_Interrupts
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
*/
#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
@@ -1614,23 +1570,11 @@
#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
-
-#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
-#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
- ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
- ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
- ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
- ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
- ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
- ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
- ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
- ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
-
/**
* @}
*/
-/** @defgroup ETH_DMA_transmit_process_state_
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
* @{
*/
#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
@@ -1645,7 +1589,7 @@
*/
-/** @defgroup ETH_DMA_receive_process_state_
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
* @{
*/
#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
@@ -1659,47 +1603,34 @@
* @}
*/
-/** @defgroup ETH_DMA_overflow_
+/** @defgroup ETH_DMA_overflow ETH DMA overflow
* @{
*/
#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
-#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
- ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
/**
* @}
*/
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
-
-/* ETHERNET MACMIIAR register Mask */
-#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
-
-/* ETHERNET MACCR register Mask */
-#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+ * @{
+ */
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
-/* ETHERNET MACFCR register Mask */
-#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
-
-
-/* ETHERNET DMAOMR register Mask */
-#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
-
-
-/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8
-
-/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
/** @brief Reset ETH handle state
* @param __HANDLE__: specifies the ETH handle.
* @retval None
@@ -1709,7 +1640,7 @@
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__: specifies the flag of TDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
@@ -1717,7 +1648,7 @@
/**
* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__: specifies the flag of RDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
@@ -1882,7 +1813,7 @@
* @brief Enables the specified ETHERNET DMA interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * enabled @defgroup ETH_DMA_Interrupts
+ * enabled @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
@@ -1891,7 +1822,7 @@
* @brief Disables the specified ETHERNET DMA interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * disabled. @defgroup ETH_DMA_Interrupts
+ * disabled. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
@@ -1899,7 +1830,7 @@
/**
* @brief Clears the ETHERNET DMA IT pending bit.
* @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
@@ -1907,7 +1838,7 @@
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check. @defgroup ETH_DMA_Flags
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
@@ -1915,7 +1846,7 @@
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to clear. @defgroup ETH_DMA_Flags
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
@@ -2117,74 +2048,102 @@
* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
* @retval None
*/
-#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Enables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enable event on ETH External event line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disable event on ETH External event line
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Get flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Clear flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
-/** @defgroup ETH_EXTI_LINE_WAKEUP
- * @{
- */
-#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
+/**
+ * @brief Enables rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
/**
* @}
*/
-
-/**
- * @brief Enables the ETH External interrupt line.
- * @param None
- * @retval None
- */
-#define __HAL_ETH_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disables the ETH External interrupt line.
- * @param None
- * @retval None
- */
-#define __HAL_ETH_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Get flag of the ETH External interrupt line.
- * @param None
- * @retval None
- */
-#define __HAL_ETH_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Clear flag of the ETH External interrupt line.
- * @param None
- * @retval None
- */
-#define __HAL_ETH_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Sets rising edge trigger to the ETH External interrupt line.
- * @param None
- * @retval None
- */
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
-
-/**
- * @brief Sets falling edge trigger to the ETH External interrupt line.
- * @param None
- * @retval None
- */
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP);\
- EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Sets rising/falling edge trigger to the ETH External interrupt line.
- * @param None
- * @retval None
- */
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
-
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ETH_Exported_Functions
+ * @{
+ */
+
/* Initialization and de-initialization functions ****************************/
+
+/** @addtogroup ETH_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
@@ -2192,41 +2151,67 @@
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+/**
+ * @}
+ */
/* IO operation functions ****************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group2
+ * @{
+ */
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
-
- /* Non-Blocking mode: Interrupt */
+/* Communication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
-
- /* Callback in non blocking modes (Interrupt) */
+/* Callback in non blocking modes (Interrupt) */
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-
-/* Cmmunication with PHY functions*/
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+/**
+ * @}
+ */
/* Peripheral Control functions **********************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group3
+ * @{
+ */
+
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
-
-/* Peripheral State functions ************************************************/
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
+/* Peripheral State functions ************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group4
+ * @{
+ */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
+
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#ifdef __cplusplus
}
@@ -2235,5 +2220,4 @@
#endif /* __STM32F4xx_HAL_ETH_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -99,7 +99,7 @@
* @{
*/
-/** @defgroup FLASH
+/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
@@ -108,16 +108,29 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
/* Variable used for Erase sectors under interruption */
FLASH_ProcessTypeDef pFlash;
-
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
/* Program operations */
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
@@ -126,13 +139,16 @@
static void FLASH_SetErrorCode(void);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
-/** @defgroup FLASH_Group1 Programming operation functions
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
@@ -164,24 +180,24 @@
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- if(TypeProgram == TYPEPROGRAM_BYTE)
+ if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_WORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
@@ -193,7 +209,7 @@
}
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
FLASH->CR &= (~FLASH_CR_PG);
@@ -222,7 +238,7 @@
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Enable End of FLASH Operation interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
@@ -237,17 +253,17 @@
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
pFlash.Address = Address;
- if(TypeProgram == TYPEPROGRAM_BYTE)
+ if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_WORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
@@ -263,7 +279,6 @@
/**
* @brief This function handles FLASH interrupt request.
- * @param None
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
@@ -300,7 +315,8 @@
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
/*Increment sector number*/
- temp = ++pFlash.Sector;
+ pFlash.Sector++;
+ temp = pFlash.Sector;
FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
}
else
@@ -317,7 +333,7 @@
}
else
{
- if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
/*MassErase ended. Return the selected bank*/
/* FLASH EOP interrupt user callback */
@@ -346,14 +362,14 @@
temp = pFlash.Sector;
pFlash.Sector = 0xFFFFFFFF;
}
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
/*return the faulty bank*/
temp = pFlash.Bank;
}
else
{
- /*retrun the faulty address*/
+ /*return the faulty address*/
temp = pFlash.Address;
}
@@ -419,7 +435,7 @@
* @}
*/
-/** @defgroup FLASH_Group2 Peripheral Control functions
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
@@ -436,7 +452,6 @@
/**
* @brief Unlock the FLASH control register access
- * @param None
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
@@ -457,7 +472,6 @@
/**
* @brief Locks the FLASH control register access
- * @param None
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
@@ -468,10 +482,8 @@
return HAL_OK;
}
-
/**
* @brief Unlock the FLASH Option Control Registers access.
- * @param None
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
@@ -492,7 +504,6 @@
/**
* @brief Lock the FLASH Option Control Registers access.
- * @param None
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
@@ -505,7 +516,6 @@
/**
* @brief Launch the option byte loading.
- * @param None
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
@@ -514,14 +524,14 @@
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
/* Wait for last operation to be completed */
- return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
-/** @defgroup FLASH_Group3 Peripheral State and Errors functions
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
@@ -537,16 +547,15 @@
/**
* @brief Get the specific FLASH error flag.
- * @param None
- * @retval FLASH_ErrorCode: The returned value can be:
- * @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
- * @arg FLASH_ERROR_PGS: FLASH Programming Sequence error flag
- * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
- * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
- * @arg FLASH_ERROR_WRP: FLASH Write protected error flag
- * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag
+ * @retval FLASH_ErrorCode: The returned value can be a combination of:
+ * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+ * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
+ * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
+ * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+ * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+ * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
*/
-FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
+uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
@@ -563,6 +572,10 @@
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
uint32_t tickstart = 0;
+
+ /* Clear Error Code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
@@ -696,39 +709,38 @@
/**
* @brief Set the specific FLASH error flag.
- * @param None
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
- pFlash.ErrorCode = FLASH_ERROR_WRP;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
{
- pFlash.ErrorCode |= (FLASH_ErrorTypeDef)FLASH_ERROR_PGA;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_PGP;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_PGS;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_RD;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_OPERATION;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
}
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,20 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief FLASH Error structure definition
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
*/
-typedef enum
-{
- FLASH_ERROR_RD = 0x01,
- FLASH_ERROR_PGS = 0x02,
- FLASH_ERROR_PGP = 0x04,
- FLASH_ERROR_PGA = 0x08,
- FLASH_ERROR_WRP = 0x10,
- FLASH_ERROR_OPERATION = 0x20
-}FLASH_ErrorTypeDef;
-
+
/**
* @brief FLASH Procedure structure definition
*/
@@ -79,7 +70,6 @@
FLASH_PROC_PROGRAM
} FLASH_ProcedureTypeDef;
-
/**
* @brief FLASH handle Structure definition
*/
@@ -89,7 +79,7 @@
__IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
- __IO uint8_t VoltageForErase; /*Internal variable to provide voltange range selected by user in IT context*/
+ __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/
__IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
@@ -99,34 +89,40 @@
HAL_LockTypeDef Lock; /* FLASH locking object */
- __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
+ __IO uint32_t ErrorCode; /* FLASH error code */
}FLASH_ProcessTypeDef;
-/**
- * @brief FLASH Error source
- */
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
-
-
-
+/** @defgroup FLASH_Error_Code FLASH Error Code
+ * @brief FLASH Error Code
+ * @{
+ */
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000001) /*!< Read Protection error */
+#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002) /*!< Programming Sequence error */
+#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004) /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) /*!< Programming Alignment error */
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010) /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020) /*!< Operation Error */
+/**
+ * @}
+ */
+
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
-#define TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */
-#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */
-#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */
-#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */
-
-#define IS_TYPEPROGRAM(VALUE)(((VALUE) == TYPEPROGRAM_BYTE) || \
- ((VALUE) == TYPEPROGRAM_HALFWORD) || \
- ((VALUE) == TYPEPROGRAM_WORD) || \
- ((VALUE) == TYPEPROGRAM_DOUBLEWORD))
-
+#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */
/**
* @}
*/
@@ -143,7 +139,6 @@
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-
/**
* @}
*/
@@ -154,7 +149,6 @@
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
-
/**
* @}
*/
@@ -183,33 +177,14 @@
* @}
*/
-/**
- * @brief ACR register byte 0 (Bits[7:0]) base address
- */
-#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
-/**
- * @brief OPTCR register byte 0 (Bits[7:0]) base address
- */
-#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
-/**
- * @brief OPTCR register byte 1 (Bits[15:8]) base address
- */
-#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
-/**
- * @brief OPTCR register byte 2 (Bits[23:16]) base address
- */
-#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
-/**
- * @brief OPTCR register byte 3 (Bits[31:24]) base address
- */
-#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
-
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @{
+ */
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__: FLASH Latency
@@ -259,15 +234,18 @@
* @note This function must be used only when the Instruction Cache is disabled.
* @retval None
*/
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_ICRST)
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
+ FLASH->ACR &= ~FLASH_ACR_ICRST; \
+ }while(0)
/**
* @brief Resets the FLASH data Cache.
* @note This function must be used only when the data Cache is disabled.
* @retval None
*/
-#define __HAL_FLASH_DATA_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_DCRST)
-
+#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
+ FLASH->ACR &= ~FLASH_ACR_DCRST; \
+ }while(0)
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
@@ -318,33 +296,127 @@
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+/**
+ * @}
+ */
/* Include FLASH HAL Extension module */
#include "stm32f4xx_hal_flash_ex.h"
#include "stm32f4xx_hal_flash_ramfunc.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
/* Program operation functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
+void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions ************************************************/
-FLASH_ErrorTypeDef HAL_FLASH_GetError(void);
+uint32_t HAL_FLASH_GetError(void);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @brief ACR register byte 0 (Bits[7:0]) base address
+ */
+#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+/**
+ * @brief OPTCR register byte 0 (Bits[7:0]) base address
+ */
+#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
+/**
+ * @brief OPTCR register byte 1 (Bits[15:8]) base address
+ */
+#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
+/**
+ * @brief OPTCR register byte 2 (Bits[23:16]) base address
+ */
+#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
+/**
+ * @brief OPTCR register byte 3 (Bits[31:24]) base address
+ */
+#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
+ * @{
+ */
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -42,7 +42,7 @@
(#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
(++) Extended space (bank 2) erase function
(++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
- (++) Dual Boot actrivation
+ (++) Dual Boot activation
(++) Write protection configuration for bank 2
(++) PCROP protection configuration and control for both banks
@@ -50,7 +50,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -84,7 +84,7 @@
* @{
*/
-/** @defgroup FLASHEx
+/** @defgroup FLASHEx FLASHEx
* @brief FLASH HAL Extension module driver
* @{
*/
@@ -93,14 +93,29 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Variables
+ * @{
+ */
extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
/* Option bytes control */
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
@@ -113,10 +128,10 @@
static FlagStatus FLASH_OB_GetRDP(void);
static uint8_t FLASH_OB_GetBOR(void);
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector);
static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector);
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
@@ -124,14 +139,17 @@
static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
-/* Private functions ---------------------------------------------------------*/
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
-/** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/
-/** @defgroup FLASHEx_Group1 Extended IO operation functions
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
* @brief Extended IO operation functions
*
@verbatim
@@ -165,23 +183,23 @@
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- if (status == HAL_OK)
+ if(status == HAL_OK)
{
/*Initialization of SectorError variable*/
*SectorError = 0xFFFFFFFF;
- if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_MER_BIT);
@@ -189,7 +207,7 @@
else
{
/* Check the parameters */
- assert_param(IS_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
/* Erase by sector by sector to be done*/
for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
@@ -197,13 +215,13 @@
FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the SER Bit */
FLASH->CR &= (~FLASH_CR_SER);
FLASH->CR &= SECTOR_MASK;
- if (status != HAL_OK)
+ if(status != HAL_OK)
{
/* In case of error, stop erase procedure and return the faulty sector*/
*SectorError = index;
@@ -234,7 +252,7 @@
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Enable End of FLASH Operation interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
@@ -246,7 +264,7 @@
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
- if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
@@ -258,7 +276,7 @@
/* Erase by sector to be done*/
/* Check the parameters */
- assert_param(IS_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
pFlash.NbSectorsToErase = pEraseInit->NbSectors;
@@ -293,7 +311,7 @@
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
{
assert_param(IS_WRPSTATE(pOBInit->WRPState));
- if (pOBInit->WRPState == WRPSTATE_ENABLE)
+ if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
{
/*Enable of Write protection on the selected Sector*/
status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
@@ -356,7 +374,7 @@
}
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/**
* @brief Program option bytes
* @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
@@ -372,33 +390,33 @@
assert_param(IS_OBEX(pAdvOBInit->OptionType));
/*Program PCROP option byte*/
- if (((pAdvOBInit->OptionType) & OBEX_PCROP) == OBEX_PCROP)
+ if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
{
/* Check the parameters */
assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
- if ((pAdvOBInit->PCROPState) == PCROPSTATE_ENABLE)
+ if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
{
/*Enable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
}
else
{
/*Disable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
}
}
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
/*Program BOOT config option byte*/
- if (((pAdvOBInit->OptionType) & OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG)
+ if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
{
status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
}
@@ -416,7 +434,7 @@
*/
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
{
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/*Get Sector*/
pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
@@ -428,7 +446,7 @@
/*Get Boot config OB*/
pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
}
/**
@@ -437,10 +455,9 @@
* @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted
* Global Read Out Protection modification (from level1 to level0)
* @note Once SPRMOD bit is active unprotection of a protected sector is not possible
- * @note Read a prtotected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- * @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx devices.
*
- * @param None
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
@@ -454,7 +471,6 @@
*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
return HAL_OK;
-
}
/**
@@ -463,10 +479,9 @@
* @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted
* Global Read Out Protection modification (from level1 to level0)
* @note Once SPRMOD bit is active unprotection of a protected sector is not possible
- * @note Read a prtotected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- * @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx devices.
*
- * @param None
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
@@ -481,15 +496,12 @@
return HAL_OK;
}
-
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-
/**
* @brief Returns the FLASH Write Protection Option Bytes value for Bank 2
* @note This function can be used only for STM32F427X and STM32F429X devices.
- * @param None
* @retval The FLASH Write Protection Option Bytes value
*/
uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
@@ -508,13 +520,13 @@
* @brief Full erase of FLASH memory sectors
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
- * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
- * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
- * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
- * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @param Banks: Banks to be erased
@@ -560,13 +572,13 @@
* The value of this parameter depend on device used within the same series
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
- * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
- * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
- * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
- * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @retval None
@@ -579,15 +591,15 @@
assert_param(IS_FLASH_SECTOR(Sector));
assert_param(IS_VOLTAGERANGE(VoltageRange));
- if(VoltageRange == VOLTAGE_RANGE_1)
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
{
tmp_psize = FLASH_PSIZE_BYTE;
}
- else if(VoltageRange == VOLTAGE_RANGE_2)
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
{
tmp_psize = FLASH_PSIZE_HALF_WORD;
}
- else if(VoltageRange == VOLTAGE_RANGE_3)
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
{
tmp_psize = FLASH_PSIZE_WORD;
}
@@ -597,7 +609,7 @@
}
/* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
- if (Sector > FLASH_SECTOR_11)
+ if(Sector > FLASH_SECTOR_11)
{
Sector += 4;
}
@@ -640,14 +652,14 @@
assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+ if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
(WRPSector < OB_WRP_SECTOR_12))
{
- if (WRPSector == OB_WRP_SECTOR_All)
+ if(WRPSector == OB_WRP_SECTOR_All)
{
/*Write protection on all sector of BANK1*/
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12));
@@ -665,10 +677,10 @@
}
/*Write protection on all sector of BANK2*/
- if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+ if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
{
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -677,7 +689,6 @@
}
}
-
return status;
}
@@ -701,7 +712,7 @@
* @arg FLASH_BANK_2: Bank2 to be erased
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
*
- * @retval HAL Staus
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
{
@@ -712,14 +723,14 @@
assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+ if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
(WRPSector < OB_WRP_SECTOR_12))
{
- if (WRPSector == OB_WRP_SECTOR_All)
+ if(WRPSector == OB_WRP_SECTOR_All)
{
/*Write protection on all sector of BANK1*/
*(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12);
@@ -737,10 +748,10 @@
}
/*Write protection on all sector of BANK2*/
- if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+ if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
{
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -772,7 +783,7 @@
assert_param(IS_OB_BOOT(BootConfig));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -811,11 +822,11 @@
assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+ if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
{
assert_param(IS_OB_PCROP(SectorBank1));
/*Write protection done on sectors of BANK1*/
@@ -829,11 +840,11 @@
}
/*Write protection on all sector of BANK2*/
- if (Banks == FLASH_BANK_BOTH)
+ if(Banks == FLASH_BANK_BOTH)
{
assert_param(IS_OB_PCROP(SectorBank2));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -876,11 +887,11 @@
assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+ if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
{
assert_param(IS_OB_PCROP(SectorBank1));
/*Write protection done on sectors of BANK1*/
@@ -894,11 +905,11 @@
}
/*Write protection on all sector of BANK2*/
- if (Banks == FLASH_BANK_BOTH)
+ if(Banks == FLASH_BANK_BOTH)
{
assert_param(IS_OB_PCROP(SectorBank2));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -916,18 +927,18 @@
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/**
* @brief Mass erase of FLASH memory
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
- * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
- * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
- * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
- * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @param Banks: Banks to be erased
@@ -957,13 +968,13 @@
* The value of this parameter depend on device used within the same series
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
- * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
- * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
- * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
- * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @retval None
@@ -976,15 +987,15 @@
assert_param(IS_FLASH_SECTOR(Sector));
assert_param(IS_VOLTAGERANGE(VoltageRange));
- if(VoltageRange == VOLTAGE_RANGE_1)
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
{
tmp_psize = FLASH_PSIZE_BYTE;
}
- else if(VoltageRange == VOLTAGE_RANGE_2)
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
{
tmp_psize = FLASH_PSIZE_HALF_WORD;
}
- else if(VoltageRange == VOLTAGE_RANGE_3)
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
{
tmp_psize = FLASH_PSIZE_WORD;
}
@@ -1027,7 +1038,7 @@
assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -1063,7 +1074,7 @@
assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -1072,9 +1083,9 @@
return status;
}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/**
* @brief Enable the read/write protection (PCROP) of the desired sectors.
* @note This function can be used only for STM32F401xx devices.
@@ -1092,7 +1103,7 @@
assert_param(IS_OB_PCROP(Sector));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -1120,7 +1131,7 @@
assert_param(IS_OB_PCROP(Sector));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -1130,7 +1141,7 @@
return status;
}
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
/**
* @brief Set the read protection level.
@@ -1152,7 +1163,7 @@
assert_param(IS_OB_RDP_LEVEL(Level));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -1189,7 +1200,7 @@
assert_param(IS_OB_STDBY_SOURCE(Stdby));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -1229,7 +1240,6 @@
/**
* @brief Return the FLASH User Option Byte value.
- * @param None
* @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
* and RST_STDBY(Bit2).
*/
@@ -1241,7 +1251,6 @@
/**
* @brief Return the FLASH Write Protection Option Bytes value.
- * @param None
* @retval uint16_t FLASH Write Protection Option Bytes value
*/
static uint16_t FLASH_OB_GetWRP(void)
@@ -1252,8 +1261,7 @@
/**
* @brief Returns the FLASH Read Protection level.
- * @param None
- * @retval FlagStatus FLASH ReadOut Protection Status:
+ * @retval FlagStatus FLASH Readout Protection Status:
* - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
* - RESET, when OB_RDP_Level_0 is set
*/
@@ -1261,7 +1269,7 @@
{
FlagStatus readstatus = RESET;
- if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_LEVEL_0))
+ if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_LEVEL_0))
{
readstatus = SET;
}
@@ -1271,7 +1279,6 @@
/**
* @brief Returns the FLASH BOR level.
- * @param None
* @retval uint8_t The FLASH BOR level:
* - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
* - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,9 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+ * @{
+ */
/**
* @brief FLASH Erase structure definition
@@ -109,7 +112,7 @@
* @brief FLASH Advanced Option Bytes Program structure definition
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
typedef struct
{
uint32_t OptionType; /*!< Option byte to be configured for extension.
@@ -118,10 +121,10 @@
uint32_t PCROPState; /*!< PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
-#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE)
+#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE) || defined (STM32F446xx)
uint16_t Sectors; /*!< specifies the sector(s) set for PCROP.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors.
@@ -138,7 +141,10 @@
#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
} FLASH_AdvOBProgramInitTypeDef;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
@@ -149,12 +155,8 @@
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
-#define TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
-#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
-
-#define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \
- ((VALUE) == TYPEERASE_MASSERASE))
-
+#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
/**
* @}
*/
@@ -162,16 +164,10 @@
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
-#define VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
-#define VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
-#define VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
-#define VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \
- ((RANGE) == VOLTAGE_RANGE_2) || \
- ((RANGE) == VOLTAGE_RANGE_3) || \
- ((RANGE) == VOLTAGE_RANGE_4))
-
+#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
+#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
+#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
+#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
/**
* @}
*/
@@ -179,12 +175,8 @@
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
-#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
-#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
-
-#define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \
- ((VALUE) == WRPSTATE_ENABLE))
-
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
/**
* @}
*/
@@ -196,9 +188,6 @@
#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */
-
-#define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-
/**
* @}
*/
@@ -210,9 +199,6 @@
#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
/*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1))/*||\
- ((LEVEL) == OB_RDP_LEVEL_2))*/
/**
* @}
*/
@@ -222,7 +208,6 @@
*/
#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
@@ -232,7 +217,6 @@
*/
#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
@@ -243,7 +227,6 @@
*/
#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
@@ -255,23 +238,17 @@
#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
- ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
/**
* @}
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
* @{
*/
-#define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable PCROP */
-#define PCROPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable PCROP */
-
-#define IS_PCROPSTATE(VALUE)(((VALUE) == PCROPSTATE_DISABLE) || \
- ((VALUE) == PCROPSTATE_ENABLE))
-
+#define OB_PCROP_STATE_DISABLE ((uint32_t)0x00) /*!< Disable PCROP */
+#define OB_PCROP_STATE_ENABLE ((uint32_t)0x01) /*!< Enable PCROP */
/**
* @}
*/
@@ -281,20 +258,13 @@
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-#define OBEX_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */
-#define OBEX_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */
-
-#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP) || \
- ((VALUE) == OBEX_BOOTCONFIG))
-
+#define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-#define OBEX_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */
-
-#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP))
-
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
/**
* @}
*/
@@ -320,30 +290,12 @@
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
-
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
- ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || \
- ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4) || \
- ((LATENCY) == FLASH_LATENCY_5) || \
- ((LATENCY) == FLASH_LATENCY_6) || \
- ((LATENCY) == FLASH_LATENCY_7) || \
- ((LATENCY) == FLASH_LATENCY_8) || \
- ((LATENCY) == FLASH_LATENCY_9) || \
- ((LATENCY) == FLASH_LATENCY_10) || \
- ((LATENCY) == FLASH_LATENCY_11) || \
- ((LATENCY) == FLASH_LATENCY_12) || \
- ((LATENCY) == FLASH_LATENCY_13) || \
- ((LATENCY) == FLASH_LATENCY_14) || \
- ((LATENCY) == FLASH_LATENCY_15))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
/*--------------------------------------------------------------------------------------------------------------*/
/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx -----------------------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
@@ -353,17 +305,7 @@
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
-
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
- ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || \
- ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4) || \
- ((LATENCY) == FLASH_LATENCY_5) || \
- ((LATENCY) == FLASH_LATENCY_6) || \
- ((LATENCY) == FLASH_LATENCY_7))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
/*--------------------------------------------------------------------------------------------------------------*/
/**
@@ -378,18 +320,12 @@
#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
-
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
-
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
/**
* @}
*/
@@ -402,9 +338,9 @@
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
/**
* @}
*/
@@ -438,21 +374,6 @@
#define FLASH_SECTOR_21 ((uint32_t)21) /*!< Sector Number 21 */
#define FLASH_SECTOR_22 ((uint32_t)22) /*!< Sector Number 22 */
#define FLASH_SECTOR_23 ((uint32_t)23) /*!< Sector Number 23 */
-
-#define FLASH_SECTOR_TOTAL 24
-
-#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
- ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
- ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
- ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
- ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
- ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
- ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
- ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
- ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
- ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
- ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
- ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
/*-----------------------------------------------------------------------------------------------------*/
@@ -470,15 +391,6 @@
#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
-
-#define FLASH_SECTOR_TOTAL 12
-
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
- ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
- ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
- ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
- ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
- ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/*-----------------------------------------------------------------------------------------------------*/
@@ -490,17 +402,11 @@
#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
-
-#define FLASH_SECTOR_TOTAL 6
-
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
- ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
- ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5))
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
-/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE)
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
@@ -509,17 +415,8 @@
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
-
-#define FLASH_SECTOR_TOTAL 8
-
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
- ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
- ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
- ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/*-----------------------------------------------------------------------------------------------------*/
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < FLASH_END))
-#define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
/**
* @}
@@ -555,8 +452,6 @@
#define OB_WRP_SECTOR_22 ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22 */
#define OB_WRP_SECTOR_23 ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
/*-----------------------------------------------------------------------------------------------------*/
@@ -575,8 +470,6 @@
#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/*-----------------------------------------------------------------------------------------------------*/
@@ -589,13 +482,11 @@
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
-/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE)
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
@@ -605,9 +496,7 @@
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/*-----------------------------------------------------------------------------------------------------*/
/**
* @}
@@ -643,8 +532,6 @@
#define OB_PCROP_SECTOR_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
#define OB_PCROP_SECTOR_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
-
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
/*-----------------------------------------------------------------------------------------------------*/
@@ -657,13 +544,11 @@
#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
-
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
-/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE)
+/*------------------------------ STM32F401xE/STM32F411xE/STM32F446xx ----------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
@@ -673,9 +558,7 @@
#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
-
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/*-----------------------------------------------------------------------------------------------------*/
/**
@@ -688,7 +571,6 @@
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
-#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
/**
* @}
@@ -698,21 +580,13 @@
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
#define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
-#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
/**
* @}
*/
-
-/**
- * @brief OPTCR1 register byte 2 (Bits[23:16]) base address
- */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
/**
* @}
@@ -721,7 +595,13 @@
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
/* Extension Program operation functions *************************************/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
@@ -729,18 +609,245 @@
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
+ * @{
+ */
+/*--------------------------------------- STM32F42xxx/STM32F43xxx--------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_SECTOR_TOTAL 24
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FLASH_SECTOR_TOTAL 12
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_TOTAL 6
+#endif /* STM32F401xC */
+
+/*--------------------------------- STM32F401xE/STM32F411xE/STM32F446xx -------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define FLASH_SECTOR_TOTAL 8
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+/**
+ * @brief OPTCR1 register byte 2 (Bits[23:16]) base address
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
+ ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+ ((LEVEL) == OB_RDP_LEVEL_2))*/
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
+ ((VALUE) == OB_PCROP_STATE_ENABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
+ ((VALUE) == OPTIONBYTE_BOOTCONFIG))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7) || \
+ ((LATENCY) == FLASH_LATENCY_8) || \
+ ((LATENCY) == FLASH_LATENCY_9) || \
+ ((LATENCY) == FLASH_LATENCY_10) || \
+ ((LATENCY) == FLASH_LATENCY_11) || \
+ ((LATENCY) == FLASH_LATENCY_12) || \
+ ((LATENCY) == FLASH_LATENCY_13) || \
+ ((LATENCY) == FLASH_LATENCY_14) || \
+ ((LATENCY) == FLASH_LATENCY_15))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
+ ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
+ ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
+ ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
+ ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
+ ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
+ ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
+ * @{
+ */
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
@@ -36,7 +36,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -70,27 +70,26 @@
* @{
*/
-/** @defgroup FLASH_RAMFUNC
+/** @defgroup FLASHRAMFUNC FLASH RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
-#if defined(STM32F411xE)
+#if defined(STM32F411xE) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_RAMFUNC_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASHRAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
* @{
*/
-/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM
+/** @defgroup FLASHRAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
* @brief Peripheral Extended features functions
*
@verbatim
@@ -109,15 +108,14 @@
/**
* @brief Stop the flash interface while System Run
* @note This mode is only available for STM32F411xx devices.
- * @note This mode could n't be set while executing with the flash itself.
+ * @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
- * @param None
* @retval None
*/
__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void)
{
/* Enable Power ctrl clock */
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Stop the flash interface while System Run */
SET_BIT(PWR->CR, PWR_CR_FISSR);
@@ -127,15 +125,14 @@
/**
* @brief Start the flash interface while System Run
* @note This mode is only available for STM32F411xx devices.
- * @note This mode could n't be set while executing with the flash itself.
+ * @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
- * @param None
* @retval None
*/
__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void)
{
/* Enable Power ctrl clock */
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Start the flash interface while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
@@ -147,13 +144,12 @@
* @note This mode is only available for STM32F411xx devices.
* @note This mode could n't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
- * @param None
* @retval None
*/
__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void)
{
/* Enable Power ctrl clock */
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable the flash sleep while System Run */
SET_BIT(PWR->CR, PWR_CR_FMSSR);
@@ -163,15 +159,14 @@
/**
* @brief Disable the flash sleep while System Run
* @note This mode is only available for STM32F411xx devices.
- * @note This mode could n't be set while executing with the flash itself.
+ * @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
- * @param None
* @retval None
*/
__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void)
{
/* Enable Power ctrl clock */
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Disable the flash sleep while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
@@ -186,7 +181,7 @@
* @}
*/
-#endif /* STM32F411xE */
+#endif /* STM32F411xE || STM32F446xx */
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F411xE)
+#if defined(STM32F411xE) || defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -52,18 +52,31 @@
* @{
*/
-/** @addtogroup FLASH_RAMFUNC
+/** @addtogroup FLASHRAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHRAMFUNC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASHRAMFUNC_Exported_Functions_Group1
+ * @{
+ */
__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void);
__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void);
__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void);
__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
#endif /* STM32F411xE */
/**
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,4098 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief FMPI2C HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The FMPI2C HAL driver can be used as follows:
+
+ (#) Declare a FMPI2C_HandleTypeDef handle structure, for example:
+ FMPI2C_HandleTypeDef hfmpi2c;
+
+ (#)Initialize the FMPI2C low level resources by implement the HAL_FMPI2C_MspInit ()API:
+ (##) Enable the FMPI2Cx interface clock
+ (##) FMPI2C pins configuration
+ (+++) Enable the clock for the FMPI2C GPIOs
+ (+++) Configure FMPI2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the FMPI2Cx interrupt priority
+ (+++) Enable the NVIC FMPI2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream
+ (+++) Associate the initilalized DMA handle to the hfmpi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.
+
+ (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init() API:
+ (+++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_FMPI2C_MspInit(&hfmpi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady()
+
+ (#) For FMPI2C IO and IO MEM operations, three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Transmit_IT()
+ (+) At transmission end of transfer HAL_FMPI2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Receive_IT()
+ (+) At reception end of transfer HAL_FMPI2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer HAL_FMPI2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_FMPI2C_Slave_Receive_IT()
+ (+) At reception end of transfer HAL_FMPI2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+ HAL_FMPI2C_Mem_Write_IT()
+ (+) At MEM end of write transfer HAL_FMPI2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+ HAL_FMPI2C_Mem_Read_IT()
+ (+) At MEM end of read transfer HAL_FMPI2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer HAL_FMPI2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Master_Receive_DMA()
+ (+) At reception end of transfer HAL_FMPI2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer HAL_FMPI2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Slave_Receive_DMA()
+ (+) At reception end of transfer HAL_FMPI2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+ HAL_FMPI2C_Mem_Write_DMA()
+ (+) At MEM end of write transfer HAL_FMPI2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+ HAL_FMPI2C_Mem_Read_DMA()
+ (+) At MEM end of read transfer HAL_FMPI2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+
+ *** FMPI2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in FMPI2C HAL driver.
+
+ (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
+ (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
+ (+) __HAL_FMPI2C_GET_FLAG : Checks whether the specified FMPI2C flag is set or not
+ (+) __HAL_FMPI2C_CLEAR_FLAG : Clears the specified FMPI2C pending flag
+ (+) __HAL_FMPI2C_ENABLE_IT: Enables the specified FMPI2C interrupt
+ (+) __HAL_FMPI2C_DISABLE_IT: Disables the specified FMPI2C interrupt
+
+ [..]
+ (@) You can refer to the FMPI2C HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMPI2C FMPI2C
+ * @brief FMPI2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FMPI2C_Private_Constants
+ * @{
+ */
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! FMPI2C TIMING clear register Mask */
+#define FMPI2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
+#define FMPI2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FMPI2C_Private_Functions
+ * @brief FMPI2C private functions
+ * @{
+ */
+static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+
+static HAL_StatusTypeDef FMPI2C_MasterTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+static HAL_StatusTypeDef FMPI2C_MasterReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+
+static HAL_StatusTypeDef FMPI2C_SlaveTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+static HAL_StatusTypeDef FMPI2C_SlaveReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FMPI2C_Exported_Functions FMPI2C Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the FMPI2Cx peripheral:
+
+ (+) User must Implement HAL_FMPI2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_FMPI2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_FMPI2C_DeInit() to restore the default configuration
+ of the selected FMPI2Cx periperal.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMPI2C according to the specified parameters
+ * in the FMPI2C_InitTypeDef and create the associated handle.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the FMPI2C handle allocation */
+ if(hfmpi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_OWN_ADDRESS1(hfmpi2c->Init.OwnAddress1));
+ assert_param(IS_FMPI2C_ADDRESSING_MODE(hfmpi2c->Init.AddressingMode));
+ assert_param(IS_FMPI2C_DUAL_ADDRESS(hfmpi2c->Init.DualAddressMode));
+ assert_param(IS_FMPI2C_OWN_ADDRESS2(hfmpi2c->Init.OwnAddress2));
+ assert_param(IS_FMPI2C_OWN_ADDRESS2_MASK(hfmpi2c->Init.OwnAddress2Masks));
+ assert_param(IS_FMPI2C_GENERAL_CALL(hfmpi2c->Init.GeneralCallMode));
+ assert_param(IS_FMPI2C_NO_STRETCH(hfmpi2c->Init.NoStretchMode));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfmpi2c->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_FMPI2C_MspInit(hfmpi2c);
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /*---------------------------- FMPI2Cx TIMINGR Configuration ------------------*/
+ /* Configure FMPI2Cx: Frequency range */
+ hfmpi2c->Instance->TIMINGR = hfmpi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- FMPI2Cx OAR1 Configuration ---------------------*/
+ /* Configure FMPI2Cx: Own Address1 and ack own address1 mode */
+ hfmpi2c->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN;
+ if(hfmpi2c->Init.OwnAddress1 != 0)
+ {
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
+ {
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1);
+ }
+ else /* FMPI2C_ADDRESSINGMODE_10BIT */
+ {
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- FMPI2Cx CR2 Configuration ----------------------*/
+ /* Configure FMPI2Cx: Addressing Master mode */
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hfmpi2c->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK);
+
+ /*---------------------------- FMPI2Cx OAR2 Configuration ---------------------*/
+ /* Configure FMPI2Cx: Dual mode and Own Address2 */
+ hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/
+ /* Configure FMPI2Cx: Generalcall and NoStretch mode */
+ hfmpi2c->Instance->CR1 = (hfmpi2c->Init.GeneralCallMode | hfmpi2c->Init.NoStretchMode);
+
+ /* Enable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FMPI2C peripheral.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the FMPI2C handle allocation */
+ if(hfmpi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the FMPI2C Peripheral Clock */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_FMPI2C_MspDeInit(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief FMPI2C MSP Init.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FMPI2C MSP DeInit
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group2 I/O operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FMPI2C data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated FMPI2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_FMPI2C_Master_Transmit()
+ (++) HAL_FMPI2C_Master_Receive()
+ (++) HAL_FMPI2C_Slave_Transmit()
+ (++) HAL_FMPI2C_Slave_Receive()
+ (++) HAL_FMPI2C_Mem_Write()
+ (++) HAL_FMPI2C_Mem_Read()
+ (++) HAL_FMPI2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_FMPI2C_Master_Transmit_IT()
+ (++) HAL_FMPI2C_Master_Receive_IT()
+ (++) HAL_FMPI2C_Slave_Transmit_IT()
+ (++) HAL_FMPI2C_Slave_Receive_IT()
+ (++) HAL_FMPI2C_Mem_Write_IT()
+ (++) HAL_FMPI2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_FMPI2C_Master_Transmit_DMA()
+ (++) HAL_FMPI2C_Master_Receive_DMA()
+ (++) HAL_FMPI2C_Slave_Transmit_DMA()
+ (++) HAL_FMPI2C_Slave_Receive_DMA()
+ (++) HAL_FMPI2C_Mem_Write_DMA()
+ (++) HAL_FMPI2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_FMPI2C_MemTxCpltCallback()
+ (++) HAL_FMPI2C_MemRxCpltCallback()
+ (++) HAL_FMPI2C_MasterTxCpltCallback()
+ (++) HAL_FMPI2C_MasterRxCpltCallback()
+ (++) HAL_FMPI2C_SlaveTxCpltCallback()
+ (++) HAL_FMPI2C_SlaveRxCpltCallback()
+ (++) HAL_FMPI2C_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*pData++);
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TXE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Write data to RXDR */
+ (*pData++) =hfmpi2c->Instance->RXDR;
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Read data from TXDR */
+ hfmpi2c->Instance->TXDR = (*pData++);
+ Size--;
+ }while(Size > 0);
+
+ /* Wait until STOP flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hfmpi2c->Instance->RXDR;
+ Size--;
+ }
+
+ /* Wait until STOP flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferSize = Size;
+ hfmpi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferSize = Size;
+ hfmpi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = Size;
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* If 10bits addressing mode is selected */
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferSize = Size;
+ hfmpi2c->XferCount = Size;
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, Size);
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is set Receiver mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, FMPI2C_TIMEOUT_DIR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to DR */
+ hfmpi2c->Instance->TXDR = (*pData++);
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hfmpi2c->Instance->RXDR;
+
+ /* Decrement the Size counter */
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_RX;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c, FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMemTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_RX;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMemReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param Trials: Number of trials
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ __IO uint32_t FMPI2C_Trials = 0;
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hfmpi2c->Instance->CR2 = __HAL_FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode,DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Device is ready */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (FMPI2C_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ }
+ }while(FMPI2C_Trials < Trials);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles FMPI2C event interrupt request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* FMPI2C in mode Transmitter ---------------------------------------------------*/
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI | FMPI2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX)
+ {
+ FMPI2C_SlaveTransmit_ISR(hfmpi2c);
+ }
+ }
+
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_TX))
+ {
+ FMPI2C_MasterTransmit_ISR(hfmpi2c);
+ }
+ }
+
+ /* FMPI2C in mode Receiver ----------------------------------------------------*/
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI | FMPI2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX)
+ {
+ FMPI2C_SlaveReceive_ISR(hfmpi2c);
+ }
+ }
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_RX))
+ {
+ FMPI2C_MasterReceive_ISR(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief This function handles FMPI2C error interrupt request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* FMPI2C Bus error interrupt occurred ------------------------------------*/
+ if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BERR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_BERR);
+ }
+
+ /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_OVR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_OVR);
+ }
+
+ /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FMPI2C error callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the FMPI2C state.
+ * @param hfmpi2c : FMPI2C handle
+ * @retval HAL state
+ */
+HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ return hfmpi2c->State;
+}
+
+/**
+* @brief Return the FMPI2C error code
+* @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+* @retval FMPI2C Error Code
+*/
+uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ return hfmpi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Handle Interrupt Flags Master Transmit Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_MasterTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET)
+ {
+ if((hfmpi2c->XferSize == 0)&&(hfmpi2c->XferCount!=0))
+ {
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ if(hfmpi2c->XferCount > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferCount, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET)
+ {
+ if(hfmpi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_TX)
+ {
+ HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Master Receive Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_MasterReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET)
+ {
+ if((hfmpi2c->XferSize == 0)&&(hfmpi2c->XferCount!=0))
+ {
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ if(hfmpi2c->XferCount > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferCount, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET)
+ {
+ if(hfmpi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_RX)
+ {
+ HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Transmit Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_SlaveTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
+ {
+ /* Check that FMPI2C transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if(hfmpi2c->XferCount == 0)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+ /* Check first if STOPF is set */
+ /* to prevent a Write Data in TX buffer */
+ /* which is stuck in TXDR until next */
+ /* communication with Master */
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI );
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ if(hfmpi2c->XferCount > 0)
+ {
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Receive Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_SlaveReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_RXI );
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Mememory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DMA FMPI2C master transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C slave transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOP flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Normal Use case, a AF is generated by master */
+ /* to inform slave the end of transfer */
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief DMA FMPI2C master receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C slave receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOPF flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief DMA FMPI2C Memory Write process complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C Memory Read process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C communication error callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Flag: specifies the FMPI2C flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of TXIS flag.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if a STOPF is detected */
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Acknowledge failed detection during an FMPI2C Communication.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ {
+ /* Generate stop if necessary only in case of FMPI2C peripheral in MASTER mode */
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_TX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_RX))
+ {
+ /* No need to generate the STOP condition if AUTOEND mode is enabled */
+ /* Generate the STOP condition only in case of SOFTEND mode is enabled */
+ if((hfmpi2c->Instance->CR2 & FMPI2C_AUTOEND_MODE) != FMPI2C_AUTOEND_MODE)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ }
+
+ /* Wait until STOP Flag is reset */
+ /* AutoEnd should be initiate after AF */
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear NACKF Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hfmpi2c: FMPI2C handle.
+ * @param DevAddress: specifies the slave address to be programmed.
+ * @param Size: specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode: new state of the FMPI2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_RELOAD_MODE: Enable Reload mode .
+ * @arg FMPI2C_AUTOEND_MODE: Enable Automatic end mode.
+ * @arg FMPI2C_SOFTEND_MODE: Enable Software end mode.
+ * @param Request: new state of the FMPI2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_NO_STARTSTOP: Don't Generate stop and start condition.
+ * @arg FMPI2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
+ * @arg FMPI2C_GENERATE_START_READ: Generate Restart for read request.
+ * @arg FMPI2C_GENERATE_START_WRITE: Generate Restart for write request.
+ * @retval None
+ */
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* Get the CR2 register value */
+ tmpreg = hfmpi2c->Instance->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << 16 ) & FMPI2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
+
+ /* update CR2 register */
+ hfmpi2c->Instance->CR2 = tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,577 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Header file of FMPI2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FMPI2C_H
+#define __STM32F4xx_HAL_FMPI2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPI2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
+ * @{
+ */
+
+/**
+ * @brief FMPI2C Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value.
+ This parameter calculated by referring to FMPI2C initialization
+ section in Reference manual */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref FMPI2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref FMPI2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref FMPI2C_own_address2_masks */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref FMPI2C_general_call_addressing_mode */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref FMPI2C_nostretch_mode */
+
+}FMPI2C_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_FMPI2C_STATE_RESET = 0x00, /*!< FMPI2C not yet initialized or disabled */
+ HAL_FMPI2C_STATE_READY = 0x01, /*!< FMPI2C initialized and ready for use */
+ HAL_FMPI2C_STATE_BUSY = 0x02, /*!< FMPI2C internal process is ongoing */
+ HAL_FMPI2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
+ HAL_FMPI2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
+ HAL_FMPI2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
+ HAL_FMPI2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_FMPI2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_FMPI2C_StateTypeDef;
+
+/**
+ * @brief HAL FMPI2C Error Code structure definition
+ */
+typedef enum
+{
+ HAL_FMPI2C_ERROR_NONE = 0x00, /*!< No error */
+ HAL_FMPI2C_ERROR_BERR = 0x01, /*!< BERR error */
+ HAL_FMPI2C_ERROR_ARLO = 0x02, /*!< ARLO error */
+ HAL_FMPI2C_ERROR_AF = 0x04, /*!< ACKF error */
+ HAL_FMPI2C_ERROR_OVR = 0x08, /*!< OVR error */
+ HAL_FMPI2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
+ HAL_FMPI2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */
+ HAL_FMPI2C_ERROR_SIZE = 0x40 /*!< Size Management error */
+}HAL_FMPI2C_ErrorTypeDef;
+
+/**
+ * @brief FMPI2C handle Structure definition
+ */
+typedef struct
+{
+ FMPI2C_TypeDef *Instance; /*!< FMPI2C registers base address */
+
+ FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */
+
+ uint16_t XferSize; /*!< FMPI2C transfer size */
+
+ __IO uint16_t XferCount; /*!< FMPI2C transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< FMPI2C locking object */
+
+ __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */
+
+ __IO HAL_FMPI2C_ErrorTypeDef ErrorCode; /* FMPI2C Error code */
+
+}FMPI2C_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMPI2C_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2C_addressing_mode FMPI2C addressing mode
+ * @{
+ */
+#define FMPI2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
+#define FMPI2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_dual_addressing_mode FMPI2C dual addressing mode
+ * @{
+ */
+
+#define FMPI2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_own_address2_masks FMPI2C own address2 masks
+ * @{
+ */
+
+#define FMPI2C_OA2_NOMASK ((uint8_t)0x00)
+#define FMPI2C_OA2_MASK01 ((uint8_t)0x01)
+#define FMPI2C_OA2_MASK02 ((uint8_t)0x02)
+#define FMPI2C_OA2_MASK03 ((uint8_t)0x03)
+#define FMPI2C_OA2_MASK04 ((uint8_t)0x04)
+#define FMPI2C_OA2_MASK05 ((uint8_t)0x05)
+#define FMPI2C_OA2_MASK06 ((uint8_t)0x06)
+#define FMPI2C_OA2_MASK07 ((uint8_t)0x07)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_general_call_addressing_mode FMPI2C general call addressing mode
+ * @{
+ */
+#define FMPI2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_nostretch_mode FMPI2C nostretch mode
+ * @{
+ */
+#define FMPI2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Memory_Address_Size FMPI2C Memory Address Size
+ * @{
+ */
+#define FMPI2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
+#define FMPI2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_ReloadEndMode_definition FMPI2C ReloadEndMode definition
+ * @{
+ */
+
+#define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD
+#define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND
+#define FMPI2C_SOFTEND_MODE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_StartStopMode_definition FMPI2C StartStopMode definition
+ * @{
+ */
+
+#define FMPI2C_NO_STARTSTOP ((uint32_t)0x00000000)
+#define FMPI2C_GENERATE_STOP FMPI2C_CR2_STOP
+#define FMPI2C_GENERATE_START_READ (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define FMPI2C_GENERATE_START_WRITE FMPI2C_CR2_START
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Interrupt_configuration_definition FMPI2C Interrupt configuration definition
+ * @brief FMPI2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE
+#define FMPI2C_IT_TCI FMPI2C_CR1_TCIE
+#define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE
+#define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE
+#define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE
+#define FMPI2C_IT_RXI FMPI2C_CR1_RXIE
+#define FMPI2C_IT_TXI FMPI2C_CR1_TXIE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
+ * @{
+ */
+
+#define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
+#define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
+#define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
+#define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR
+#define FMPI2C_FLAG_AF FMPI2C_ISR_NACKF
+#define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF
+#define FMPI2C_FLAG_TC FMPI2C_ISR_TC
+#define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR
+#define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR
+#define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO
+#define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR
+#define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR
+#define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
+#define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT
+#define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY
+#define FMPI2C_FLAG_DIR FMPI2C_ISR_DIR
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMPI2C handle state
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @retval None
+ */
+#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
+
+/** @brief Enables or disables the specified FMPI2C interrupts.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_IT_ERRI: Errors interrupt enable
+ * @arg FMPI2C_IT_TCI: Transfer complete interrupt enable
+ * @arg FMPI2C_IT_STOPI: STOP detection interrupt enable
+ * @arg FMPI2C_IT_NACKI: NACK received interrupt enable
+ * @arg FMPI2C_IT_ADDRI: Address match interrupt enable
+ * @arg FMPI2C_IT_RXI: RX interrupt enable
+ * @arg FMPI2C_IT_TXI: TX interrupt enable
+ *
+ * @retval None
+ */
+
+#define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+#define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified FMPI2C interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __INTERRUPT__: specifies the FMPI2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_IT_ERRI: Errors interrupt enable
+ * @arg FMPI2C_IT_TCI: Transfer complete interrupt enable
+ * @arg FMPI2C_IT_STOPI: STOP detection interrupt enable
+ * @arg FMPI2C_IT_NACKI: NACK received interrupt enable
+ * @arg FMPI2C_IT_ADDRI: Address match interrupt enable
+ * @arg FMPI2C_IT_RXI: RX interrupt enable
+ * @arg FMPI2C_IT_TXI: TX interrupt enable
+ *
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified FMPI2C flag is set or not.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_FLAG_TXE: Transmit data register empty
+ * @arg FMPI2C_FLAG_TXIS: Transmit interrupt status
+ * @arg FMPI2C_FLAG_RXNE: Receive data register not empty
+ * @arg FMPI2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg FMPI2C_FLAG_AF: Acknowledge failure received flag
+ * @arg FMPI2C_FLAG_STOPF: STOP detection flag
+ * @arg FMPI2C_FLAG_TC: Transfer complete (master mode)
+ * @arg FMPI2C_FLAG_TCR: Transfer complete reload
+ * @arg FMPI2C_FLAG_BERR: Bus error
+ * @arg FMPI2C_FLAG_ARLO: Arbitration lost
+ * @arg FMPI2C_FLAG_OVR: Overrun/Underrun
+ * @arg FMPI2C_FLAG_PECERR: PEC error in reception
+ * @arg FMPI2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg FMPI2C_FLAG_ALERT: SMBus alert
+ * @arg FMPI2C_FLAG_BUSY: Bus busy
+ * @arg FMPI2C_FLAG_DIR: Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
+
+/** @brief Clears the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FMPI2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg FMPI2C_FLAG_AF: Acknowledge failure received flag
+ * @arg FMPI2C_FLAG_STOPF: STOP detection flag
+ * @arg FMPI2C_FLAG_BERR: Bus error
+ * @arg FMPI2C_FLAG_ARLO: Arbitration lost
+ * @arg FMPI2C_FLAG_OVR: Overrun/Underrun
+ * @arg FMPI2C_FLAG_PECERR: PEC error in reception
+ * @arg FMPI2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg FMPI2C_FLAG_ALERT: SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & FMPI2C_FLAG_MASK))
+
+
+#define __HAL_FMPI2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= FMPI2C_CR1_PE)
+#define __HAL_FMPI2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~FMPI2C_CR1_PE)
+
+#define __HAL_FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+
+#define __HAL_FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define __HAL_FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define __HAL_FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+
+#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+ * @}
+ */
+
+/* Include FMPI2C HAL Extension module */
+#include "stm32f4xx_hal_fmpi2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPI2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization/de-initialization functions**********************************/
+HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hFMPI2C);
+HAL_StatusTypeDef HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hFMPI2C);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group2
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+ /******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+ /******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral State functions ************************************************/
+HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hFMPI2C);
+uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hFMPI2C);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
+ * @{
+ */
+#define FMPI2C_FLAG_MASK ((uint32_t)0x0001FFFF)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Macros FMPI2C Private Macros
+ * @{
+ */
+
+#define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
+
+#define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
+
+#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \
+ ((MASK) == FMPI2C_OA2_MASK01) || \
+ ((MASK) == FMPI2C_OA2_MASK02) || \
+ ((MASK) == FMPI2C_OA2_MASK03) || \
+ ((MASK) == FMPI2C_OA2_MASK04) || \
+ ((MASK) == FMPI2C_OA2_MASK05) || \
+ ((MASK) == FMPI2C_OA2_MASK06) || \
+ ((MASK) == FMPI2C_OA2_MASK07))
+
+#define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
+ ((CALL) == FMPI2C_GENERALCALL_ENABLE))
+
+#define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
+
+#define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \
+ ((MODE) == FMPI2C_AUTOEND_MODE) || \
+ ((MODE) == FMPI2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPI2C_GENERATE_STOP) || \
+ ((REQUEST) == FMPI2C_GENERATE_START_READ) || \
+ ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == FMPI2C_NO_STARTSTOP))
+
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
+ * @brief FMPI2C private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_FMPI2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,326 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c_ex.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Extended FMPI2C HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
+ * + Extended Control methods
+ *
+ @verbatim
+ ==============================================================================
+ ##### FMPI2C peripheral extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the FMPI2C interface for STM32L4XX
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable wakeup from Stop mode
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMPI2CEx FMPI2CEx
+ * @brief FMPI2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
+ * @{
+ */
+
+
+/** @defgroup FMPI2CEx_Exported_Functions_Group1 Peripheral Control methods
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures FMPI2C Analog noise filter.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @param AnalogFilter : new state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_AnalogFilter_Config(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_ANALOG_FILTER(AnalogFilter));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Reset FMPI2Cx ANOFF bit */
+ hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hfmpi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures FMPI2C Digital noise filter.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_DigitalFilter_Config(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_DIGITAL_FILTER(DigitalFilter));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Get the old register value */
+ tmpreg = hfmpi2c->Instance->CR1;
+
+ /* Reset FMPI2Cx DNF bits [11:8] */
+ tmpreg &= ~(FMPI2C_CR1_DFN);
+
+ /* Set FMPI2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8;
+
+ /* Store the new register value */
+ hfmpi2c->Instance->CR1 = tmpreg;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables FMPI2C wakeup from stop mode.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Enable wakeup from stop mode */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_WUPEN;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables FMPI2C wakeup from stop mode.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Enable wakeup from stop mode */
+ hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_WUPEN);
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FMPI2C1 fast mode plus driving capability.
+ * @param ConfigFastModePlus: selects the pin.
+ * This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the FMPI2C1 fast mode plus driving capability.
+ * @param ConfigFastModePlus: selects the pin.
+ * This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,151 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c_ex.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Header file of FMPI2C HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FMPI2C_EX_H
+#define __STM32F4xx_HAL_FMPI2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPI2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMPI2CEx_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2CEx_Analog_Filter FMPI2C Analog Filter
+ * @{
+ */
+#define FMPI2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2CEx_FastModePlus FMPI2C Fast Mode Plus
+ * @{
+ */
+#define FMPI2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */
+#define FMPI2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPI2CEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMPI2CEx_Exported_Functions_Group1
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_FMPI2CEx_AnalogFilter_Config(FMPI2C_HandleTypeDef *hFMPI2C, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_FMPI2CEx_DigitalFilter_Config(FMPI2C_HandleTypeDef *hFMPI2C, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hFMPI2C);
+HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macros I2C Private Macros
+ * @{
+ */
+#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
+
+#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+
+#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
+ (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FMPI2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -15,42 +15,43 @@
##### GPIO Peripheral features #####
==============================================================================
[..]
- (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
- configured by software in several modes:
- (++) Input mode
- (++) Analog mode
- (++) Output mode
- (++) Alternate function mode
- (++) External interrupt/event lines
-
- (+) During and just after reset, the alternate functions and external interrupt
- lines are not active and the I/O ports are configured in input floating mode.
-
- (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
- activated or not.
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+ in several modes:
+ (+) Input mode
+ (+) Analog mode
+ (+) Output mode
+ (+) Alternate function mode
+ (+) External interrupt/event lines
- (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
- type and the IO speed can be selected depending on the VDD value.
+ [..]
+ During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ [..]
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
- (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
- multiplexer that allows only one peripheral alternate function (AF) connected
- to an IO pin at a time. In this way, there can be no conflict between peripherals
- sharing the same IO pin.
+ [..]
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
- (+) All ports have external interrupt/event capability. To use external interrupt
- lines, the port must be configured in input mode. All available GPIO pins are
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
- (+) The external interrupt/event controller consists of up to 23 edge detectors
- (16 lines are connected to GPIO) for generating event/interrupt requests (each
- input line can be independently configured to select the type (interrupt or event)
- and the corresponding trigger event (rising or falling or both). Each line can
- also be masked independently.
+ [..]
+ All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ [..]
+ The external interrupt/event controller consists of up to 23 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
- (#) Enable the GPIO AHB clock using the following function: __GPIOx_CLK_ENABLE().
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
@@ -74,6 +75,9 @@
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
@@ -91,7 +95,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -125,7 +129,7 @@
* @{
*/
-/** @defgroup GPIO
+/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
@@ -134,19 +138,9 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-#define GET_GPIO_SOURCE(__GPIOx__) \
-(((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? (uint32_t)0 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? (uint32_t)1 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? (uint32_t)2 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0C00)))? (uint32_t)3 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1000)))? (uint32_t)4 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1400)))? (uint32_t)5 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1800)))? (uint32_t)6 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1C00)))? (uint32_t)7 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x2000)))? (uint32_t)8 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x2400)))? (uint32_t)9 : (uint32_t)10)
-
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
#define GPIO_MODE ((uint32_t)0x00000003)
#define EXTI_MODE ((uint32_t)0x10000000)
#define GPIO_MODE_IT ((uint32_t)0x00010000)
@@ -156,26 +150,34 @@
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define GPIO_NUMBER ((uint32_t)16)
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
-/** @defgroup GPIO_Group1 Initialization and de-initialization functions
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
-
+ [..]
+ This section provides functions allowing to initialize and de-initialize the GPIOs
+ to be ready for use.
+
@endverbatim
* @{
*/
+
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
@@ -192,6 +194,7 @@
uint32_t temp = 0x00;
/* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
@@ -255,11 +258,11 @@
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable SYSCFG Clock */
- __SYSCFG_CLK_ENABLE();
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2];
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- temp |= ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
SYSCFG->EXTICR[position >> 2] = temp;
/* Clear EXTI line configuration */
@@ -315,6 +318,9 @@
uint32_t iocurrent = 0x00;
uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
{
@@ -326,7 +332,7 @@
if(iocurrent == ioposition)
{
/*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO Direction in Input Floting Mode */
+ /* Configure IO Direction in Input Floating Mode */
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
/* Configure the default Alternate Function in current IO */
@@ -338,21 +344,26 @@
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
- /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
/*------------------------- EXTI Mode Configuration --------------------*/
- /* Configure the External Interrupt or event for the current IO */
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
+ tmp = SYSCFG->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03))))
+ {
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
}
}
}
@@ -361,7 +372,7 @@
* @}
*/
-/** @defgroup GPIO_Group2 IO operation functions
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read and Write
*
@verbatim
@@ -424,11 +435,11 @@
if(PinState != GPIO_PIN_RESET)
{
- GPIOx->BSRRL = GPIO_Pin;
+ GPIOx->BSRR = GPIO_Pin;
}
else
{
- GPIOx->BSRRH = GPIO_Pin ;
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,9 +55,12 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
/**
- * @brief GPIO Init structure definition
+ * @brief GPIO Init structure definition
*/
typedef struct
{
@@ -74,7 +77,7 @@
This parameter can be a value of @ref GPIO_speed_define */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
- This parameter can be a value of @ref GPIO_Alternat_function_selection */
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */
}GPIO_InitTypeDef;
/**
@@ -85,15 +88,17 @@
GPIO_PIN_RESET = 0,
GPIO_PIN_SET
}GPIO_PinState;
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Constants
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
- */
+ */
-/** @defgroup GPIO_pins_define
+/** @defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
@@ -115,13 +120,11 @@
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
-
/**
* @}
*/
-/** @defgroup GPIO_mode_define
+/** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
@@ -146,24 +149,11 @@
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-
/**
* @}
*/
-/** @defgroup GPIO_speed_define
+
+/** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
*/
@@ -171,23 +161,17 @@
#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */
#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
- ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
/**
* @}
*/
- /** @defgroup GPIO_pull_define
+ /** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
/**
* @}
*/
@@ -197,6 +181,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
/**
* @brief Checks whether the specified EXTI line flag is set or not.
@@ -237,16 +224,32 @@
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+ * @}
+ */
/* Include GPIO HAL Extension module */
#include "stm32f4xx_hal_gpio_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
-/* IO operation functions *******************************************************/
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
@@ -261,6 +264,59 @@
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,23 +50,21 @@
* @{
*/
-/** @addtogroup GPIO
+/** @defgroup GPIOEx GPIOEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
-
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_Alternat_function_selection
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
* @{
*/
-/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+ * @{
+ */
+
+/*------------------------------------------ STM32F429xx/STM32F439xx --------------------------------------*/
#if defined (STM32F429xx) || defined (STM32F439xx)
/**
* @brief AF 0 selection
@@ -110,6 +108,7 @@
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
@@ -181,30 +180,6 @@
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
- ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
- ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
- ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
- ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
- ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
- ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
- ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
- ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
- ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
- ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
- ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
- ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
- ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
- ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
- ((AF) == GPIO_AF14_LTDC))
-
#endif /* STM32F429xx || STM32F439xx */
/*------------------------------------------------------------------------------------------*/
@@ -252,10 +227,13 @@
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
-#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+/** @brief GPIO_Legacy
+ */
+#define GPIO_AF5_I2S3ext GPIO_AF5_SPI3 /* I2S3ext_SD Alternate Function mapping */
/**
* @brief AF 6 selection
@@ -317,29 +295,6 @@
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
- ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
- ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
- ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
- ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
- ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
- ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
- ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
- ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
- ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
- ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
- ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
- ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
- ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
- ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1))
-
#endif /* STM32F427xx || STM32F437xx */
/*------------------------------------------------------------------------------------------*/
@@ -446,26 +401,6 @@
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
- ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
- ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
- ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
- ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
- ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
- ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
- ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
- ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
- ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
- ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
- ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
-
#endif /* STM32F407xx || STM32F417xx */
/*------------------------------------------------------------------------------------------*/
@@ -519,7 +454,7 @@
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
/**
* @brief AF 7 selection
@@ -562,25 +497,6 @@
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
- ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
- ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
- ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
- ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
- ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
- ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
- ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
- ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
- ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
- ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
-
#endif /* STM32F405xx || STM32F415xx */
/*------------------------------------------------------------------------------------------*/
@@ -671,21 +587,6 @@
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
- ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
- ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
- ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
- ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
- ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
- ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
-
#endif /* STM32F401xC || STM32F401xE */
/*------------------------------------------------------------------------------------------*/
@@ -779,7 +680,342 @@
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F411xE */
+/*---------------------------------------- STM32F446xx -------------------------------------------*/
+#if defined (STM32F446xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
+#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
+#define GPIO_AF10_QSPI ((uint8_t)0xA) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F446xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+ * @{
+ */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+ * @{
+ */
+#if defined (STM32F405xx) || defined (STM32F415xx) || defined (STM32F407xx) || defined (STM32F417xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U :\
+ ((__GPIOx__) == (GPIOI))? 8U : 9U)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined (STM32F427xx) || defined (STM32F437xx) || defined (STM32F429xx) || defined (STM32F439xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U :\
+ ((__GPIOx__) == (GPIOI))? 8U :\
+ ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U : 5U)
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined (STM32F446xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U : 8U)
+#endif /* STM32F446xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+ * @{
+ */
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+#if defined (STM32F429xx) || defined (STM32F439xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF14_LTDC))
+
+#endif /* STM32F429xx || STM32F439xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/
+#if defined (STM32F427xx) || defined (STM32F437xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1))
+
+#endif /* STM32F427xx || STM32F437xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/
+#if defined (STM32F407xx) || defined (STM32F417xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F407xx || STM32F417xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/
+#if defined (STM32F405xx) || defined (STM32F415xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F405xx || STM32F415xx */
+
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx--------------------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
+ ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
+ ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F401xC || STM32F401xE */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F411xx--------------------------------------*/
+#if defined(STM32F411xE)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@@ -797,6 +1033,39 @@
((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------------------------------*/
+
+/*----------------------------------------------- STM32F446xx ----------------------------------------*/
+#if defined(STM32F446xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \
+ ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \
+ ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \
+ ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F446xx */
+
/**
* @}
*/
@@ -805,9 +1074,14 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -20,7 +20,7 @@
[..]
The HASH HAL driver can be used as follows:
(#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
(##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
(+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
@@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,7 @@
* @{
*/
-/** @defgroup HASH
+/** @defgroup HASH HASH
* @brief HASH HAL module driver.
* @{
*/
@@ -116,1526 +116,23 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASH_DMAError(DMA_HandleTypeDef *hdma);
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the HASH according to the specified parameters
- in the HASH_InitTypeDef and creates the associated handle.
- (+) DeInitialize the HASH peripheral.
- (+) Initialize the HASH MSP.
- (+) DeInitialize HASH MSP.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH according to the specified parameters in the
- HASH_HandleTypeDef and creates the associated handle.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
-{
- /* Check the hash handle allocation */
- if(hhash == HAL_NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
-
- if(hhash->State == HAL_HASH_STATE_RESET)
- {
- /* Init the low level hardware */
- HAL_HASH_MspInit(hhash);
- }
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Reset HashInCount, HashBuffSize and HashITCounter */
- hhash->HashInCount = 0;
- hhash->HashBuffSize = 0;
- hhash->HashITCounter = 0;
-
- /* Set the data type */
- HASH->CR |= (uint32_t) (hhash->Init.DataType);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Set the default HASH phase */
- hhash->Phase = HAL_HASH_PHASE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the HASH peripheral.
- * @note This API must be called before starting a new processing.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
-{
- /* Check the HASH handle allocation */
- if(hhash == HAL_NULL)
- {
- return HAL_ERROR;
- }
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Set the default HASH phase */
- hhash->Phase = HAL_HASH_PHASE_READY;
-
- /* Reset HashInCount, HashBuffSize and HashITCounter */
- hhash->HashInCount = 0;
- hhash->HashBuffSize = 0;
- hhash->HashITCounter = 0;
-
- /* DeInit the low level hardware */
- HAL_HASH_MspDeInit(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH MSP.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
-__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
-{
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes HASH MSP.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
-__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
-{
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Input data transfer complete callback.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
- __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
-{
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_InCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Data transfer Error callback.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
- __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
-{
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Digest computation complete callback. It is used only with interrupt.
- * @note This callback is not relevant with DMA.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
- __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
-{
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_DgstCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Group2 HASH processing functions using polling mode
- * @brief processing functions using polling mode
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using polling mode functions#####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is multiple of 64 bytes, appending the input buffer is possible.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware
- * and appending the input buffer is no more possible.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is multiple of 64 bytes, appending the input buffer is possible.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware
- * and appending the input buffer is no more possible.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA1 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA1 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
/**
* @}
*/
-
-/** @defgroup HASH_Group3 HASH processing functions using interrupt mode
- * @brief processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using interrupt mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA1 mode */
- HASH->CR |= HASH_AlgoSelection_MD5;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
-
- if(hhash->HashInCount == 0)
- {
- /* Disable Interrupts */
- HASH->IMR = 0;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount > 64)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
-
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount -= 64;
- }
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
-
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- }
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA1 mode */
- HASH->CR |= HASH_AlgoSelection_SHA1;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
- if(hhash->HashInCount == 0)
- {
- /* Disable Interrupts */
- HASH->IMR = 0;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount > 64)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
-
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount -= 64;
- }
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
-
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- }
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief This function handles HASH interrupt request.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
-{
- switch(HASH->CR & HASH_CR_ALGO)
- {
- case HASH_AlgoSelection_MD5:
- HAL_HASH_MD5_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
- break;
-
- case HASH_AlgoSelection_SHA1:
- HAL_HASH_SHA1_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Group4 HASH processing functions using DMA mode
- * @brief processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using DMA mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup HASH_Private_Functions
* @{
*/
/**
- * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
- control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Returns the computed digest in MD5 mode
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA1;
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Returns the computed digest in SHA1 mode.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process UnLock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Group5 HASH-MAC (HMAC) processing functions using polling mode
- * @brief HMAC processing functions using polling mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using polling mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in HMAC MD5 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in HMAC SHA1 mode
- * then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Group6 HASH-MAC (HMAC) processing functions using DMA mode
- * @brief HMAC processing functions using DMA mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using DMA mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in HMAC MD5 mode
- * then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in HMAC SHA1 mode
- * then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Group7 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the HASH state
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval HAL state
- */
-HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
-{
- return hhash->State;
-}
-
-/**
- * @}
- */
-
-/**
* @brief DMA HASH Input Data complete callback.
* @param hdma: DMA handle
* @retval None
@@ -1813,6 +310,1526 @@
/**
* @}
*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HASH_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the HASH according to the specified parameters
+ in the HASH_InitTypeDef and creates the associated handle.
+ (+) DeInitialize the HASH peripheral.
+ (+) Initialize the HASH MSP.
+ (+) DeInitialize HASH MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH according to the specified parameters in the
+ HASH_HandleTypeDef and creates the associated handle.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
+{
+ /* Check the hash handle allocation */
+ if(hhash == HAL_NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+
+ if(hhash->State == HAL_HASH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_HASH_MspInit(hhash);
+ }
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Reset HashInCount, HashBuffSize and HashITCounter */
+ hhash->HashInCount = 0;
+ hhash->HashBuffSize = 0;
+ hhash->HashITCounter = 0;
+
+ /* Set the data type */
+ HASH->CR |= (uint32_t) (hhash->Init.DataType);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Set the default HASH phase */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the HASH peripheral.
+ * @note This API must be called before starting a new processing.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
+{
+ /* Check the HASH handle allocation */
+ if(hhash == HAL_NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Set the default HASH phase */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
+ /* Reset HashInCount, HashBuffSize and HashITCounter */
+ hhash->HashInCount = 0;
+ hhash->HashBuffSize = 0;
+ hhash->HashITCounter = 0;
+
+ /* DeInit the low level hardware */
+ HAL_HASH_MspDeInit(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH MSP.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes HASH MSP.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input data transfer complete callback.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_InCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data transfer Error callback.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Digest computation complete callback. It is used only with interrupt.
+ * @note This callback is not relevant with DMA.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_DgstCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
+ * @brief processing functions using polling mode
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using polling mode functions#####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware
+ * and appending the input buffer is no more possible.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 16);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware
+ * and appending the input buffer is no more possible.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 20);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
+ * @brief processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using interrupt mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->HashITCounter == 0)
+ {
+ hhash->HashITCounter = 1;
+ }
+ else
+ {
+ hhash->HashITCounter = 0;
+ }
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode */
+ HASH->CR |= HASH_ALGOSELECTION_MD5;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
+
+ if(hhash->HashInCount == 0)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount > 64)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ if(hhash->HashITCounter == 0)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ if(hhash->HashInCount >= 68)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68;
+ hhash->pHashInBuffPtr+= 68;
+ }
+ else
+ {
+ hhash->HashInCount -= 64;
+ }
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64;
+ hhash->pHashInBuffPtr+= 64;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4) && (inputcounter%4))
+ {
+ inputcounter = (inputcounter+4-inputcounter%4);
+ }
+
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0;
+ }
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->HashITCounter == 0)
+ {
+ hhash->HashITCounter = 1;
+ }
+ else
+ {
+ hhash->HashITCounter = 0;
+ }
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
+ if(hhash->HashInCount == 0)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount > 64)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ if(hhash->HashITCounter == 0)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ if(hhash->HashInCount >= 68)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68;
+ hhash->pHashInBuffPtr+= 68;
+ }
+ else
+ {
+ hhash->HashInCount -= 64;
+ }
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64;
+ hhash->pHashInBuffPtr+= 64;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4) && (inputcounter%4))
+ {
+ inputcounter = (inputcounter+4-inputcounter%4);
+ }
+
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0;
+ }
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles HASH interrupt request.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+ switch(HASH->CR & HASH_CR_ALGO)
+ {
+ case HASH_ALGOSELECTION_MD5:
+ HAL_HASH_MD5_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
+ break;
+
+ case HASH_ALGOSELECTION_SHA1:
+ HAL_HASH_SHA1_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
+ * @brief processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using DMA mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
+ control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in MD5 mode
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 16);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
+ control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in SHA1 mode.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 20);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
+ * @brief HMAC processing functions using polling mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using polling mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 16);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 20);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
+ * @brief HMAC processing functions using DMA mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using DMA mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode
+ * then enables DMA to control data transfer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode
+ * then enables DMA to control data transfer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the HASH state
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval HAL state
+ */
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+ return hhash->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
#endif /* HAL_HASH_MODULE_ENABLED */
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_hash.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,19 +52,24 @@
* @{
*/
-/** @addtogroup HASH
- * @{
+/** @addtogroup HASH
+ * @brief HASH HAL module driver
+ * @{
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Types HASH Exported Types
+ * @{
+ */
-/**
- * @brief HASH Configuration Structure definition
+/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
+ * @{
*/
+
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref HASH_Data_Type */
+ This parameter can be a value of @ref HASH DataType */
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
@@ -72,8 +77,13 @@
}HASH_InitTypeDef;
/**
- * @brief HAL State structures definition
- */
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
+ * @{
+ */
+
typedef enum
{
HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */
@@ -84,8 +94,13 @@
}HAL_HASH_STATETypeDef;
/**
- * @brief HAL phase structures definition
+ * @}
*/
+
+/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
+ * @{
+ */
+
typedef enum
{
HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */
@@ -93,8 +108,13 @@
}HAL_HASHPhaseTypeDef;
/**
- * @brief HASH Handle Structure definition
+ * @}
*/
+
+/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
+ * @{
+ */
+
typedef struct
{
HASH_InitTypeDef Init; /*!< HASH required parameters */
@@ -120,69 +140,62 @@
__IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */
} HASH_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
+
-/** @defgroup HASH_Exported_Constants
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HASH_Exported_Constants HASH Exported Constants
* @{
*/
-/** @defgroup HASH_Algo_Selection
+/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
* @{
*/
-#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
-#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
-#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
-#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
-
-#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
+#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
/**
* @}
*/
-/** @defgroup HASH_Algorithm_Mode
+/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
* @{
- */
-#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
-#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
-
-#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
- ((ALGOMODE) == HASH_AlgoMode_HMAC))
+ */
+#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
*/
-/** @defgroup HASH_Data_Type
+/** @defgroup HASH_Exported_Constants_Group3 HASH DataType
* @{
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
-
-#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DATATYPE_32B)|| \
- ((DATATYPE) == HASH_DATATYPE_16B)|| \
- ((DATATYPE) == HASH_DATATYPE_8B) || \
- ((DATATYPE) == HASH_DATATYPE_1B))
/**
* @}
*/
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
+/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
+ * @brief HASH HMAC Long key used only for HMAC mode
* @{
- */
-#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
-
-#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
- ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+ */
+#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
/**
* @}
*/
-/** @defgroup HASH_flags_definition
+/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
* @{
*/
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
@@ -194,9 +207,9 @@
* @}
*/
-/** @defgroup HASH_interrupts_definition
+/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
* @{
- */
+ */
#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
/**
@@ -208,7 +221,10 @@
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup HASH_Exported_Macros HASH Exported Macros
+ * @{
+ */
+
/** @brief Reset HASH handle state
* @param __HANDLE__: specifies the HASH handle.
* @retval None
@@ -228,33 +244,20 @@
#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
/**
- * @brief Macros for HMAC finish.
- * @param None
- * @retval None
- */
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
-
-/**
* @brief Enable the multiple DMA mode.
* This feature is available only in STM32F429x and STM32F439x devices.
- * @param None
* @retval None
*/
#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
/**
* @brief Disable the multiple DMA mode.
- * @param None
* @retval None
*/
#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
/**
* @brief Start the digest computation
- * @param None
* @retval None
*/
#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
@@ -268,50 +271,164 @@
HASH->STR |= 8 * ((SIZE) % 4);\
}while(0)
+/**
+ * @}
+ */
+
/* Include HASH HAL Extension module */
#include "stm32f4xx_hal_hash_ex.h"
-
/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions **********************************/
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
+ * @{
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
-/* HASH processing using polling *********************************************/
+/** @addtogroup HASH_Exported_Functions_Group2
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/* HASH-MAC processing using polling *****************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group3
+ * @{
+ */
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+ * @}
+ */
-/* HASH processing using interrupt *******************************************/
+/** @addtogroup HASH_Exported_Functions_Group4
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+/**
+ * @}
+ */
-/* HASH processing using DMA *************************************************/
+/** @addtogroup HASH_Exported_Functions_Group5
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+ * @}
+ */
-/* HASH-HMAC processing using DMA ********************************************/
+/** @addtogroup HASH_Exported_Functions_Group6
+ * @{
+ */
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+/**
+ * @}
+ */
-/* Processing functions ******************************************************/
+/** @addtogroup HASH_Exported_Functions_Group7
+ * @{
+ */
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
-/* Peripheral State functions ************************************************/
+/** @addtogroup HASH_Exported_Functions_Group8
+ * @{
+ */
HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup HASH_Private_Types HASH Private Types
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Variables HASH Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Constants HASH Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros HASH Private Macros
+ * @{
+ */
+#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
+
+
+#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
+ ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
+
+
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+ ((__DATATYPE__) == HASH_DATATYPE_1B))
+
+
+#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
+ ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@@ -17,7 +17,7 @@
[..]
The HASH HAL driver can be used as follows:
(#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
(##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
(+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -99,7 +99,7 @@
* @{
*/
-/** @defgroup HASHEx
+/** @defgroup HASHEx HASHEx
* @brief HASH Extension HAL module driver.
* @{
*/
@@ -113,1310 +113,24 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup HASHEx_Private_Functions
+ * @{
+ */
static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASHEx_Private_Functions
- * @{
- */
-
-/** @defgroup HASHEx_Group1 HASH processing functions
- * @brief processing functions using polling mode
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using polling mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the hash value using one of the following algorithms:
- (+) SHA224
- (+) SHA256
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA224 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA256 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Initializes the HASH peripheral in SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA224 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA256 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
- * @brief HMAC processing functions using polling mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using polling mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the HMAC value using one of the following algorithms:
- (+) SHA224
- (+) SHA256
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in HMAC SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in HMAC SHA256 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey);
- }
- else
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC);
- }
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
/**
* @}
*/
-
-/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
- * @brief processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using interrupt functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
- (+) SHA224
- (+) SHA256
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- uint32_t inputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode */
- HASH->CR |= HASH_AlgoSelection_SHA224;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- /* Read the message digest */
- HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);
- if(hhash->HashInCount == 0)
- {
- /* Disable Interrupts */
- HASH->IMR = 0;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount > 64)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount -= 64;
- }
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
-
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- }
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- uint32_t inputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode */
- HASH->CR |= HASH_AlgoSelection_SHA256;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- /* Read the message digest */
- HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);
- if(hhash->HashInCount == 0)
- {
- /* Disable Interrupts */
- HASH->IMR = 0;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount > 64)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
-
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount -= 64;
- }
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
-
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- }
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief This function handles HASH interrupt request.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
-void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
-{
- switch(HASH->CR & HASH_CR_ALGO)
- {
-
- case HASH_AlgoSelection_SHA224:
- HAL_HASHEx_SHA224_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
- break;
-
- case HASH_AlgoSelection_SHA256:
- HAL_HASHEx_SHA256_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
- * @brief processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using DMA functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
- (+) SHA224
- (+) SHA256
-
-@endverbatim
- * @{
- */
-
+/* Private functions ---------------------------------------------------------*/
-/**
- * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA224 | HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Returns the computed digest in SHA224
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA256 | HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process UnLock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Returns the computed digest in SHA256.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
- * @brief HMAC processing functions using DMA mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using DMA functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) SHA224
- (+) SHA256
-
-@endverbatim
+/** @addtogroup HASHEx_Private_Functions
* @{
*/
/**
- * @brief Initializes the HASH peripheral in HMAC SHA224 mode
- * then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HASH peripheral in HMAC SHA256 mode
- * then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t inputaddr;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey);
- }
- else
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC);
- }
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
* @brief Writes the input buffer in data register.
* @param pInBuffer: Pointer to input buffer
* @param Size: The size of input buffer
@@ -1591,6 +305,1308 @@
HAL_HASH_ErrorCallback(hhash);
}
+ /**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HASHEx_Exported_Functions
+ * @{
+ */
+
+/** @defgroup HASHEx_Group1 HASH processing functions
+ * @brief processing functions using polling mode
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using polling mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 28);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 32);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
+ * @brief HMAC processing functions using polling mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using polling mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 28);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
+ }
+ else
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
+ }
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 32);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
+ * @brief processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using interrupt functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->HashITCounter == 0)
+ {
+ hhash->HashITCounter = 1;
+ }
+ else
+ {
+ hhash->HashITCounter = 0;
+ }
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ /* Read the message digest */
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);
+ if(hhash->HashInCount == 0)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount > 64)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ if(hhash->HashITCounter == 0)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ if(hhash->HashInCount >= 68)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68;
+ hhash->pHashInBuffPtr+= 68;
+ }
+ else
+ {
+ hhash->HashInCount -= 64;
+ }
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64;
+ hhash->pHashInBuffPtr+= 64;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4) && (inputcounter%4))
+ {
+ inputcounter = (inputcounter+4-inputcounter%4);
+ }
+
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0;
+ }
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->HashITCounter == 0)
+ {
+ hhash->HashITCounter = 1;
+ }
+ else
+ {
+ hhash->HashITCounter = 0;
+ }
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ /* Read the message digest */
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);
+ if(hhash->HashInCount == 0)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount > 64)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ if(hhash->HashITCounter == 0)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ if(hhash->HashInCount >= 68)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68;
+ hhash->pHashInBuffPtr+= 68;
+ }
+ else
+ {
+ hhash->HashInCount -= 64;
+ }
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64;
+ hhash->pHashInBuffPtr+= 64;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4) && (inputcounter%4))
+ {
+ inputcounter = (inputcounter+4-inputcounter%4);
+ }
+
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0;
+ }
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles HASH interrupt request.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+ switch(HASH->CR & HASH_CR_ALGO)
+ {
+
+ case HASH_ALGOSELECTION_SHA224:
+ HAL_HASHEx_SHA224_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
+ break;
+
+ case HASH_ALGOSELECTION_SHA256:
+ HAL_HASHEx_SHA256_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
+ * @brief processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using DMA functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
+ control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in SHA224
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 28);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
+ control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in SHA256.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 32);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
+ * @brief HMAC processing functions using DMA mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using DMA functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode
+ * then enables DMA to control data transfer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode
+ * then enables DMA to control data transfer.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param Size: Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64)
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
+ }
+ else
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
+ }
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -51,8 +51,9 @@
* @{
*/
-/** @addtogroup HASHEx
- * @{
+/** @addtogroup HASHEx
+ * @brief HASHEx HAL Extension module driver
+ * @{
*/
/* Exported types ------------------------------------------------------------*/
@@ -60,33 +61,127 @@
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/* HASH processing using polling *********************************************/
+/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions
+ * @{
+ */
+
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-/* HASH-MAC processing using polling *****************************************/
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions
+ * @{
+ */
+
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-/* HASH processing using interrupt *******************************************/
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using functions
+ * @{
+ */
+
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-/* HASH processing using DMA *************************************************/
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA
+ * @{
+ */
+
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-/* HASH-HMAC processing using DMA ********************************************/
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA
+ * @{
+ */
+
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/* Processing functions ******************************************************/
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions
+ * @{
+ */
+
void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Types HASHEx Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Variables HASHEx Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Constants HASHEx Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Macros HASHEx Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Functions HASHEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F437xx || STM32F439xx */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -43,7 +43,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -72,12 +72,12 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @defgroup HCD
- * @brief HCD HAL module driver
+/** @addtogroup HCD
* @{
*/
@@ -87,21 +87,27 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup HCD_Private_Functions
+ * @{
+ */
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup HCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions
* @{
*/
-/** @defgroup HCD_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @addtogroup HCD_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@@ -126,27 +132,27 @@
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
-
+
hhcd->State = HAL_HCD_STATE_BUSY;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd);
-
+
/* Disable the Interrupts */
- __HAL_HCD_DISABLE(hhcd);
-
- /*Init the Core (common init.) */
- USB_CoreInit(hhcd->Instance, hhcd->Init);
-
- /* Force Host Mode*/
- USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
-
- /* Init Host */
- USB_HostInit(hhcd->Instance, hhcd->Init);
-
- hhcd->State= HAL_HCD_STATE_READY;
-
- return HAL_OK;
+ __HAL_HCD_DISABLE(hhcd);
+
+ /* Init the Core (common init.) */
+ USB_CoreInit(hhcd->Instance, hhcd->Init);
+
+ /* Force Host Mode*/
+ USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
+
+ /* Init Host */
+ USB_HostInit(hhcd->Instance, hhcd->Init);
+
+ hhcd->State= HAL_HCD_STATE_READY;
+
+ return HAL_OK;
}
/**
@@ -166,7 +172,7 @@
* @param ep_type: Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type,
- * EP_TYPE_ISOC: Isochrounous type,
+ * EP_TYPE_ISOC: Isochronous type,
* EP_TYPE_BULK: Bulk type,
* EP_TYPE_INTR: Interrupt type
* @param mps: Max Packet Size.
@@ -192,7 +198,7 @@
hhcd->hc[ch_num].ep_num = epnum & 0x7F;
hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
hhcd->hc[ch_num].speed = speed;
-
+
status = USB_HC_Init(hhcd->Instance,
ch_num,
epnum,
@@ -205,8 +211,6 @@
return status;
}
-
-
/**
* @brief Halt a host channel
* @param hhcd: HCD handle
@@ -214,8 +218,7 @@
* This parameter can be a value from 1 to 15
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num)
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -225,6 +228,7 @@
return status;
}
+
/**
* @brief DeInitialize the host driver
* @param hhcd: HCD handle
@@ -243,7 +247,7 @@
/* DeInit the low level hardware */
HAL_HCD_MspDeInit(hhcd);
- __HAL_HCD_DISABLE(hhcd);
+ __HAL_HCD_DISABLE(hhcd);
hhcd->State = HAL_HCD_STATE_RESET;
@@ -258,7 +262,7 @@
__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implenetd in the user file
+ the HAL_PCD_MspInit could be implemented in the user file
*/
}
@@ -267,10 +271,10 @@
* @param hhcd: HCD handle
* @retval None
*/
-__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhhcd)
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implenetd in the user file
+ the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
@@ -278,7 +282,7 @@
* @}
*/
-/** @defgroup HCD_Group2 IO operation functions
+/** @addtogroup HCD_Exported_Functions_Group2
* @brief HCD IO operation functions
*
@verbatim
@@ -303,7 +307,7 @@
* @param ep_type: Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type/
- * EP_TYPE_ISOC: Isochrounous type/
+ * EP_TYPE_ISOC: Isochronous type/
* EP_TYPE_BULK: Bulk type/
* EP_TYPE_INTR: Interrupt type/
* @param token: Endpoint Type.
@@ -317,13 +321,13 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping)
+ uint8_t ch_num,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping)
{
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
@@ -355,7 +359,7 @@
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
{
@@ -374,7 +378,7 @@
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
{
@@ -404,7 +408,7 @@
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
@@ -422,14 +426,13 @@
case EP_TYPE_ISOC:
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- break;
-
+ break;
}
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
hhcd->hc[ch_num].urb_state = URB_IDLE;
- hhcd->hc[ch_num].xfer_count = 0 ;
+ hhcd->hc[ch_num].xfer_count = 0;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
@@ -446,10 +449,10 @@
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t i = 0 , interrupt = 0;
- /* ensure that we are in device mode */
+ /* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
- /* avoid spurious interrupt */
+ /* Avoid spurious interrupt */
if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
@@ -457,25 +460,25 @@
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
}
-
+
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
}
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
}
@@ -486,10 +489,10 @@
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
+
/* Handle Host Port Interrupts */
HAL_HCD_Disconnect_Callback(hhcd);
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
}
@@ -505,19 +508,18 @@
HAL_HCD_SOF_Callback(hhcd);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
-
+
/* Handle Host channel Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
-
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
- for (i = 0; i < hhcd->Init.Host_channels ; i++)
+ for (i = 0; i < hhcd->Init.Host_channels; i++)
{
if (interrupt & (1 << i))
{
if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)
{
- HCD_HC_IN_IRQHandler (hhcd, i);
+ HCD_HC_IN_IRQHandler(hhcd, i);
}
else
{
@@ -528,7 +530,7 @@
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
}
- /* Handle Rx Queue Level Interrupts */
+ /* Handle Rx Queue Level Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
@@ -537,7 +539,6 @@
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
-
}
}
@@ -549,7 +550,7 @@
__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_SOF_Callback could be implenetd in the user file
+ the HAL_HCD_SOF_Callback could be implemented in the user file
*/
}
@@ -561,19 +562,19 @@
__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Connect_Callback could be implenetd in the user file
+ the HAL_HCD_Connect_Callback could be implemented in the user file
*/
}
/**
- * @brief Disonnexion Event callback.
+ * @brief Disconnexion Event callback.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Disconnect_Callback could be implenetd in the user file
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
@@ -595,7 +596,7 @@
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_HC_NotifyURBChange_Callback could be implenetd in the user file
+ the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/
}
@@ -603,10 +604,10 @@
* @}
*/
-/** @defgroup HCD_Group3 Peripheral Control functions
- * @brief management functions
+/** @addtogroup HCD_Exported_Functions_Group3
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
@@ -660,10 +661,10 @@
* @}
*/
-/** @defgroup HCD_Group4 Peripheral State functions
+/** @addtogroup HCD_Exported_Functions_Group4
* @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
@@ -697,7 +698,7 @@
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
- * URB_STALL
+ * URB_STALL/
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -758,22 +759,28 @@
{
return (USB_GetHostSpeed(hhcd->Instance));
}
-
/**
* @}
*/
/**
+ * @}
+ */
+
+/** @addtogroup HCD_Private_Functions
+ * @{
+ */
+/**
* @brief This function handles Host Channel IN interrupt requests.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
- * @retval none
+ * @retval None
*/
-static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
-
+
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
@@ -814,7 +821,7 @@
if (hhcd->Init.dma_enable)
{
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
- (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+ (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
hhcd->hc[chnum].state = HC_XFRC;
@@ -877,10 +884,10 @@
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].ErrCnt++;
- hhcd->hc[chnum].state = HC_XACTERR;
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ hhcd->hc[chnum].ErrCnt++;
+ hhcd->hc[chnum].state = HC_XACTERR;
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
{
@@ -895,10 +902,10 @@
/* re-activate the channel */
USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-
+
}
hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
}
@@ -907,7 +914,7 @@
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
- * @retval none
+ * @retval None
*/
static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -1047,21 +1054,21 @@
/**
* @brief This function handles Rx Queue Level interrupt requests.
* @param hhcd: HCD handle
- * @retval none
+ * @retval None
*/
-static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint8_t channelnum =0;
- uint32_t pktsts;
- uint32_t pktcnt;
- uint32_t temp = 0;
+ uint8_t channelnum = 0;
+ uint32_t pktsts;
+ uint32_t pktcnt;
+ uint32_t temp = 0;
- temp = hhcd->Instance->GRXSTSP ;
+ temp = hhcd->Instance->GRXSTSP;
channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-
+
switch (pktsts)
{
case GRXSTS_PKTSTS_IN:
@@ -1070,11 +1077,11 @@
{
USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
-
+
/*manage multiple Xfer */
hhcd->hc[channelnum].xfer_buff += pktcnt;
hhcd->hc[channelnum].xfer_count += pktcnt;
-
+
if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
{
/* re-activate the channel when more packets are expected */
@@ -1084,7 +1091,7 @@
}
}
break;
-
+
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
break;
case GRXSTS_PKTSTS_IN_XFER_COMP:
@@ -1111,7 +1118,7 @@
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
- /* Check wether Port Connect Detected */
+ /* Check whether Port Connect Detected */
if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
{
if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
@@ -1165,7 +1172,7 @@
}
}
- /* Check For an overcurrent */
+ /* Check for an overcurrent */
if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,15 +50,19 @@
* @{
*/
-/** @addtogroup HCD
+/** @defgroup HCD HCD
+ * @brief HCD HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+ * @{
+ */
- /**
- * @brief HCD Status structures structure definition
- */
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+ * @{
+ */
typedef enum
{
HAL_HCD_STATE_RESET = 0x00,
@@ -73,9 +77,12 @@
typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
+/**
+ * @}
+ */
-/**
- * @brief HCD Handle Structure definition
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+ * @{
*/
typedef struct
{
@@ -84,42 +91,31 @@
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
- void *pData; /*!< Pointer Stack Handler */
-
+ void *pData; /*!< Pointer Stack Handler */
} HCD_HandleTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Constants
- * @{
- */
-
-/** @defgroup HCD_Instance_definition
- * @{
- */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
- #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
- ((INSTANCE) == USB_OTG_HS))
-#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
- #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-#endif
-
/**
* @}
*/
-/** @defgroup HCD_Speed
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+ * @{
+ */
+/** @defgroup HCD_Speed HCD Speed
* @{
*/
#define HCD_SPEED_HIGH 0
#define HCD_SPEED_LOW 2
#define HCD_SPEED_FULL 3
-
/**
* @}
*/
-
- /** @defgroup HCD_PHY_Module
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
* @{
*/
#define HCD_PHY_ULPI 1
@@ -127,94 +123,156 @@
/**
* @}
*/
+
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup HCD_Interrupt_Clock
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
-#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
+#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
-
-
+
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
-
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num);
+/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t pipe,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+/* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t pipe,
- uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping);
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
- /* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+ * @{
+ */
+/** @defgroup HCD_Instance_definition HCD Instance definition
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) ||\
+ defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
-/* Peripheral State functions **************************************************/
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
*/
-/**
- * @}
- */
-
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -35,7 +35,7 @@
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream
- (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
the DMA Tx or Rx Stream
@@ -43,7 +43,7 @@
Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
@@ -153,7 +153,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -187,7 +187,7 @@
* @{
*/
-/** @defgroup I2C
+/** @defgroup I2C I2C
* @brief I2C HAL module driver
* @{
*/
@@ -196,12 +196,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Constants
+ * @{
+ */
#define I2C_TIMEOUT_FLAG ((uint32_t)35) /* 35 ms */
#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /* 10 s */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
@@ -229,14 +238,16 @@
static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
* @{
*/
-/** @defgroup I2C_Group1 Initialization and de-initialization functions
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -244,7 +255,7 @@
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Cx peripheral:
+ de-initialize the I2Cx peripheral:
(+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
@@ -261,7 +272,7 @@
(++) Nostretch mode
(+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx periperal.
+ of the selected I2Cx peripheral.
@endverbatim
* @{
@@ -298,20 +309,22 @@
if(hi2c->State == HAL_I2C_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
}
hi2c->State = HAL_I2C_STATE_BUSY;
- /* Disble the selected I2C peripheral */
+ /* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
/* Calculate frequency range */
- freqrange = __HAL_I2C_FREQRANGE(pclk1);
+ freqrange = I2C_FREQRANGE(pclk1);
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
@@ -319,11 +332,11 @@
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
- hi2c->Instance->TRISE = __HAL_I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
+ hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
- hi2c->Instance->CCR = __HAL_I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
+ hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
@@ -411,7 +424,7 @@
* @}
*/
-/** @defgroup I2C_Group2 IO operation functions
+/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -1266,7 +1279,7 @@
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
/* Set the DMA error callback */
@@ -1342,7 +1355,7 @@
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
/* Set the DMA error callback */
@@ -1428,7 +1441,7 @@
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
/* Set the DMA error callback */
@@ -1513,7 +1526,7 @@
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
/* Set the DMA error callback */
@@ -2054,7 +2067,7 @@
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
/* Set the DMA error callback */
@@ -2132,7 +2145,7 @@
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
/* Set the DMA error callback */
@@ -2225,7 +2238,7 @@
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR or AF flag are set */
/* Get tick */
@@ -2469,6 +2482,9 @@
{
hi2c->State = HAL_I2C_STATE_READY;
+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
HAL_I2C_ErrorCallback(hi2c);
}
}
@@ -2567,7 +2583,7 @@
* @}
*/
-/** @defgroup I2C_Group3 Peripheral State and Errors functions
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -2710,6 +2726,9 @@
return HAL_TIMEOUT;
}
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -2765,6 +2784,9 @@
return HAL_TIMEOUT;
}
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -2932,6 +2954,7 @@
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
@@ -2948,12 +2971,12 @@
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
}
else
{
/* Send header of slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
@@ -2969,7 +2992,7 @@
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_ADDRESS(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
}
/* Wait until ADDR flag is set */
@@ -2993,6 +3016,7 @@
* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @param DevAddress: Target device address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
@@ -3012,12 +3036,12 @@
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_READ(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
}
else
{
/* Send header of slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
@@ -3033,7 +3057,7 @@
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_ADDRESS(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
@@ -3061,7 +3085,7 @@
}
/* Send header of slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_READ(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
}
/* Wait until ADDR flag is set */
@@ -3087,6 +3111,7 @@
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
@@ -3101,7 +3126,7 @@
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
@@ -3129,13 +3154,13 @@
if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
@@ -3144,7 +3169,7 @@
}
/* Send LSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
return HAL_OK;
@@ -3157,6 +3182,7 @@
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
@@ -3174,7 +3200,7 @@
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
@@ -3202,13 +3228,13 @@
if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
@@ -3217,7 +3243,7 @@
}
/* Send LSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TXE flag is set */
@@ -3236,7 +3262,7 @@
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_READ(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
/**
* @brief I2C Configuration Structure definition
*/
@@ -105,21 +108,6 @@
}HAL_I2C_StateTypeDef;
/**
- * @brief HAL I2C Error Code structure definition
- */
-typedef enum
-{
- HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
- HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
- HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
- HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
- HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
- HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */
-
-}HAL_I2C_ErrorTypeDef;
-
-/**
* @brief I2C handle Structure definition
*/
typedef struct
@@ -142,89 +130,88 @@
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
- __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
}I2C_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
-/** @defgroup I2C_duty_cycle_in_fast_mode
+/** @defgroup I2C_Error_Code I2C Error Code
+ * @brief I2C Error Code
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout Error */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
*/
#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
-
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
- ((CYCLE) == I2C_DUTYCYCLE_16_9))
-/**
- * @}
- */
-
-/** @defgroup I2C_addressing_mode
- * @{
- */
-#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
-#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
-
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
- ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
/**
* @}
*/
-/** @defgroup I2C_dual_addressing_mode
+/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
-#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
-#define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
/**
* @}
*/
-/** @defgroup I2C_general_call_addressing_mode
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
-#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
-#define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
- ((CALL) == I2C_GENERALCALL_ENABLED))
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
/**
* @}
*/
-/** @defgroup I2C_nostretch_mode
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
-#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
-#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLED))
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
/**
* @}
*/
-/** @defgroup I2C_Memory_Address_Size
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
/**
* @}
*/
-/** @defgroup I2C_Interrupt_configuration_definition
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @{
*/
#define I2C_IT_BUF I2C_CR2_ITBUFEN
@@ -234,7 +221,7 @@
* @}
*/
-/** @defgroup I2C_Flag_definition
+/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
@@ -267,6 +254,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
/** @brief Reset I2C handle state
* @param __HANDLE__: specifies the I2C Handle.
@@ -285,7 +275,6 @@
* @arg I2C_IT_ERR: Error interrupt enable
* @retval None
*/
-
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
@@ -330,7 +319,6 @@
* @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
@@ -355,53 +343,57 @@
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
- (__HANDLE__)->Instance->SR2;}while(0)
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ tmpreg = (__HANDLE__)->Instance->SR2; \
+ UNUSED(tmpreg); \
+ } while(0)
/** @brief Clears the I2C STOPF pending flag.
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
- (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;}while(0)
-
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
+ UNUSED(tmpreg); \
+ } while(0)
+
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
-#define __HAL_I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
-#define __HAL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
-#define __HAL_I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
-#define __HAL_I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
-#define __HAL_I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (__HAL_I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
- ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
- ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define __HAL_I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
-#define __HAL_I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define __HAL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define __HAL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define __HAL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-
-#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+/**
+ * @}
+ */
/* Include I2C HAL Extension module */
#include "stm32f4xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+/** @addtogroup I2C_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -438,10 +430,92 @@
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+/** @addtogroup I2C_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control and State functions **************************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+ * @{
+ */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+ ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief I2C Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C extension peripheral:
@@ -30,7 +30,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -64,28 +64,27 @@
* @{
*/
-/** @defgroup I2CEx
+/** @defgroup I2CEx I2CEx
* @brief I2C HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2CEx_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Functions I2C Exported Functions
* @{
*/
-/** @defgroup I2CEx_Group1 Extension features functions
+/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions
* @brief Extension features functions
*
@verbatim
@@ -106,7 +105,7 @@
* @param AnalogFilter: new state of the Analog filter.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
uint32_t tmp = 0;
@@ -145,7 +144,7 @@
* @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint16_t tmpreg = 0;
uint32_t tmp = 0;
@@ -191,7 +190,7 @@
/**
* @}
*/
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F446xx */
#endif /* HAL_I2C_MODULE_ENABLED */
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,8 +43,8 @@
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -58,27 +58,15 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Constants
+/** @defgroup I2CEx_Exported_Constants I2C Exported Constants
* @{
*/
-/** @defgroup I2CEx_Analog_Filter
+/** @defgroup I2CEx_Analog_Filter I2C Analog Filter
* @{
*/
-#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
-#define I2C_ANALOGFILTER_DISABLED I2C_FLTR_ANOFF
-
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLED))
-/**
- * @}
- */
-
-/** @defgroup I2CEx_Digital_Filter
- * @{
- */
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF
/**
* @}
*/
@@ -89,19 +77,55 @@
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2CEx_Exported_Functions
+ * @{
+ */
+/** @addtogroup I2CEx_Exported_Functions_Group1
+ * @{
+ */
/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
/**
* @}
*/
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Private Constants
+ * @{
+ */
+
/**
* @}
*/
-
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macros I2C Private Macros
+ * @{
+ */
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -33,7 +33,7 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
DMA Tx/Rx Stream.
@@ -109,7 +109,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -143,7 +143,7 @@
* @{
*/
-/** @defgroup I2S
+/** @defgroup I2S I2S
* @brief I2S HAL module driver
* @{
*/
@@ -155,23 +155,28 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Private_Functions
+/** @addtogroup I2S_Private_Functions
* @{
*/
-/** @defgroup I2S_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Sx peripheral in simplex mode:
+ de-initialize the I2Sx peripheral in simplex mode:
(+) User must Implement HAL_I2S_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
@@ -184,10 +189,9 @@
(++) MCLK Output
(++) Audio frequency
(++) Polarity
- (++) Full duplex mode
(+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx periperal.
+ of the selected I2Sx peripheral.
@endverbatim
* @{
*/
@@ -199,7 +203,7 @@
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0, i2sclk = 0;
@@ -211,6 +215,7 @@
}
/* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
@@ -218,10 +223,11 @@
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
- assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
if(hi2s->State == HAL_I2S_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
}
@@ -252,47 +258,7 @@
/* Get I2S source Clock frequency ****************************************/
/* If an external I2S clock has to be used, the specific define should be set
in the project configuration or in the stm32f4xx_conf.h file */
- if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
- {
- /* Set external clock as I2S clock source */
- if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
- {
- RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Set the I2S clock to the external clock value */
- i2sclk = EXTERNAL_CLOCK_VALUE;
- }
- else
- {
- /* Check if PLLI2S is enabled or Not */
- if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
- {
- hi2s->State= HAL_I2S_STATE_READY;
-
- return HAL_ERROR;
- }
-
- /* Set PLLI2S as I2S clock source */
- if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
- {
- RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Get the PLLM value */
- if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
- {
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
- }
- else
- {
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
- }
- i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6));
- i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28));
- }
+ i2sclk = I2S_GetInputClock(hi2s);
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
@@ -333,40 +299,21 @@
/* Configure the I2S with the I2S_InitStruct values */
tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
+ {
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
+ }
+ else
+ {
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+ }
+#else
/* Write to SPIx I2SCFGR */
hi2s->Instance->I2SCFGR = tmpreg;
-
- /* Configure the I2S extended if the full duplex mode is enabled */
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
- I2SxEXT(hi2s->Instance)->I2SPR = 2;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
- {
- tmp = I2S_MODE_SLAVE_RX;
- }
- else
- {
- if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
- {
- tmp = I2S_MODE_SLAVE_TX;
- }
- }
-
- /* Configure the I2S Slave with the I2S Master parameter values */
- tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
-
- /* Write to SPIx I2SCFGR */
- I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
- }
+#endif
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State= HAL_I2S_STATE_READY;
@@ -411,7 +358,7 @@
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspInit could be implenetd in the user file
+ the HAL_I2S_MspInit could be implemented in the user file
*/
}
@@ -424,17 +371,16 @@
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspDeInit could be implenetd in the user file
+ the HAL_I2S_MspDeInit could be implemented in the user file
*/
}
-
/**
* @}
*/
-/** @defgroup I2S_Group2 IO operation functions
- * @brief Data transfers functions
- *
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -568,7 +514,7 @@
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
@@ -821,10 +767,10 @@
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- /* Set the I2S Tx DMA Half transfert complete callback */
+ /* Set the I2S Tx DMA Half transfer complete callback */
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
- /* Set the I2S Tx DMA transfert complete callback */
+ /* Set the I2S Tx DMA transfer complete callback */
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
/* Set the DMA error callback */
@@ -905,10 +851,10 @@
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- /* Set the I2S Rx DMA Half transfert complete callback */
+ /* Set the I2S Rx DMA Half transfer complete callback */
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
- /* Set the I2S Rx DMA transfert complete callback */
+ /* Set the I2S Rx DMA transfer complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
/* Set the DMA error callback */
@@ -957,7 +903,7 @@
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -978,15 +924,11 @@
{
/* Disable the I2S DMA Tx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- /* Disable the I2SEx Rx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
else
{
/* Disable the I2S DMA Rx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- /* Disable the I2SEx Tx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
}
}
@@ -1002,7 +944,7 @@
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1023,15 +965,11 @@
{
/* Enable the I2S DMA Tx request */
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
- /* Disable the I2SEx Rx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
}
else
{
/* Enable the I2S DMA Rx request */
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
- /* Enable the I2SEx Tx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
}
}
@@ -1054,7 +992,7 @@
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1062,14 +1000,7 @@
/* Disable the I2S Tx/Rx DMA requests */
hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
-
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable the I2S extended Tx/Rx DMA requests */
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
-
+
/* Abort the I2S DMA Stream tx */
if(hi2s->hdmatx != HAL_NULL)
{
@@ -1084,12 +1015,6 @@
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable the I2Sext peripheral */
- I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
- }
-
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
@@ -1104,11 +1029,10 @@
* the configuration information for I2S module
* @retval None
*/
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
- uint32_t tmp1 = 0, tmp2 = 0;
- if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
- {
+ uint32_t tmp1 = 0, tmp2 = 0;
+
if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
@@ -1133,68 +1057,10 @@
{
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
- /* I2S in mode Tramitter -----------------------------------------------*/
+ /* I2S in mode Transmitter -----------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
I2S_Transmit_IT(hi2s);
- }
-
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Underrun error interrupt occurred --------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- }
- }
- }
- else
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
- {
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
- /* I2Sext in mode Receiver ---------------------------------------------*/
- if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
- }
-
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
- /* I2Sext Overrun error interrupt occurred ------------------------------*/
- if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
- {
- /* Clear I2Sext OVR Flag */
- I2SxEXT(hi2s->Instance)->DR;
- I2SxEXT(hi2s->Instance)->SR;
- hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
- }
-
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
- /* I2S in mode Tramitter -----------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
}
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
@@ -1204,59 +1070,6 @@
{
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
- /* I2S in mode Receiver ------------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
- if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
- }
-
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Overrun error interrupt occurred ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- }
-
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
- /* I2Sext in mode Tramitter --------------------------------------------*/
- if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
- if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
- }
-
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
- /* I2Sext Underrun error interrupt occurred -----------------------------*/
- if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
- {
- /* Clear I2Sext UDR Flag */
- I2SxEXT(hi2s->Instance)->SR;
- hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
- }
}
}
@@ -1278,7 +1091,7 @@
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
*/
}
@@ -1291,7 +1104,7 @@
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxCpltCallback could be implenetd in the user file
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
}
@@ -1304,7 +1117,7 @@
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implenetd in the user file
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
}
@@ -1317,7 +1130,7 @@
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implenetd in the user file
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
}
@@ -1330,7 +1143,7 @@
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_ErrorCallback could be implenetd in the user file
+ the HAL_I2S_ErrorCallback could be implemented in the user file
*/
}
@@ -1338,9 +1151,8 @@
* @}
*/
-/** @defgroup I2S_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -1370,60 +1182,21 @@
* the configuration information for I2S module
* @retval I2S Error Code
*/
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
{
return hi2s->ErrorCode;
}
-
/**
* @}
*/
/**
- * @brief DMA I2S transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
- {
- hi2s->TxXferCount = 0;
-
- /* Disable Tx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable Rx DMA Request for the slave*/
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->RxXferCount == 0)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- HAL_I2S_TxCpltCallback(hi2s);
-}
-
-/**
* @brief DMA I2S transmit process half complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
-void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+ void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -1431,43 +1204,6 @@
}
/**
- * @brief DMA I2S receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
- {
- /* Disable Rx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable Tx DMA Request for the slave*/
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
-
- hi2s->RxXferCount = 0;
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->TxXferCount == 0)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- HAL_I2S_RxCpltCallback(hi2s);
-}
-
-/**
* @brief DMA I2S receive process half complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
@@ -1505,7 +1241,7 @@
* the configuration information for I2S module
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
@@ -1549,7 +1285,7 @@
* the configuration information for I2S module
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
@@ -1600,7 +1336,7 @@
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param Flag: Flag checked
- * @param State: Value of the flag expected
+ * @param Status: Value of the flag expected
* @param Timeout: Duration of the timeout
* @retval HAL status
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
/**
* @brief I2S Init structure definition
*/
@@ -103,20 +107,6 @@
}HAL_I2S_StateTypeDef;
/**
- * @brief HAL I2S Error Code structure definition
- */
-typedef enum
-{
- HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
- HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
- HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
- HAL_I2SEX_ERROR_UDR = 0x04, /*!< I2S extended Underrun error */
- HAL_I2SEX_ERROR_OVR = 0x08, /*!< I2S extended Overrun error */
- HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
- HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
-}HAL_I2S_ErrorTypeDef;
-
-/**
* @brief I2S handle Structure definition
*/
typedef struct
@@ -145,46 +135,56 @@
__IO HAL_I2S_StateTypeDef State; /* I2S communication state */
- __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
-
+ __IO uint32_t ErrorCode; /* I2S Error code */
+
}I2S_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2S_Exported_Constants
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
-#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
-/** @defgroup I2S_Clock_Source
+/** @defgroup I2S_Error_Code I2S Error Code
+ * @brief I2S Error Code
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000001) /*!< I2S Underrun error */
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< I2S Overrun error */
+#define HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004) /*!< I2S extended Underrun error */
+#define HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008) /*!< I2S extended Overrun error */
+#define HAL_I2S_ERROR_FRE ((uint32_t)0x00000010) /*!< I2S Frame format error */
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000020) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
#define I2S_CLOCK_PLL ((uint32_t)0x00000000)
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
-
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
- ((CLOCK) == I2S_CLOCK_PLL))
+#define I2S_CLOCK_PLLR ((uint32_t)0x00000002)
+#define I2S_CLOCK_PLLSRC ((uint32_t)0x00000003)
/**
* @}
*/
-/** @defgroup I2S_Mode
+/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
-
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX) || \
- ((MODE) == I2S_MODE_MASTER_RX))
/**
* @}
*/
-/** @defgroup I2S_Standard
+/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
@@ -192,53 +192,31 @@
#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
-/** @defgroup I2S_Legacy
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-/**
- * @}
- */
-
/**
* @}
*/
-/** @defgroup I2S_Data_Format
+/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
/**
* @}
*/
-/** @defgroup I2S_MCLK_Output
+/** @defgroup I2S_MCLK_Output I2S Mclk Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
/**
* @}
*/
-/** @defgroup I2S_Audio_Frequency
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
@@ -251,39 +229,29 @@
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
/**
* @}
*/
-/** @defgroup I2S_FullDuplex_Mode
+/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
* @{
*/
#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
-
-#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
- ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
/**
* @}
*/
-/** @defgroup I2S_Clock_Polarity
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW ((uint32_t)0x00000000)
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
/**
* @}
*/
-/** @defgroup I2S_Interrupt_configuration_definition
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_IT_TXE SPI_CR2_TXEIE
@@ -293,7 +261,7 @@
* @}
*/
-/** @defgroup I2S_Flag_definition
+/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXE
@@ -312,9 +280,11 @@
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
+ * @{
+ */
/** @brief Reset I2S handle state
* @param __HANDLE__: specifies the I2S Handle.
@@ -372,27 +342,53 @@
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
- (__HANDLE__)->Instance->SR;}while(0)
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
-
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+/**
+ * @}
+ */
+
/* Include I2S Extension module */
#include "stm32f4xx_hal_i2s_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+ * @{
+ */
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
@@ -411,7 +407,7 @@
/* Peripheral Control and State functions **************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
@@ -419,13 +415,83 @@
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Constants I2S Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+ ((CLOCK) == I2S_CLOCK_PLLR) ||\
+ ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
+ ((CLOCK) == I2S_CLOCK_PLL))
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX) || \
+ ((MODE) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
+ ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
void I2S_DMAError(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
/**
* @}
@@ -433,7 +499,7 @@
/**
* @}
- */
+ */
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
@@ -74,7 +74,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -108,21 +108,32 @@
* @{
*/
-/** @defgroup I2SEx
+/** @defgroup I2SEx I2SEx
* @brief I2S HAL module driver
* @{
*/
#ifdef HAL_I2S_MODULE_ENABLED
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/** @addtogroup I2SEx_Private_Functions
+ * @{
+ */
+/**
+ * @}
+ */
-/** @defgroup I2SEx_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2SEx_Exported_Functions I2S Exported Functions
* @{
*/
@@ -164,6 +175,160 @@
@endverbatim
* @{
*/
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0, i2sclk = 0;
+
+ /* Check the I2S handle allocation */
+ if(hi2s == HAL_NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+ assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
+
+ if(hi2s->State == HAL_I2S_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_I2S_MspInit(hi2s);
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ hi2s->Instance->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = hi2s->Instance->I2SCFGR;
+
+ /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing) *******************/
+ if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get I2S source Clock frequency ****************************************/
+ i2sclk = I2S_GetInputClock(hi2s);
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint32_t)(tmp & (uint32_t)1);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint32_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+
+ /* Configure the I2S with the I2S_InitStruct values */
+ tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
+ {
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
+ }
+ else
+ {
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+ }
+#else
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+#endif
+
+ /* Configure the I2S extended if the full duplex mode is enabled */
+ assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ I2SxEXT(hi2s->Instance)->I2SPR = 2;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
+
+ /* Get the mode to be configured for the extended I2S */
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ {
+ tmp = I2S_MODE_SLAVE_RX;
+ }
+ else
+ {
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
+ {
+ tmp = I2S_MODE_SLAVE_TX;
+ }
+ }
+
+ /* Configure the I2S Slave with the I2S Master parameter values */
+ tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+
+ /* Write to SPIx I2SCFGR */
+ I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
+ }
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
/**
* @brief Full-Duplex Transmit/Receive data in blocking mode.
@@ -464,7 +629,6 @@
}
}
-
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
@@ -523,19 +687,19 @@
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- /* Set the I2S Rx DMA Half transfert complete callback */
+ /* Set the I2S Rx DMA Half transfer complete callback */
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
- /* Set the I2S Rx DMA transfert complete callback */
+ /* Set the I2S Rx DMA transfer complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
/* Set the I2S Rx DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
- /* Set the I2S Tx DMA Half transfert complete callback */
+ /* Set the I2S Tx DMA Half transfer complete callback */
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
- /* Set the I2S Tx DMA transfert complete callback */
+ /* Set the I2S Tx DMA transfer complete callback */
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
/* Set the I2S Tx DMA error callback */
@@ -619,9 +783,330 @@
}
/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ {
+ /* Disable the I2S DMA Tx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ /* Disable the I2SEx Rx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* Disable the I2S DMA Rx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ /* Disable the I2SEx Tx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ {
+ /* Enable the I2S DMA Tx request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ /* Disable the I2SEx Rx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
+ }
+ else
+ {
+ /* Enable the I2S DMA Rx request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ /* Enable the I2SEx Tx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
+ hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
+
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable the I2S extended Tx/Rx DMA requests */
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+
+ /* Abort the I2S DMA Stream tx */
+ if(hi2s->hdmatx != HAL_NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ /* Abort the I2S DMA Stream rx */
+ if(hi2s->hdmarx != HAL_NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable the I2Sext peripheral */
+ I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
+ }
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t tmp1 = 0, tmp2 = 0;
+ __IO uint32_t tmpreg1 = 0;
+ if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ }
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ }
+ }
+ }
+ else
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+ {
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
+ /* I2Sext in mode Receiver ---------------------------------------------*/
+ if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
+ /* I2Sext Overrun error interrupt occurred ------------------------------*/
+ if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
+ {
+ /* Clear I2Sext OVR Flag */
+ tmpreg1 = I2SxEXT(hi2s->Instance)->DR;
+ tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
+ hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
+ UNUSED(tmpreg1);
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ }
+
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
+ /* I2Sext in mode Tramitter --------------------------------------------*/
+ if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
+ /* I2Sext Underrun error interrupt occurred -----------------------------*/
+ if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
+ {
+ /* Clear I2Sext UDR Flag */
+ tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
+ hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
+ UNUSED(tmpreg1);
+ }
+ }
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
+ {
+ /* Set the I2S state ready to be able to start again the process */
+ hi2s->State= HAL_I2S_STATE_READY;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+}
+
+/**
* @}
*/
+
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
@@ -735,7 +1220,249 @@
return HAL_BUSY;
}
}
+#endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ {
+ hi2s->TxXferCount = 0;
+ /* Disable Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable Rx DMA Request for the slave*/
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+#endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if(hi2s->RxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ else
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ {
+ /* Disable Rx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable Tx DMA Request for the slave*/
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+#endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */
+ hi2s->RxXferCount = 0;
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if(hi2s->TxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ else
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ HAL_I2S_RxCpltCallback(hi2s);
+}
+
+/**
+ * @brief Get I2S clock Input based on Source clock selection in RCC
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Clock Input
+ */
+uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
+{
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0;
+ /* This variable used to store the I2S_CK_x (value in Hz) */
+ uint32_t i2ssourceclock = 0;
+
+ /* Configure SAI Clock based on SAI source clock selection */
+#if defined(STM32F446xx)
+ switch(hi2s->Init.ClockSource)
+ {
+ case I2S_CLOCK_EXTERNAL :
+ {
+ /* Set the I2S clock to the external clock value */
+ i2ssourceclock = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ case I2S_CLOCK_PLL :
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
+ break;
+ }
+ case I2S_CLOCK_PLLR :
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6) & (RCC_PLLCFGR_PLLN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28) & (RCC_PLLCFGR_PLLR >> 28)));
+ break;
+ }
+ case I2S_CLOCK_PLLSRC :
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ i2ssourceclock = (uint32_t)(HSE_VALUE);
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ i2ssourceclock = (uint32_t)(HSI_VALUE);
+ }
+ break;
+ }
+ default :
+ {
+ break;
+ }
+ }
+#endif /* STM32F446xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE)
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f4xx_conf.h file */
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+ {
+ /* Enable the External Clock selection */
+ __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
+
+ /* Set the I2S clock to the external clock value */
+ i2ssourceclock = EXTERNAL_CLOCK_VALUE;
+ }
+ else
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
+ }
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */
+
+#if defined(STM32F411xE)
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f4xx_conf.h file */
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+ {
+ /* Enable the External Clock selection */
+ __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
+
+ /* Set the I2S clock to the external clock value */
+ i2ssourceclock = EXTERNAL_CLOCK_VALUE;
+ }
+ else
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
+ }
+#endif /* STM32F411xE */
+
+ /* the return result is the value of SAI clock */
+ return i2ssourceclock;
+
+}
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,20 +54,82 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2SEx_Exported_Types I2S Exported Types
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2SEx_Exported_Constants I2S Exported Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2SEx_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2SEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2SEx_Exported_Functions_Group1
+ * @{
+ */
/* Extended features functions **************************************************/
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2SEx_Private_Constants I2S Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2SEx_Private_Macros I2S Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2SEx_Private_Functions I2S Private Functions
+ * @{
+ */
HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s);
+uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_irda.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
@@ -34,7 +34,7 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
@@ -42,7 +42,7 @@
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_IRDA_MspInit() API.
+ by calling the customized HAL_IRDA_MspInit() API.
-@@- The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
@@ -97,7 +97,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -131,7 +131,7 @@
* @{
*/
-/** @defgroup IRDA
+/** @defgroup IRDA IRDA
* @brief HAL IRDA module driver
* @{
*/
@@ -140,12 +140,22 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup IRDA_Private_Constants
+ * @{
+ */
#define IRDA_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+ * @{
+ */
static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
@@ -153,14 +163,15 @@
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IRDA_Private_Functions
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
* @{
*/
-/** @defgroup IRDA_Group1 IrDA Initialization and de-initialization functions
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -214,6 +225,8 @@
if(hirda->State == HAL_IRDA_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_IRDA_MspInit(hirda);
}
@@ -221,7 +234,7 @@
hirda->State = HAL_IRDA_STATE_BUSY;
/* Disable the IRDA peripheral */
- __IRDA_DISABLE(hirda);
+ __HAL_IRDA_DISABLE(hirda);
/* Set the IRDA communication parameters */
IRDA_SetConfig(hirda);
@@ -233,7 +246,7 @@
hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
/* Enable the IRDA peripheral */
- __IRDA_ENABLE(hirda);
+ __HAL_IRDA_ENABLE(hirda);
/* Set the prescaler */
MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
@@ -270,6 +283,9 @@
hirda->State = HAL_IRDA_STATE_BUSY;
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
/* DeInit the low level hardware */
HAL_IRDA_MspDeInit(hirda);
@@ -292,7 +308,7 @@
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit could be implenetd in the user file
+ the HAL_IRDA_MspInit could be implemented in the user file
*/
}
@@ -305,7 +321,7 @@
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit could be implenetd in the user file
+ the HAL_IRDA_MspDeInit could be implemented in the user file
*/
}
@@ -313,7 +329,7 @@
* @}
*/
-/** @defgroup IRDA_Group2 IO operation functions
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
* @brief IRDA Transmit/Receive functions
*
@verbatim
@@ -338,7 +354,7 @@
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
+ will be executed respectively at the end of the transmit or Receive process
The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode API's are :
@@ -584,15 +600,12 @@
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
- /* Enable the IRDA Parity Error Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
+
/* Enable the IRDA Transmit Data Register Empty Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
@@ -640,18 +653,18 @@
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
/* Enable the IRDA Data Register not empty Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
-
+
/* Enable the IRDA Parity Error Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
+
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
return HAL_OK;
}
else
@@ -698,10 +711,10 @@
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
- /* Set the IRDA DMA transfert complete callback */
+ /* Set the IRDA DMA transfer complete callback */
hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
- /* Set the IRDA DMA half transfert complete callback */
+ /* Set the IRDA DMA half transfer complete callback */
hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
/* Set the DMA error callback */
@@ -711,6 +724,9 @@
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
hirda->Instance->CR3 |= USART_CR3_DMAT;
@@ -763,10 +779,10 @@
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
- /* Set the IRDA DMA transfert complete callback */
+ /* Set the IRDA DMA transfer complete callback */
hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
- /* Set the IRDA DMA half transfert complete callback */
+ /* Set the IRDA DMA half transfer complete callback */
hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
/* Set the DMA error callback */
@@ -818,6 +834,13 @@
hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
}
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@@ -843,20 +866,27 @@
}
else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Enable the UART DMA Rx request */
hirda->Instance->CR3 |= USART_CR3_DMAR;
}
else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Enable the UART DMA Tx & Rx request */
hirda->Instance->CR3 |= USART_CR3_DMAT;
hirda->Instance->CR3 |= USART_CR3_DMAR;
}
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+ return HAL_ERROR;
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@@ -966,6 +996,14 @@
{
IRDA_Transmit_IT(hirda);
}
+
+ tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
+ tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ }
}
/**
@@ -1037,7 +1075,7 @@
* @}
*/
-/** @defgroup IRDA_Group3 Peripheral State and Errors functions
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief IRDA State and Errors functions
*
@verbatim
@@ -1097,27 +1135,8 @@
in the IRDA CR3 register */
hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
- /* Wait for IRDA TC Flag */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- hirda->State = HAL_IRDA_STATE_TIMEOUT;
- HAL_IRDA_ErrorCallback(hirda);
- }
- else
- {
- /* No Timeout */
- /* Check if a receive process is ongoing or not */
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_READY;
- }
- HAL_IRDA_TxCpltCallback(hirda);
- }
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
}
/* DMA Circular mode */
else
@@ -1306,39 +1325,48 @@
/* Disable the IRDA Transmit Data Register Empty Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the IRDA Parity Error Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->State = HAL_IRDA_STATE_READY;
- }
- /* Wait on TC flag to be able to start a second transfer */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
}
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+/**
* @brief Receives an amount of data in non blocking mode.
* @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
@@ -1453,25 +1481,24 @@
/*-------------------------- USART BRR Configuration -----------------------*/
if((hirda->Instance == USART1) || (hirda->Instance == USART6))
{
- hirda->Instance->BRR = __IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
+ hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
}
else
{
- hirda->Instance->BRR = __IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
+ hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
}
}
/**
* @}
*/
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
/**
* @}
*/
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_irda.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,9 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
/**
* @brief IRDA Init Structure definition
*/
@@ -83,7 +85,7 @@
uint8_t Prescaler; /*!< Specifies the Prescaler */
uint32_t IrDAMode; /*!< Specifies the IrDA mode
- This parameter can be a value of @ref IrDA_Low_Power */
+ This parameter can be a value of @ref IRDA_Low_Power */
}IRDA_InitTypeDef;
/**
@@ -93,7 +95,7 @@
{
HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
@@ -102,20 +104,7 @@
}HAL_IRDA_StateTypeDef;
/**
- * @brief HAL IRDA Error Code structure definition
- */
-typedef enum
-{
- HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
- HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
- HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
- HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
- HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_IRDA_ErrorTypeDef;
-
-/**
- * @brief IRDA handle Structure definition
+ * @brief IRDA handle Structure definition
*/
typedef struct
{
@@ -139,68 +128,74 @@
DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /* Locking object */
- __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */
+ __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */
- __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */
-
+ __IO uint32_t ErrorCode; /* IRDA Error code */
+
}IRDA_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants
+/** @defgroup IRDA_Exported_Constants IRDA Exported constants
* @{
*/
+/** @defgroup IRDA_Error_Code IRDA Error Code
+ * @brief IRDA Error Code
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
-/** @defgroup IRDA_Word_Length
+/** @defgroup IRDA_Word_Length IRDA Word Length
* @{
*/
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
/**
* @}
*/
-
-/** @defgroup IRDA_Parity
+/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE ((uint32_t)0x00000000)
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
- ((PARITY) == IRDA_PARITY_EVEN) || \
- ((PARITY) == IRDA_PARITY_ODD))
/**
* @}
*/
-
-/** @defgroup IRDA_Mode
+/** @defgroup IRDA_Mode IRDA Transfer Mode
* @{
*/
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
-/** @defgroup IrDA_Low_Power
+/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
- ((MODE) == IRDA_POWERMODE_NORMAL))
/**
* @}
*/
-/** @defgroup IRDA_Flags
+/** @defgroup IRDA_Flags IRDA Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
@@ -217,28 +212,25 @@
* @}
*/
-/** @defgroup IRDA_Interrupt_definition
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
- *
* @{
*/
-
-#define IRDA_IT_PE ((uint32_t)0x10000100)
-#define IRDA_IT_TXE ((uint32_t)0x10000080)
-#define IRDA_IT_TC ((uint32_t)0x10000040)
-#define IRDA_IT_RXNE ((uint32_t)0x10000020)
-#define IRDA_IT_IDLE ((uint32_t)0x10000010)
+#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define IRDA_IT_LBD ((uint32_t)0x20000040)
+#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
-#define IRDA_IT_CTS ((uint32_t)0x30000400)
-#define IRDA_IT_ERR ((uint32_t)0x30000001)
-
+#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@@ -248,6 +240,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
/** @brief Reset IRDA handle state
* @param __HANDLE__: specifies the USART Handle.
@@ -310,8 +305,13 @@
* UART peripheral.
* @retval None
*/
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
- (__HANDLE__)->Instance->DR;}while(0)
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
/** @brief Clear the IRDA FE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
@@ -356,17 +356,14 @@
* @arg IRDA_IT_IDLE: Idle line detection interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified IRDA interrupt.
- * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
-#define IRDA_IT_MASK ((uint32_t)0x0000FFFF)
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
/** @brief Checks whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__: specifies the USART Handle.
@@ -385,26 +382,58 @@
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
+/** @brief Macro to enable the IRDA's one bit sample method
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+/** @brief Macro to disable the IRDA's one bit sample method
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-#define __IRDA_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define __IRDA_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+/** @brief Enable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __IRDA_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
-
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+/** @addtogroup IRDA_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -421,10 +450,76 @@
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+/** @addtogroup IRDA_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+
+/** @brief IRDA interruptions flag mask
+ *
+ */
+#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+
+#define IRDA_CR1_REG_INDEX 1
+#define IRDA_CR2_REG_INDEX 2
+#define IRDA_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
+
+#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define IRDA_BRR(_PCLK_, _BAUD_) ((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,18 +2,18 @@
******************************************************************************
* @file stm32f4xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
- * + Initialization and de-initialization functions
+ * + Initialization and Configuration functions
* + IO operation functions
* + Peripheral State functions
*
@verbatim
==============================================================================
- ##### IWDG Generic features #####
+ ##### IWDG Specific features #####
==============================================================================
[..]
(+) The IWDG can be started by either software or hardware (configurable
@@ -76,15 +76,13 @@
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
- (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
- (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -118,7 +116,7 @@
* @{
*/
-/** @defgroup IWDG
+/** @defgroup IWDG IWDG
* @brief IWDG HAL module driver.
* @{
*/
@@ -127,17 +125,23 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+ /** @addtogroup IWDG_Private_Constants
+ * @{
+ */
#define IWDG_TIMEOUT_FLAG ((uint32_t)1000) /* 1 s */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
-/** @defgroup IWDG_Group1 Initialization and de-initialization functions
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@@ -176,6 +180,8 @@
if(hiwdg->State == HAL_IWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hiwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
}
@@ -184,7 +190,7 @@
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Enable write access to IWDG_PR and IWDG_RLR registers */
- __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
@@ -214,7 +220,7 @@
* @}
*/
-/** @defgroup IWDG_Group2 IO operation functions
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -309,7 +315,7 @@
* @}
*/
-/** @defgroup IWDG_Group3 Peripheral State functions
+/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
/**
* @brief IWDG HAL State Structure definition
*/
@@ -66,7 +69,6 @@
HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
-
}HAL_IWDG_StateTypeDef;
/**
@@ -79,11 +81,10 @@
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
}IWDG_InitTypeDef;
/**
- * @brief IWDG handle Structure definition
+ * @brief IWDG Handle Structure definition
*/
typedef struct
{
@@ -91,49 +92,44 @@
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
- HAL_LockTypeDef Lock; /*!< IWDG locking object */
+ HAL_LockTypeDef Lock; /*!< IWDG Locking object */
__IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
-
}IWDG_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_Registers_BitMask
- * @{
- */
-/* --- KR Register ---*/
-/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG reload counter enable */
-#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG peripheral enable */
-#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR write Access enable */
-#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR write Access disable */
-
-#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \
- ((__KR__) == KR_KEY_ENABLE))|| \
- ((__KR__) == KR_KEY_EWA)) || \
- ((__KR__) == KR_KEY_DWA))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag_definition
- * @{
- */
-#define IWDG_FLAG_PVU ((uint32_t)0x0001) /*!< Watchdog counter prescaler value update flag */
-#define IWDG_FLAG_RVU ((uint32_t)0x0002) /*!< Watchdog counter reload value update flag */
-
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
- ((FLAG) == IWDG_FLAG_RVU))
-
/**
* @}
*/
-/** @defgroup IWDG_Prescaler
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
+ * @brief IWDG registers bit mask
+ * @{
+ */
+/* --- KR Register ---*/
+/* KR register bit mask */
+#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag_definition IWDG Flag definition
+ * @{
+ */
+#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */
+#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
@@ -143,25 +139,6 @@
#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
-
-
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \
- ((PRESCALER) == IWDG_PRESCALER_8) || \
- ((PRESCALER) == IWDG_PRESCALER_16) || \
- ((PRESCALER) == IWDG_PRESCALER_32) || \
- ((PRESCALER) == IWDG_PRESCALER_64) || \
- ((PRESCALER) == IWDG_PRESCALER_128)|| \
- ((PRESCALER) == IWDG_PRESCALER_256))
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Reload_Value
- * @{
- */
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-
/**
* @}
*/
@@ -170,10 +147,13 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
/** @brief Reset IWDG handle state
- * @param __HANDLE__: IWDG handle
+ * @param __HANDLE__: IWDG handle.
* @retval None
*/
#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
@@ -183,7 +163,7 @@
* @param __HANDLE__: IWDG handle
* @retval None
*/
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE)
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reloads IWDG counter with value defined in the reload register
@@ -191,21 +171,7 @@
* @param __HANDLE__: IWDG handle
* @retval None
*/
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD)
-
-/**
- * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA)
-
-/**
- * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA)
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @brief Gets the selected IWDG's flag status.
@@ -218,21 +184,95 @@
*/
#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+/** @addtogroup IWDG_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
/**
* @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+/**
+ * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+ /** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
*/
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
@@ -35,7 +35,7 @@
(#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
and HAL_LTDC_EnableColorKeying functions.
- (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineInterrupt()
+ (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
function
(#) If needed, reconfigure and change the pixel format value, the alpha value
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,7 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @defgroup LTDC
+/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
@@ -119,11 +119,11 @@
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
/* Private functions ---------------------------------------------------------*/
-/** @defgroup LTDC_Private_Functions
+/** @defgroup LTDC_Exported_Functions LTDC Exported Functions
* @{
*/
-/** @defgroup LTDC_Group1 Initialization and Configuration functions
+/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -172,6 +172,8 @@
if(hltdc->State == HAL_LTDC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hltdc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
}
@@ -219,7 +221,7 @@
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
- /* Initialise the error code */
+ /* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
/* Initialize the LTDC state*/
@@ -241,7 +243,7 @@
/* DeInit the low level hardware */
HAL_LTDC_MspDeInit(hltdc);
- /* Initialise the error code */
+ /* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
/* Initialize the LTDC state*/
@@ -283,7 +285,7 @@
* @}
*/
-/** @defgroup LTDC_Group2 IO operation functions
+/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -405,7 +407,7 @@
* @}
*/
-/** @defgroup LTDC_Group3 Peripheral Control functions
+/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -502,8 +504,8 @@
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Configures the default color values */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
/* Sets the Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
@@ -545,12 +547,19 @@
for(counter = 0; (counter < CLUTSize); counter++)
{
- tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
+ if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
+ {
+ tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
+ }
+ else
+ {
+ tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
+ }
pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
pCLUT = (uint32_t *)pcounter;
/* Specifies the C-LUT address and RGB value */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;
+ LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;
}
/* Change the LTDC state*/
@@ -583,7 +592,7 @@
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Enable LTDC color keying by setting COLKEN bit */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
/* Sets the Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
@@ -618,7 +627,7 @@
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Disable LTDC color keying by setting COLKEN bit */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
/* Sets the Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
@@ -654,7 +663,7 @@
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Disable LTDC color lookup table by setting CLUTEN bit */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
/* Sets the Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
@@ -690,7 +699,7 @@
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Disable LTDC color lookup table by setting CLUTEN bit */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
/* Sets the Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
@@ -1044,7 +1053,7 @@
* @}
*/
-/** @defgroup LTDC_Group4 Peripheral State and Errors functions
+/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -1090,7 +1099,7 @@
* @brief Configures the LTDC peripheral
* @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pLayerCfg: Pointer LTDC Layer Configuration strusture
+ * @param pLayerCfg: Pointer LTDC Layer Configuration structure
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values: 0 or 1
* @retval None
@@ -1103,36 +1112,36 @@
/* Configures the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);
/* Configures the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);
/* Specifies the pixel format */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
/* Configures the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);
tmp2 = (pLayerCfg->Alpha0 << 24);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
/* Specifies the constant alpha value */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
+ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
+ LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
/* Specifies the blending factors */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
/* Configures the color frame buffer start address */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
@@ -1155,15 +1164,15 @@
}
/* Configures the color frame buffer pitch in byte */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | ((pLayerCfg->ImageWidth * tmp) + 3));
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3));
/* Configures the frame buffer line number */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
/* Enable LTDC_Layer by setting LEN bit */
- __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
}
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -47,17 +47,19 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @addtogroup LTDC
+/** @defgroup LTDC LTDC
+ * @brief LTDC HAL module driver
* @{
*/
-
+
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup LTDC_Exported_Types LTDC Exported Types
+ * @{
+ */
#define MAX_LAYER 2
/**
@@ -97,31 +99,30 @@
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
- uint32_t VerticalSync; /*!< configures the number of Vertical synchronization heigh.
+ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
- uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh.
+ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
- uint32_t AccumulatedActiveH; /*!< configures the accumulated active heigh.
+ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
uint32_t TotalWidth; /*!< configures the total width.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
- uint32_t TotalHeigh; /*!< configures the total heigh.
+ uint32_t TotalHeigh; /*!< configures the total height.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
} LTDC_InitTypeDef;
-
/**
* @brief LTDC Layer structure definition
*/
@@ -195,135 +196,98 @@
__IO uint32_t ErrorCode; /*!< LTDC Error code */
} LTDC_HandleTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Constants
- * @{
- */
-
-/** @defgroup LTDC_Layer
- * @{
- */
-#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
-/**
- * @}
- */
-
-/** @defgroup LTDC Error Code
- * @{
- */
-#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000) /*!< LTDC No error */
-#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001) /*!< LTDC Transfer error */
-#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002) /*!< LTDC FIFO Underrun */
-#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< LTDC Timeout error */
-
/**
* @}
*/
-/** @defgroup LTDC_HS_POLARITY
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
* @{
*/
-#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
-#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
-#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
- ((HSPOL) == LTDC_HSPOLARITY_AH))
+/** @defgroup LTDC_Error_Code LTDC Error Code
+ * @{
+ */
+#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000) /*!< LTDC No error */
+#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001) /*!< LTDC Transfer error */
+#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002) /*!< LTDC FIFO Underrun */
+#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< LTDC Timeout error */
/**
* @}
*/
-/** @defgroup LTDC_VS_POLARITY
+/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{
*/
-#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
-#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
-
-#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \
- ((VSPOL) == LTDC_VSPOLARITY_AH))
-/**
- * @}
- */
-
-/** @defgroup LTDC_DE_POLARITY
- * @{
- */
-#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
-#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
-
-#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || \
- ((DEPOL) == LTDC_DEPOLARITY_AH))
+#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/**
* @}
*/
-/** @defgroup LTDC_PC_POLARITY
+/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{
*/
-#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
-#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
-
-#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || \
- ((PCPOL) == LTDC_PCPOLARITY_IIPC))
+#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
+ * @{
+ */
+#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/**
* @}
*/
-/** @defgroup LTDC_SYNC
+/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{
*/
-#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
-#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization heigh. */
-
-#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)
+#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/**
* @}
*/
-/** @defgroup LTDC_BACK_COLOR
+/** @defgroup LTDC_SYNC LTDC SYNC
* @{
- */
-#define LTDC_COLOR ((uint32_t)0x000000FF) /*!< Color mask */
+ */
+#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
+#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
+/**
+ * @}
+ */
-#define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR)
-#define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR)
-#define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR)
+/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
+ * @{
+ */
+#define LTDC_COLOR ((uint32_t)0x000000FF) /*!< Color mask */
/**
* @}
*/
-/** @defgroup LTDC_BlendingFactor1
+/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{
*/
#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
-
-#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
- ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
/**
* @}
*/
-/** @defgroup LTDC_BlendingFactor2
+/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{
*/
#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
-
-#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
- ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
/**
* @}
*/
-/** @defgroup LTDC_Pixelformat
+/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */
@@ -334,26 +298,19 @@
#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006) /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007) /*!< AL88 LTDC pixel format */
-
-#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || \
- ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
- ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || \
- ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
/**
* @}
*/
-/** @defgroup LTDC_Alpha
+/** @defgroup LTDC_Alpha LTDC Alpha
* @{
*/
#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */
-
-#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)
/**
* @}
*/
-/** @defgroup LTDC_LAYER_Config
+/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
* @{
*/
#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */
@@ -361,51 +318,28 @@
#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
-
-#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)
-#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)
-#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION)
-#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)
-
-#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
-#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
-
-#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
/**
* @}
*/
-/** @defgroup LTDC_LIPosition
- * @{
- */
-#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
-/**
- * @}
- */
-
-/** @defgroup LTDC_Interrupts
+/** @defgroup LTDC_Interrupts LTDC Interrupts
* @{
*/
#define LTDC_IT_LI LTDC_IER_LIE
#define LTDC_IT_FU LTDC_IER_FUIE
#define LTDC_IT_TE LTDC_IER_TERRIE
#define LTDC_IT_RR LTDC_IER_RRIE
-
-#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
-/** @defgroup LTDC_Flag
+/** @defgroup LTDC_Flag LTDC Flag
* @{
*/
#define LTDC_FLAG_LI LTDC_ISR_LIF
#define LTDC_FLAG_FU LTDC_ISR_FUIF
#define LTDC_FLAG_TE LTDC_ISR_TERRIF
#define LTDC_FLAG_RR LTDC_ISR_RRIF
-
-#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
- ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
/**
* @}
*/
@@ -415,6 +349,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
+ * @{
+ */
/** @brief Reset LTDC handle state
* @param __HANDLE__: specifies the LTDC handle.
@@ -440,21 +377,19 @@
* @brief Enable the LTDC Layer.
* @param __HANDLE__: LTDC handle
* @param __LAYER__: Specify the layer to be enabled
- This parameter can be 0 or 1
+ * This parameter can be 0 or 1
* @retval None.
*/
-#define __HAL_LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))
-
-#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
* @param __HANDLE__: LTDC handle
* @param __LAYER__: Specify the layer to be disabled
- This parameter can be 0 or 1
+ * This parameter can be 0 or 1
* @retval None.
*/
-#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
/**
* @brief Reload Layer Configuration.
@@ -528,9 +463,17 @@
* @retval The state of INTERRUPT (SET or RESET).
*/
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-
+/** @addtogroup LTDC_Exported_Functions
+ * @{
+ */
+/** @addtogroup LTDC_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
@@ -538,10 +481,22 @@
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
+/**
+ * @}
+ */
+/** @addtogroup LTDC_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *****************************************************/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
+/**
+ * @}
+ */
+/** @addtogroup LTDC_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
@@ -558,12 +513,104 @@
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+/**
+ * @}
+ */
+/** @addtogroup LTDC_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral State functions *************************************************/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
+/**
+ * @}
+ */
-#endif /* STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LTDC_Private_Types LTDC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LTDC_Private_Variables LTDC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LTDC_Private_Constants LTDC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LTDC_Private_Macros LTDC Private Macros
+ * @{
+ */
+#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
+#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
+#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
+ ((HSPOL) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \
+ ((VSPOL) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || \
+ ((DEPOL) == LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || \
+ ((PCPOL) == LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR)
+#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
+ ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
+#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
+ ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
+#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
+#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)
+#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)
+#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
+#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -572,7 +619,9 @@
/**
* @}
*/
-
+
+#endif /* STM32F429xx || STM32F439xx */
+
#ifdef __cplusplus
}
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_msp_template.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,119 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_msp_template.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief This file contains the HAL System and Peripheral (PPP) MSP initialization
+ * and de-initialization functions.
+ * It should be copied to the application folder and renamed into 'stm32f4xx_hal_msp.c'.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_MSP HAL MSP
+ * @brief HAL MSP module.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the Global MSP.
+ * @note This function is called from HAL_Init() function to perform system
+ * level initialization (GPIOs, clock, DMA, interrupt).
+ * @retval None
+ */
+void HAL_MspInit(void)
+{
+
+}
+
+/**
+ * @brief DeInitializes the Global MSP.
+ * @note This functiona is called from HAL_DeInit() function to perform system
+ * level de-initialization (GPIOs, clock, DMA, interrupt).
+ * @retval None
+ */
+void HAL_MspDeInit(void)
+{
+
+}
+
+/**
+ * @brief Initializes the PPP MSP.
+ * @note This functiona is called from HAL_PPP_Init() function to perform
+ * peripheral(PPP) system level initialization (GPIOs, clock, DMA, interrupt)
+ * @retval None
+ */
+void HAL_PPP_MspInit(void)
+{
+
+}
+
+/**
+ * @brief DeInitializes the PPP MSP.
+ * @note This functiona is called from HAL_PPP_DeInit() function to perform
+ * peripheral(PPP) system level de-initialization (GPIOs, clock, DMA, interrupt)
+ * @retval None
+ */
+void HAL_PPP_MspDeInit(void)
+{
+
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nand.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -89,26 +89,44 @@
* @{
*/
-/** @defgroup NAND
- * @brief NAND driver modules
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
+
+/** @defgroup NAND NAND
+ * @brief NAND HAL module driver
* @{
*/
-#ifdef HAL_NAND_MODULE_ENABLED
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup NAND_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
-/** @defgroup NAND_Group1 Initialization and de-initialization functions
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -141,6 +159,8 @@
if(hnand->State == HAL_NAND_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hnand->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
}
@@ -280,7 +300,7 @@
* @}
*/
-/** @defgroup NAND_Group2 Input and Output functions
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -305,7 +325,7 @@
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
__IO uint32_t data = 0;
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -319,34 +339,34 @@
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
+ /* Send Read ID command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- /* Read the electronic signature from NAND flash */
- data = *(__IO uint32_t *)deviceAddress;
+ /* Read the electronic signature from NAND flash */
+ data = *(__IO uint32_t *)deviceaddress;
/* Return the data read */
- pNAND_ID->Maker_Id = __ADDR_1st_CYCLE(data);
- pNAND_ID->Device_Id = __ADDR_2nd_CYCLE(data);
- pNAND_ID->Third_Id = __ADDR_3rd_CYCLE(data);
- pNAND_ID->Fourth_Id = __ADDR_4th_CYCLE(data);
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
@@ -359,44 +379,43 @@
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
- uint32_t deviceAddress = 0;
-
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnand);
-
+
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
- /* Identify the device address */
+ /* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
-
-
- /* Update the NAND controller state */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
-
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
-
+
}
-
/**
* @brief Read Page(s) from NAND memory block
@@ -407,10 +426,12 @@
* @param NumPageToRead : number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
{
__IO uint32_t index = 0;
- uint32_t deviceAddress = 0, numPagesRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
+ uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -424,61 +445,68 @@
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Page(s) read loop */
- while((NumPageToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
- {
- /* NAND raw address calculation */
- nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr > 1024)
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for(index = 0 ; index < hnand->Info.PageSize; index++)
+ for(index = size; index != 0; index--)
{
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
NumPageToRead--;
/* Increment the NAND address */
- HAL_NAND_Address_Inc(hnand, pAddress);
-
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
-
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
}
@@ -492,11 +520,13 @@
* @param NumPageToWrite : number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
{
- __IO uint32_t index = 0;
+ __IO uint32_t index = 0;
uint32_t tickstart = 0;
- uint32_t deviceAddress = 0 , numPagesWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
+ uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -510,78 +540,84 @@
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
/* Page(s) write loop */
- while((NumPageToWrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
- {
- /* NAND raw address calculation */
- nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
-
+ while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr > 1024)
+ if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
/* Write data to memory */
- for(index = 0 ; index < hnand->Info.PageSize; index++)
+ for(index = size; index != 0; index--)
{
- *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- /* Get tick */
- tickstart = HAL_GetTick();
-
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
NumPageToWrite--;
/* Increment the NAND address */
- HAL_NAND_Address_Inc(hnand, pAddress);
-
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
-
/**
* @brief Read Spare area(s) from NAND memory
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
@@ -591,10 +627,12 @@
* @param NumSpareAreaToRead: Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
__IO uint32_t index = 0;
- uint32_t deviceAddress = 0, numSpareAreaRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -608,59 +646,67 @@
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
/* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
- {
- /* NAND raw address calculation */
- nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
+ while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr > 1024)
+ if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
+ for (index = size ;index != 0; index--)
{
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ num_spare_area_read++;
/* Decrement spare areas to read */
NumSpareAreaToRead--;
/* Increment the NAND address */
- HAL_NAND_Address_Inc(hnand, pAddress);
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
@@ -674,11 +720,13 @@
* @param NumSpareAreaTowrite : number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
__IO uint32_t index = 0;
uint32_t tickstart = 0;
- uint32_t deviceAddress = 0, numSpareAreaWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -692,67 +740,73 @@
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the FMC_NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
/* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
- {
- /* NAND raw address calculation */
- nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
+ while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
/* Write data to memory */
- for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
+ for(; index < size; index++)
{
- *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- /* Get tick */
- tickstart = HAL_GetTick();
-
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ num_spare_area_written++;
/* Decrement spare areas to write */
NumSpareAreaTowrite--;
/* Increment the NAND address */
- HAL_NAND_Address_Inc(hnand, pAddress);
-
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
@@ -761,7 +815,7 @@
/* Process unlocked */
__HAL_UNLOCK(hnand);
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -771,9 +825,10 @@
* @param pAddress : pointer to NAND address structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
- uint32_t DeviceAddress = 0;
+ uint32_t deviceaddress = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -787,41 +842,55 @@
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- DeviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- DeviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
}
-
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
-
/**
* @brief NAND memory read status
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
@@ -831,23 +900,23 @@
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
uint32_t data = 0;
- uint32_t DeviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
- DeviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- DeviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
- data = *(__IO uint8_t *)DeviceAddress;
+ data = *(__IO uint8_t *)deviceaddress;
/* Return the status */
if((data & NAND_ERROR) == NAND_ERROR)
@@ -860,19 +929,18 @@
}
return NAND_BUSY;
-
}
/**
* @brief Increment the NAND memory address
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND adress structure
+ * @param pAddress: pointer to NAND address structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
@@ -899,13 +967,11 @@
return (status);
}
-
-
/**
* @}
*/
-/** @defgroup NAND_Group3 Control functions
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
@@ -944,17 +1010,16 @@
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
- return HAL_OK;
+ return HAL_OK;
}
-
/**
* @brief Disables dynamically FMC_NAND ECC feature.
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
@@ -1003,13 +1068,13 @@
return status;
}
-
+
/**
* @}
*/
-/** @defgroup NAND_Group4 State functions
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -1042,15 +1107,19 @@
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx */
+
#endif /* HAL_NAND_MODULE_ENABLED */
/**
* @}
*/
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_nand.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,13 +44,13 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
#include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -60,10 +60,15 @@
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
+
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
/**
* @brief HAL NAND State structures definition
@@ -103,7 +108,7 @@
uint16_t Block; /*!< NAND memory Block address */
-}NAND_AddressTypedef;
+}NAND_AddressTypeDef;
/**
* @brief NAND Memory info Structure definition
@@ -136,12 +141,99 @@
NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
}NAND_HandleTypeDef;
-
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup NAND_Exported_Constants
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__: specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
#define NAND_DEVICE1 ((uint32_t)0x70000000)
#define NAND_DEVICE2 ((uint32_t)0x80000000)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
@@ -149,16 +241,16 @@
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
@@ -170,18 +262,14 @@
#define NAND_BUSY ((uint32_t)0x00000000)
#define NAND_ERROR ((uint32_t)0x00000001)
#define NAND_READY ((uint32_t)0x00000040)
-
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @brief Reset NAND handle state
- * @param __HANDLE__: specifies the NAND handle.
- * @retval None
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
*/
-#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
/**
* @brief NAND memory address computation.
@@ -189,50 +277,28 @@
* @param __HANDLE__ : NAND handle.
* @retval NAND Raw address value
*/
-#define __ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
-
+
/**
* @brief NAND memory address cycling.
* @param __ADDRESS__: NAND memory address.
* @retval NAND address cycling value.
*/
-#define __ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define __ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
-#define __ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
-#define __ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
-
-/* Exported functions --------------------------------------------------------*/
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/* IO operation functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
-
-/* NAND Control functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx */
+
+/**
+ * @}
+ */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nor.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -49,13 +49,13 @@
[..]
Below the list of most used macros in NOR HAL driver.
- (+) __NOR_WRITE : NOR memory write data to specified address
+ (+) NOR_WRITE : NOR memory write data to specified address
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -89,27 +89,63 @@
* @{
*/
-/** @defgroup NOR
+/** @defgroup NOR NOR
* @brief NOR driver modules
* @{
*/
#ifdef HAL_NOR_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup NOR_Private_Functions
+/** @defgroup NOR_Private_Defines NOR Private Defines
* @{
*/
-/** @defgroup NOR_Group1 Initialization and de-initialization functions
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -141,10 +177,12 @@
if(hnor->State == HAL_NOR_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hnor->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
}
-
+
/* Initialize NOR control Interface */
FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
@@ -155,7 +193,7 @@
FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -213,7 +251,7 @@
}
/**
- * @brief NOR BSP Wait fro Ready/Busy signal
+ * @brief NOR BSP Wait for Ready/Busy signal
* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Timeout: Maximum timeout value
@@ -230,7 +268,7 @@
* @}
*/
-/** @defgroup NOR_Group2 Input and Output functions
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -252,7 +290,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -266,34 +304,34 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read ID command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
/* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -311,7 +349,7 @@
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -325,22 +363,22 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
- __NOR_WRITE(deviceAddress, 0x00F0);
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -360,7 +398,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -374,31 +412,31 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
- __NOR_WRITE(pAddress, 0x00F0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ __NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
/* Read the data */
- *pData = *(__IO uint32_t *)pAddress;
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -418,7 +456,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -432,31 +470,31 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send program data command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
/* Write the data */
- __NOR_WRITE(pAddress, *pData);
+ NOR_WRITE(pAddress, *pData);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -478,7 +516,7 @@
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -492,28 +530,28 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
- __NOR_WRITE(uwAddress, 0x00F0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(uwAddress, 0x00F0);
/* Read buffer */
while( uwBufferSize > 0)
@@ -543,10 +581,9 @@
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
- uint32_t lastloadedaddress = 0;
- uint32_t currentaddress = 0;
- uint32_t endaddress = 0;
- uint32_t deviceAddress = 0;
+ uint16_t * p_currentaddress = (uint16_t *)NULL;
+ uint16_t * p_endaddress = (uint16_t *)NULL;
+ uint32_t lastloadedaddress = 0, deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -560,49 +597,49 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Initialize variables */
- currentaddress = uwAddress;
- endaddress = uwAddress + uwBufferSize - 1;
- lastloadedaddress = uwAddress;
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
+ p_endaddress = p_currentaddress + (uwBufferSize-1);
+ lastloadedaddress = (uint32_t)(uwAddress);
/* Issue unlock command sequence */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
/* Write Buffer Load Command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
/* Load Data into NOR Buffer */
- while(currentaddress <= endaddress)
+ while(p_currentaddress <= p_endaddress)
{
/* Store last loaded address & data value (for polling) */
- lastloadedaddress = currentaddress;
+ lastloadedaddress = (uint32_t)p_currentaddress;
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
+ NOR_WRITE(p_currentaddress, *pData++);
- currentaddress += 1;
+ p_currentaddress ++;
}
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -623,7 +660,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -637,31 +674,31 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send block erase command sequence */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -681,7 +718,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -695,31 +732,31 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send NOR chip erase command sequence */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -738,7 +775,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -752,32 +789,32 @@
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read CFI query command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
/* read the NOR CFI information */
- pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS);
- pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS);
- pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS);
- pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS);
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -792,7 +829,7 @@
* @}
*/
-/** @defgroup NOR_Group3 Control functions
+/** @defgroup NOR_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
@@ -858,7 +895,7 @@
* @}
*/
-/** @defgroup NOR_Group4 State functions
+/** @defgroup NOR_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
@@ -887,13 +924,13 @@
* @brief Returns the NOR operation status.
* @param hnor: pointer to the NOR handle
* @param Address: Device address
- * @param Timeout: NOR progamming Timeout
- * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
- * or NOR_TIMEOUT
+ * @param Timeout: NOR programming Timeout
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+ * or HAL_NOR_STATUS_TIMEOUT
*/
-NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
- NOR_StatusTypedef status = NOR_ONGOING;
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpSR1 = 0, tmpSR2 = 0;
uint32_t tickstart = 0;
@@ -901,16 +938,17 @@
HAL_NOR_MspWait(hnor, Timeout);
/* Get the NOR memory operation status -------------------------------------*/
- while(status != NOR_SUCCESS)
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
{
- /* Get tick */
- tickstart = HAL_GetTick();
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
- status = NOR_TIMEOUT;
+ status = HAL_NOR_STATUS_TIMEOUT;
}
}
@@ -918,29 +956,28 @@
tmpSR1 = *(__IO uint16_t *)Address;
tmpSR2 = *(__IO uint16_t *)Address;
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
{
- return NOR_SUCCESS;
+ return HAL_NOR_STATUS_SUCCESS ;
}
- if((tmpSR1 & 0x0020) == 0x0020)
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
- return NOR_ONGOING;
+ status = HAL_NOR_STATUS_ONGOING;
}
tmpSR1 = *(__IO uint16_t *)Address;
tmpSR2 = *(__IO uint16_t *)Address;
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
{
- return NOR_SUCCESS;
+ return HAL_NOR_STATUS_SUCCESS;
}
-
- if((tmpSR1 & 0x0020) == 0x0020)
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
- return NOR_ERROR;
+ return HAL_NOR_STATUS_ERROR;
}
}
@@ -951,11 +988,13 @@
/**
* @}
*/
+
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_NOR_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_nor.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,13 +44,13 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
#include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -60,9 +60,15 @@
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
/**
* @brief HAL SRAM State structures definition
*/
@@ -80,11 +86,11 @@
*/
typedef enum
{
- NOR_SUCCESS = 0,
- NOR_ONGOING,
- NOR_ERROR,
- NOR_TIMEOUT
-}NOR_StatusTypedef;
+ HAL_NOR_STATUS_SUCCESS = 0,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
/**
* @brief FMC NOR ID typedef
@@ -97,7 +103,7 @@
uint16_t Device_Code2;
- uint16_t Device_Code3; /*!< Defines the devices' codes used to identify the memory.
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
These codes can be accessed by performing read operations with specific
control signals and addresses set.They can also be accessed by issuing
an Auto Select command */
@@ -136,10 +142,90 @@
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-}NOR_HandleTypeDef;
+}NOR_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+ * @{
+ */
+/** @brief Reset NOR handle state
+ * @param __HANDLE__: specifies the NOR handle.
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions
+ * @{
+ */
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup NOR_Exported_Constants
+/** @addtogroup NOR_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3
+ * @{
+ */
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4
+ * @{
+ */
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
* @{
*/
/* NOR device IDs addresses */
@@ -166,66 +252,38 @@
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
-
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Reset NOR handle state
- * @param __HANDLE__: specifies the NOR handle.
- * @retval None
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
*/
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-
/**
* @brief NOR memory address shifting.
- * @param __ADDRESS__: NOR memory address
+ * @param __NOR_ADDRESS__: NOR base address
+ * @param NOR_MEMORY_WIDTH: NOR memory width
+ * @param ADDRESS: NOR memory address
* @retval NOR shifted address value
*/
-#define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) (((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):\
- ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2 * (ADDRESS)))):\
+ ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
/**
* @brief NOR memory write data to specified address.
- * @param __ADDRESS__: NOR memory address
- * @param __DATA__: Data to write
+ * @param ADDRESS: NOR memory address
+ * @param DATA: Data to write
* @retval None
*/
-#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
-
-/* Exported functions --------------------------------------------------------*/
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+#define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-/* NOR Control functions *****************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-
-/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -17,37 +17,40 @@
control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
to interface with PCCARD devices. This driver is used for:
- (+) PCCARD/compact flash memory configuration sequence using the function
- HAL_PCCARD_Init() with control and timing parameters for both common and
- attribute spaces.
+ (+) PCCARD/Compact Flash memory configuration sequence using the function
+ HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
+ both common and attribute spaces.
- (+) Read PCCARD/compact flash memory maker and device IDs using the function
- HAL_CF_Read_ID(). The read information is stored in the CompactFlash_ID
- structure declared by the function caller.
+ (+) Read PCCARD/Compact Flash memory maker and device IDs using the function
+ HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
+ the CompactFlash_ID structure declared by the function caller.
- (+) Access PCCARD/compact flash memory by read/write operations using the functions
+ (+) Access PCCARD/Compact Flash memory by read/write operations using the functions
+ HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
- (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_CF_Reset().
+ (+) Perform PCCARD/Compact Flash Reset chip operation using the function
+ HAL_PCCARD_Reset()/HAL_CF_Reset.
- (+) Perform PCCARD/compact flash erase sector operation using the function
- HAL_CF_Erase_Sector().
+ (+) Perform PCCARD/Compact Flash erase sector operation using the function
+ HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
- (+) Read the PCCARD/compact flash status operation using the function HAL_CF_ReadStatus().
+ (+) Read the PCCARD/Compact Flash status operation using the function
+ HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
- (+) You can monitor the PCCARD/compact flash device HAL state by calling the function
- HAL_PCCARD_GetState()
+ (+) You can monitor the PCCARD/Compact Flash device HAL state by calling
+ the function HAL_PCCARD_GetState()/HAL_CF_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
- operations. If a PCCARD/compact flash device contains different operations
+ operations. If a PCCARD/Compact Flash device contains different operations
and/or implementations, it should be implemented separately.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -81,25 +84,39 @@
* @{
*/
-/** @defgroup PCCARD
- * @brief PCCARD driver modules
+#ifdef HAL_PCCARD_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup PCCARD PCCARD
+ * @brief PCCARD HAL module driver
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
* @{
*/
-#ifdef HAL_PCCARD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_READ_WRITE_SECTOR (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_ERASE_SECTOR (uint32_t)0x00000400
+#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+#define PCCARD_STATUS_OK (uint8_t)0x58
+#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PCCARD_Private_Functions
+/* Private function ----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
* @{
*/
-/** @defgroup PCCARD_Group1 Initialization and de-initialization functions
+/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -133,6 +150,8 @@
if(hpccard->State == HAL_PCCARD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hpccard->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
}
@@ -215,7 +234,7 @@
* @}
*/
-/** @defgroup PCCARD_Group2 Input and Output functions
+/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -238,10 +257,10 @@
* @retval HAL status
*
*/
-HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -255,31 +274,31 @@
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- /* Initialize the CF status */
- *pStatus = CF_READY;
+ /* Initialize the PCCARD status */
+ *pStatus = PCCARD_READY;
/* Send the Identify Command */
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = 0xECEC;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
- /* Read CF IDs and timeout treatment */
+ /* Read PCCARD IDs and timeout treatment */
do
{
- /* Read the CF status */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* Read the PCCARD status */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
else
{
- /* Read CF ID bytes */
+ /* Read PCCARD ID bytes */
for(index = 0; index < 16; index++)
{
- CompactFlash_ID[index] = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_DATA);
+ CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
}
}
@@ -298,13 +317,13 @@
* the configuration information for PCCARD module.
* @param pBuffer: pointer to destination read buffer
* @param SectorAddress: Sector address to read
- * @param pStatus: pointer to CF status
+ * @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index = 0;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -318,44 +337,44 @@
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- /* Initialize CF status */
- *pStatus = CF_READY;
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0xE4A0;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
do
{
/* wait till the Status = 0x80 */
- status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status == 0x80) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
- timeout = 0xFFFF;
+ timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
do
{
- /* wait till the Status = 0x58 */
- status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Read bytes */
- for(; index < CF_SECTOR_SIZE; index++)
+ for(; index < PCCARD_SECTOR_SIZE; index++)
{
- *(uint16_t *)pBuffer++ = *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR);
+ *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
}
/* Update the PCCARD controller state */
@@ -374,13 +393,13 @@
* the configuration information for PCCARD module.
* @param pBuffer: pointer to source write buffer
* @param SectorAddress: Sector address to write
- * @param pStatus: pointer to CF status
+ * @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index = 0;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -394,42 +413,42 @@
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- /* Initialize CF status */
- *pStatus = CF_READY;
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0x30A0;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
{
- /* Wait till the Status = 0x58 */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* Wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Write bytes */
- for(; index < CF_SECTOR_SIZE; index++)
+ for(; index < PCCARD_SECTOR_SIZE; index++)
{
- *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
+ *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
}
do
{
- /* Wait till the Status = 0x50 */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x50) && timeout);
+ }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Update the PCCARD controller state */
@@ -447,13 +466,13 @@
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param SectorAddress: Sector address to erase
- * @param pStatus: pointer to CF status
+ * @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0x400;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -467,29 +486,29 @@
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- /* Initialize CF status */
- *pStatus = CF_READY;
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_LOW) = 0x00;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = 0x00;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_NUMBER) = SectorAddress;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = 0x01;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CARD_HEAD) = 0xA0;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = CF_ERASE_SECTOR_CMD;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
- /* wait till the CF is ready */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* wait till the PCCARD is ready */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- while((status != 0x50) && timeout)
+ while((status != PCCARD_STATUS_WRITE_OK) && timeout)
{
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Check the PCCARD controller state */
@@ -507,9 +526,8 @@
* the configuration information for PCCARD module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
{
-
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -519,17 +537,17 @@
return HAL_BUSY;
}
- /* Provide an SW reset and Read and verify the:
- - CF Configuration Option Register at address 0x98000200 --> 0x80
- - Card Configuration and Status Register at address 0x98000202 --> 0x00
- - Pin Replacement Register at address 0x98000204 --> 0x0C
+ /* Provide a SW reset and Read and verify the:
+ - PCCard Configuration Option Register at address 0x98000200 --> 0x80
+ - Card Configuration and Status Register at address 0x98000202 --> 0x00
+ - Pin Replacement Register at address 0x98000204 --> 0x0C
- Socket and Copy Register at address 0x98000206 --> 0x00
*/
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- *(__IO uint8_t *)(0x98000202) = 0x01;
+ *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01;
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
@@ -587,7 +605,6 @@
/* Clear PCCARD interrupt FIFO empty pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
}
-
}
/**
@@ -607,7 +624,7 @@
* @}
*/
-/** @defgroup PCCARD_Group4 State functions
+/** @defgroup PCCARD_Exported_Functions_Group3 State functions
* @brief Peripheral State functions
*
@verbatim
@@ -637,37 +654,36 @@
* @brief Get the compact flash memory status
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @retval New status of the CF operation. This parameter can be:
+ * @retval New status of the PCCARD operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
- * - CompactFlash_READY: when memory is ready for the next operation
- *
+ * - CompactFlash_READY: when memory is ready for the next operation
*/
-CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard)
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint32_t timeout = 0x1000000, status_CF;
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
{
- return CF_ONGOING;
+ return HAL_PCCARD_STATUS_ONGOING;
}
- status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- while((status_CF == CF_BUSY) && timeout)
+ while((status_pccard == PCCARD_BUSY) && timeout)
{
- status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if(timeout == 0)
{
- status_CF = CF_TIMEOUT_ERROR;
+ status_pccard = PCCARD_TIMEOUT_ERROR;
}
/* Return the operation status */
- return (CF_StatusTypedef) status_CF;
+ return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
@@ -677,31 +693,31 @@
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
* - CompactFlash_READY: when memory is ready for the next operation
- * - CompactFlash_ERROR: when the previous operation gererates error
+ * - CompactFlash_ERROR: when the previous operation generates error
*/
-CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard)
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint8_t data = 0, status_CF = CF_BUSY;
+ uint8_t data = 0, status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
{
- return CF_ONGOING;
+ return HAL_PCCARD_STATUS_ONGOING;
}
/* Read status operation */
- data = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- if((data & CF_TIMEOUT_ERROR) == CF_TIMEOUT_ERROR)
+ if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
{
- status_CF = CF_TIMEOUT_ERROR;
+ status_pccard = PCCARD_TIMEOUT_ERROR;
}
- else if((data & CF_READY) == CF_READY)
+ else if((data & PCCARD_READY) == PCCARD_READY)
{
- status_CF = CF_READY;
+ status_pccard = PCCARD_READY;
}
- return (CF_StatusTypedef) status_CF;
+ return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
@@ -711,8 +727,9 @@
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-#endif /* HAL_PCCARD_MODULE_ENABLED */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_PCCARD_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,11 +44,11 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#include "stm32f4xx_ll_fmc.h"
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
@@ -56,16 +56,20 @@
* @{
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
/** @addtogroup PCCARD
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
+ * @{
+ */
/**
- * @brief HAL SRAM State structures definition
+ * @brief HAL PCCARD State structures definition
*/
typedef enum
{
@@ -74,14 +78,14 @@
HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
}HAL_PCCARD_StateTypeDef;
-
+
typedef enum
{
- CF_SUCCESS = 0,
- CF_ONGOING,
- CF_ERROR,
- CF_TIMEOUT
-}CF_StatusTypedef;
+ HAL_PCCARD_STATUS_SUCCESS = 0,
+ HAL_PCCARD_STATUS_ONGOING,
+ HAL_PCCARD_STATUS_ERROR,
+ HAL_PCCARD_STATUS_TIMEOUT
+}HAL_PCCARD_StatusTypeDef;
/**
* @brief FMC_PCCARD handle Structure definition
@@ -97,81 +101,159 @@
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
}PCCARD_HandleTypeDef;
-
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Constants
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
* @{
*/
-
-#define CF_DEVICE_ADDRESS ((uint32_t)0x90000000)
-#define CF_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
-#define CF_COMMON_SPACE_ADDRESS CF_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
-#define CF_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
-#define CF_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ((uint8_t)0x00) /* Data register */
-#define CF_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
-#define CF_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
-#define CF_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
-#define CF_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
-#define CF_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
-#define CF_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
-#define CF_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
-#define CF_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ((uint8_t)0x20)
-#define CF_WRITE_SECTOR_CMD ((uint8_t)0x30)
-#define CF_ERASE_SECTOR_CMD ((uint8_t)0xC0)
-#define CF_IDENTIFY_CMD ((uint8_t)0xEC)
-
-/* Compact Flash status */
-#define CF_TIMEOUT_ERROR ((uint8_t)0x60)
-#define CF_BUSY ((uint8_t)0x80)
-#define CF_PROGR ((uint8_t)0x01)
-#define CF_READY ((uint8_t)0x40)
-
-#define CF_SECTOR_SIZE ((uint32_t)255) /* In half words */
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-
/** @brief Reset PCCARD handle state
* @param __HANDLE__: specifies the PCCARD handle.
* @retval None
*/
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-
-/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
-HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
-
-/* PCCARD State functions *******************************************************/
-HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
-CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard);
-CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard);
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCCARD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group3
+ * @{
+ */
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
+ * @{
+ */
+#define PCCARD_DEVICE_ADDRESS ((uint32_t)0x90000000)
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
+
+/* Flash-ATA registers description */
+#define ATA_DATA ((uint8_t)0x00) /* Data register */
+#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
+#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
+#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
+#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
+#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
+#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
+#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
+#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
+
+/* Flash-ATA commands */
+#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
+#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
+#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
+#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
+
+/* PC Card/Compact Flash status */
+#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
+#define PCCARD_BUSY ((uint8_t)0x80)
+#define PCCARD_PROGR ((uint8_t)0x01)
+#define PCCARD_READY ((uint8_t)0x40)
+
+#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */
+
+/**
+ * @}
+ */
+/* Compact Flash redefinition */
+#define HAL_CF_Init HAL_PCCARD_Init
+#define HAL_CF_DeInit HAL_PCCARD_DeInit
+#define HAL_CF_MspInit HAL_PCCARD_MspInit
+#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
+
+#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
+#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
+#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
+#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
+#define HAL_CF_Reset HAL_PCCARD_Reset
+#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
+#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
+
+#define HAL_CF_GetState HAL_PCCARD_GetState
+#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
+#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
+
+#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
+#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
+
+
+#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
+#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
+#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
+
+#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
+#define CF_BUSY PCCARD_BUSY
+#define CF_PROGR PCCARD_PROGR
+#define CF_READY PCCARD_READY
+
+#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
+
+/* Private macros ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -45,7 +45,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -79,31 +79,44 @@
* @{
*/
-/** @defgroup PCD
+/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup PCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
-/** @defgroup PCD_Group1 Initialization and de-initialization functions
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@@ -153,7 +166,7 @@
hpcd->IN_ep[i].is_in = 1;
hpcd->IN_ep[i].num = i;
hpcd->IN_ep[i].tx_fifo_num = i;
- /* Control until ep is actvated */
+ /* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0;
hpcd->IN_ep[i].xfer_buff = 0;
@@ -179,6 +192,14 @@
hpcd->State= HAL_PCD_STATE_READY;
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable == 1)
+ {
+ HAL_PCDEx_ActivateLPM(hpcd);
+ }
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+
USB_DevDisconnect (hpcd->Instance);
return HAL_OK;
}
@@ -217,7 +238,7 @@
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implenetd in the user file
+ the HAL_PCD_MspInit could be implemented in the user file
*/
}
@@ -229,7 +250,7 @@
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implenetd in the user file
+ the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
@@ -237,10 +258,10 @@
* @}
*/
-/** @defgroup PCD_Group2 IO operation functions
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@@ -276,7 +297,7 @@
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
USB_StopDevice(hpcd->Instance);
- USB_DevDisconnect (hpcd->Instance);
+ USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -425,12 +446,21 @@
/* Handle Resume Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
- /* Clear the Remote Wake-up Signaling */
+ /* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
- HAL_PCD_ResumeCallback(hpcd);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ if(hpcd->LPM_State == LPM_L1)
+ {
+ hpcd->LPM_State = LPM_L0;
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+ }
+ else
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+ {
+ HAL_PCD_ResumeCallback(hpcd);
+ }
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
@@ -444,8 +474,24 @@
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
-
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ /* Handle LPM Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+ if( hpcd->LPM_State == LPM_L0)
+ {
+ hpcd->LPM_State = LPM_L1;
+ hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+ }
+ else
+ {
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ }
+#endif /* USB_OTG_GLPMCFG_LPMEN */
/* Handle Reset Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
@@ -504,8 +550,7 @@
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
-
-
+
/* Handle RxQLevel Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
@@ -573,26 +618,28 @@
}
/**
- * @brief Data out stage callbacks
+ * @brief Data OUT stage callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Data IN stage callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
@@ -603,7 +650,7 @@
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
@@ -615,7 +662,7 @@
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
@@ -627,7 +674,7 @@
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
@@ -640,7 +687,7 @@
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
@@ -652,31 +699,33 @@
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO OUT callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
- * @brief Incomplete ISO IN callbacks
+ * @brief Incomplete ISO IN callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
@@ -688,7 +737,7 @@
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
@@ -700,18 +749,18 @@
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
}
/**
* @}
*/
-
-/** @defgroup PCD_Group3 Peripheral Control functions
- * @brief management functions
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
@@ -724,7 +773,7 @@
*/
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Connect the USB device
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -737,7 +786,7 @@
}
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Disconnect the USB device
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -766,7 +815,7 @@
* @brief Open and configure an endpoint
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packert size
+ * @param ep_mps: endpoint max packet size
* @param ep_type: endpoint type
* @retval HAL status
*/
@@ -845,7 +894,6 @@
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
-
USB_OTG_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
@@ -1019,43 +1067,43 @@
}
/**
- * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
+ * @brief HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling
* @param hpcd: PCD handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
- /* active Remote wakeup signaling */
+ /* Activate Remote wake-up signaling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
}
return HAL_OK;
}
/**
- * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
+ * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling
* @param hpcd: PCD handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- /* active Remote wakeup signaling */
- USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+ /* De-activate Remote wake-up signaling */
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
}
/**
* @}
*/
-/** @defgroup PCD_Group4 Peripheral State functions
- * @brief Peripheral State functions
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
@@ -1081,9 +1129,19 @@
*/
/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+ * @{
+ */
+
+/**
* @brief DCD_WriteEmptyTxFifo
* check FIFO for the next packet to be loaded
* @param hpcd: PCD handle
+ * @param epnum : endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,10 +55,13 @@
*/
/* Exported types ------------------------------------------------------------*/
-
- /**
- * @brief PCD State structures definition
- */
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
typedef enum
{
HAL_PCD_STATE_RESET = 0x00,
@@ -68,6 +71,16 @@
HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
+#ifdef USB_OTG_GLPMCFG_LPMEN
+/* Device LPM suspend state */
+typedef enum
+{
+ LPM_L0 = 0x00, /* on */
+ LPM_L1 = 0x01, /* LPM L1 sleep */
+ LPM_L2 = 0x02, /* suspend */
+ LPM_L3 = 0x03, /* off */
+}PCD_LPM_StateTypeDef;
+#endif /* USB_OTG_GLPMCFG_LPMEN */
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
@@ -78,23 +91,35 @@
*/
typedef struct
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- void *pData; /*!< Pointer to upper stack Handler */
-
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ uint32_t BESL;
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+ void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
-
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extension module */
+#include "stm32f4xx_hal_pcd_ex.h"
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-/** @defgroup PCD_Speed
+/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0
@@ -104,7 +129,7 @@
* @}
*/
- /** @defgroup PCD_PHY_Module
+/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1
@@ -112,28 +137,13 @@
/**
* @}
*/
-
-/** @defgroup PCD_Instance_definition
- * @{
- */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
- #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
- ((INSTANCE) == USB_OTG_HS))
-#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
- #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-#endif
/**
* @}
*/
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup PCD_Interrupt_Clock
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
@@ -146,85 +156,83 @@
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
-
+ ~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
+
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
+#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
+#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define USB_HS_EXTI_LINE_WAKEUP ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
-#define USB_FS_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
-
-
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_HS_EXTI_ENABLE_IT() EXTI->IMR |= (USB_HS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_HS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_HS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_HS_EXTI_GET_FLAG() EXTI->PR & (USB_HS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG() EXTI->PR = (USB_HS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_HS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP)
-
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP;)\
- EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= USB_HS_EXTI_LINE_WAKEUP
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_FS_EXTI_LINE_WAKEUP)
-
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT() EXTI->IMR |= USB_FS_EXTI_LINE_WAKEUP
-#define __HAL_USB_FS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_FS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_FS_EXTI_GET_FLAG() EXTI->PR & (USB_FS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG() EXTI->PR = USB_FS_EXTI_LINE_WAKEUP
-
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
-
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP)
-
-
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP
-
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_FS_EXTI_LINE_WAKEUP)
-
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
-/* Include PCD HAL Extension module */
-#include "stm32f4xx_hal_pcd_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-/* I/O operation functions *****************************************************/
- /* Non-Blocking mode: Interrupt */
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
@@ -240,8 +248,14 @@
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
-/* Peripheral Control functions ************************************************/
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
@@ -253,15 +267,42 @@
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
-/* Create an alias to keep compatibility with the old name */
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
-/* Peripheral State functions **************************************************/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/** @defgroup PCD_Instance_definition PCD Instance definition
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,29 +46,27 @@
* @{
*/
-/** @defgroup PCDEx
+/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
+#ifdef HAL_PCD_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PCDEx_Private_Functions
- * @{
- */
-
-
-/** @defgroup PCDEx_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
@@ -80,8 +78,10 @@
*/
/**
- * @brief Update FIFO configuration
+ * @brief Set Tx FIFO
* @param hpcd: PCD handle
+ * @param fifo: The number of Tx fifo
+ * @param size: Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
@@ -122,18 +122,63 @@
}
/**
- * @brief Update FIFO configuration
+ * @brief Set Rx FIFO
* @param hpcd: PCD handle
+ * @param size: Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
-
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
+#if defined(STM32F446xx)
+/**
+ * @brief HAL_PCDEx_ActivateLPM : active LPM Feature
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = ENABLE;
+ hpcd->LPM_State = LPM_L0;
+ USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCDEx_DeActivateLPM : de-active LPM feature
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = DISABLE;
+ USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer
+ * @param hpcd: PCD handle
+ * @param msg: LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+}
+#endif /* STM32F446xx */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,12 +53,31 @@
/** @addtogroup PCDEx
* @{
*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(STM32F446xx)
+typedef enum
+{
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+}PCD_LPM_MsgTypeDef;
+#endif /* STM32F446xx */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-
-/* Peripheral Extended functions *********************************************/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#if defined(STM32F446xx)
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+#endif /* STM32F446xx */
/**
* @}
@@ -68,6 +87,14 @@
* @}
*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -47,7 +47,7 @@
* @{
*/
-/** @defgroup PWR
+/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
@@ -56,16 +56,34 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWR_Private_Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_MODE_IT ((uint32_t)0x00010000)
+#define PVD_MODE_EVT ((uint32_t)0x00020000)
+#define PVD_RISING_EDGE ((uint32_t)0x00000001)
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Functions
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
-/** @defgroup PWR_Group1 Initialization and de-initialization functions
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -78,7 +96,7 @@
write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
- __PWR_CLK_ENABLE() macro.
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
@endverbatim
@@ -87,13 +105,12 @@
/**
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
- * @param None
* @retval None
*/
void HAL_PWR_DeInit(void)
{
- __PWR_FORCE_RESET();
- __PWR_RELEASE_RESET();
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
}
/**
@@ -101,7 +118,6 @@
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
- * @param None
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
@@ -114,7 +130,6 @@
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
- * @param None
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
@@ -126,7 +141,7 @@
* @}
*/
-/** @defgroup PWR_Group2 Peripheral Control functions
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
@@ -143,15 +158,16 @@
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
- __HAL_PVD_EXTI_ENABLE_IT() macro.
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
- *** WakeUp pin configuration ***
+ *** Wake-up pin configuration ***
================================
[..]
- (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
+ (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
forced in input pull-down configuration and is active on rising edges.
- (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
+ (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
+ Only for STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin 2 on PC.13
*** Low Power modes configuration ***
=====================================
@@ -186,9 +202,9 @@
are preserved.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption In Stop mode, FLASH can be powered off before
- entering the Stop mode using the HAL_PWR_EnableFlashPowerDown() function.
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
It can be switched on again by software after exiting the Stop mode using
- the HAL_PWR_DisableFlashPowerDown() function.
+ the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
@@ -214,18 +230,18 @@
(++) Entry:
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
(++) Exit:
- (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+ (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
- *** Auto-wakeup (AWU) from low-power mode ***
+ *** Auto-wake-up (AWU) from low-power mode ***
=============================================
[..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event or a time-stamp event, without depending on
- an external interrupt (Auto-wakeup mode).
+ Wake-up event, a tamper event or a time-stamp event, without depending on
+ an external interrupt (Auto-wake-up mode).
- (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+ (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
@@ -234,8 +250,8 @@
is necessary to configure the RTC to detect the tamper or time stamp event using the
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
- configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
+ configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
@@ -250,52 +266,47 @@
* detection level.
* @retval None
*/
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
- uint32_t tmpreg = 0;
-
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= ~ (uint32_t)PWR_CR_PLS;
-
/* Set PLS[7:5] bits according to PVDLevel value */
- tmpreg |= sConfigPVD->PVDLevel;
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Configure the EXTI 16 interrupt */
- if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_RISING))
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure interrupt mode */
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
- __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD);
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
- /* Clear the edge trigger for the EXTI Line 16 (PVD) */
- EXTI->RTSR &= ~EXTI_RTSR_TR16;
- EXTI->FTSR &= ~EXTI_FTSR_TR16;
- /* Configure the rising edge */
- if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_RISING))
+
+ /* Configure the edge */
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
- EXTI->RTSR |= PWR_EXTI_LINE_PVD;
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
- /* Configure the falling edge */
- if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_FALLING))
+
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
- EXTI->FTSR |= PWR_EXTI_LINE_PVD;
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}
/**
* @brief Enables the Power Voltage Detector(PVD).
- * @param None
* @retval None
*/
void HAL_PWR_EnablePVD(void)
@@ -305,7 +316,6 @@
/**
* @brief Disables the Power Voltage Detector(PVD).
- * @param None
* @retval None
*/
void HAL_PWR_DisablePVD(void)
@@ -314,31 +324,37 @@
}
/**
- * @brief Enables the WakeUp PINx functionality.
+ * @brief Enables the Wake-up PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2 only available in case of STM32F446xx devices
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)ENABLE;
+
+ /* Enable the wake up pin */
+ SET_BIT(PWR->CSR, WakeUpPinx);
}
/**
- * @brief Disables the WakeUp PINx functionality.
+ * @brief Disables the Wake-up PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2 only available in case of STM32F446xx devices
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)DISABLE;
+
+ /* Disable the wake up pin */
+ CLEAR_BIT(PWR->CSR, WakeUpPinx);
}
/**
@@ -367,6 +383,9 @@
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
@@ -385,7 +404,7 @@
/**
* @brief Enters Stop mode.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
+ * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
@@ -403,25 +422,15 @@
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
- uint32_t tmpreg = 0;
-
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
- /* Select the regulator state in Stop mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDS bits */
- tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
-
- /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
- tmpreg |= Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
+ /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
/* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
@@ -432,10 +441,12 @@
else
{
/* Request Wait For Event */
+ __SEV();
+ __WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
@@ -446,16 +457,15 @@
* Alarm out, or RTC clock calibration out.
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
* - WKUP pin 1 (PA0) if enabled.
- * @param None
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Select Standby mode */
- PWR->CR |= PWR_CR_PDDS;
-
+ SET_BIT(PWR->CR, PWR_CR_PDDS);
+
/* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
@@ -468,25 +478,23 @@
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_IRQHandler().
- * @param None
* @retval None
*/
void HAL_PWR_PVD_IRQHandler(void)
{
- /* Check PWR exti flag */
- if(__HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) != RESET)
+ /* Check PWR Exti flag */
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR Exti pending bit */
- __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD);
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}
/**
* @brief PWR PVD interrupt callback
- * @param None
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
@@ -497,6 +505,56 @@
}
/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enables CORTEX M4 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Disables CORTEX M4 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,11 @@
*/
/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
/**
* @brief PWR PVD configuration structure definition
*/
@@ -67,45 +72,25 @@
This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* Alias word address of PMODE bit */
-#define PMODE_BitNumber 0x0E
-#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PWR_WakeUp_Pins
- * @{
- */
-
-#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
-#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
/**
* @}
*/
-/** @defgroup PWR_PVD_detection_level
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+ * @{
+ */
+#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100)
+#define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
@@ -115,74 +100,55 @@
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
+ (Compare internally to VREFINT) */
/**
* @}
*/
-/** @defgroup PWR_PVD_Mode
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
-#define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
-#define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
- ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
- */
+ */
-/** @defgroup PWR_Regulator_state_in_STOP_mode
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
/**
* @}
*/
-/** @defgroup PWR_SLEEP_mode_entry
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
/**
* @}
*/
-/** @defgroup PWR_STOP_mode_entry
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
* @}
*/
-/** @defgroup PWR_Regulator_Voltage_Scale
- * @{
- */
-#define PWR_REGULATOR_VOLTAGE_SCALE1 ((uint32_t)0x0000C000)
-#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00008000)
-#define PWR_REGULATOR_VOLTAGE_SCALE3 ((uint32_t)0x00004000)
-#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
- ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
- ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
+/** @defgroup PWR_Flag PWR Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF
@@ -190,7 +156,6 @@
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
-
/**
* @}
*/
@@ -200,7 +165,28 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F17xx)
+/** @brief macros configure the main internal regulator output voltage.
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption when the device does
+ * not operate at the maximum frequency (refer to the datasheets for more details).
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
+ __IO uint32_t tmpreg; \
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
+ UNUSED(tmpreg); \
+ } while(0)
+#else
/** @brief macros configure the main internal regulator output voltage.
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
@@ -211,7 +197,14 @@
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
* @retval None
*/
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
+ __IO uint32_t tmpreg; \
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
/** @brief Check PWR flag is set or not.
* @param __FLAG__: specifies the flag to check.
@@ -244,65 +237,116 @@
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+ * @brief Enable the PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable the PVD EXTI Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
/**
- * @brief Enable the PVD Exti Line.
- * @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
-#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
/**
- * @brief Disable the PVD EXTI Line.
- * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
-#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/**
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
- * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
* @retval EXTI PVD Line Status.
*/
-#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
/**
* @brief Clear the PVD Exti flag.
- * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
* @retval None.
*/
-#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
+ * @brief Generates a Software interrupt on PVD EXTI line.
* @retval None
*/
-#define __HAL_PVD_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @}
+ */
/* Include PWR HAL Extension module */
#include "stm32f4xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
-
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
/* Initialization and de-initialization functions *****************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
+/**
+ * @}
+ */
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
/* Peripheral Control functions **********************************************/
/* PVD configuration */
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
@@ -315,9 +359,112 @@
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
+/* Power PVD IRQ Handler */
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
+/* Cortex System Control functions *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+ * @{
+ */
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_register_alias_address PWR Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+#define PWR_CR_OFFSET 0x00
+#define PWR_CSR_OFFSET 0x04
+#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
+#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address
+ * @{
+ */
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
+#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
+#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
+
+/* Alias word address of PMODE bit */
+#define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
+#define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
+ * @{
+ */
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+ * @{
+ */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_NORMAL))
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
* @{
*/
-/** @defgroup PWREx
+/** @defgroup PWREx PWREx
* @brief PWR HAL module driver
* @{
*/
@@ -55,19 +55,27 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Constants
+ * @{
+ */
#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
#define PWR_BKPREG_TIMEOUT_VALUE 1000
+#define PWR_VOSRDY_TIMEOUT_VALUE 1000
+/**
+ * @}
+ */
+
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWREx_Private_Functions
- * @{
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
*/
-/** @defgroup PWREx_Group1 Peripheral Extended features functions
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
* @brief Peripheral Extended features functions
*
@verbatim
@@ -83,7 +91,7 @@
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
retained even in Standby or VBAT mode when the low power backup regulator
is enabled. It can be considered as an internal EEPROM when VBAT is
- always present. You can use the HAL_PWR_EnableBkUpReg() function to
+ always present. You can use the HAL_PWREx_EnableBkUpReg() function to
enable the low power backup regulator.
(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
@@ -109,7 +117,7 @@
=======================================
[..]
(+) By setting the FPDS bit in the PWR_CR register by using the
- HAL_PWR_EnableFlashPowerDown() function, the Flash memory also enters power
+ HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
down mode when the device enters Stop mode. When the Flash memory
is in power down mode, an additional startup delay is incurred when
waking up from Stop mode.
@@ -148,7 +156,6 @@
/**
* @brief Enables the Backup Regulator.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
@@ -173,7 +180,6 @@
/**
* @brief Disables the Backup Regulator.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
@@ -198,7 +204,6 @@
/**
* @brief Enables the Flash Power Down in Stop mode.
- * @param None
* @retval None
*/
void HAL_PWREx_EnableFlashPowerDown(void)
@@ -208,7 +213,6 @@
/**
* @brief Disables the Flash Power Down in Stop mode.
- * @param None
* @retval None
*/
void HAL_PWREx_DisableFlashPowerDown(void)
@@ -216,11 +220,154 @@
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
}
+/**
+ * @brief Return Voltage Scaling Range.
+ * @retval The configured scale for the regulator voltage(VOS bit field).
+ * The returned value can be one of the following:
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+ */
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+ return (PWR->CR & PWR_CR_VOS);
+}
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/**
+ * @brief Configures the main internal regulator output voltage.
+ * @param VoltageScaling: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+ * the maximum value of fHCLK = 168 MHz.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+ * the maximum value of fHCLK = 144 MHz.
+ * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
+ * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
+ * When moving from Range 2 to Range 1, the system frequency can be increased to
+ * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+ uint32_t tickstart = 0;
+
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ /* Enable PWR RCC Clock Peripheral */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Set Range */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+/**
+ * @brief Configures the main internal regulator output voltage.
+ * @param VoltageScaling: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+ * the maximum value of fHCLK is 168 MHz. It can be extended to
+ * 180 MHz by activating the over-drive mode.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+ * the maximum value of fHCLK is 144 MHz. It can be extended to,
+ * 168 MHz by activating the over-drive mode.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
+ * the maximum value of fHCLK is 120 MHz.
+ * @note To update the system clock frequency(SYSCLK):
+ * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
+ * - Call the HAL_RCC_OscConfig() to configure the PLL.
+ * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
+ * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
+ * @note The scale can be modified only when the HSI or HSE clock source is selected
+ * as system clock source, otherwise the API returns HAL_ERROR.
+ * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
+ * value in the PWR_CR1 register are not taken in account.
+ * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
+ * @note The new voltage scale is active only when the PLL is ON.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+ uint32_t tickstart = 0;
+
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ /* Enable PWR RCC Clock Peripheral */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ {
+ /* Disable the main PLL */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set Range */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+
+ /* Enable the main PLL */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/**
* @brief Enables Main Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
- * @param None
* @retval None
*/
void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
@@ -231,7 +378,6 @@
/**
* @brief Disables Main Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
- * @param None
* @retval None
*/
void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
@@ -242,7 +388,6 @@
/**
* @brief Enables Low Power Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
- * @param None
* @retval None
*/
void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
@@ -253,7 +398,6 @@
/**
* @brief Disables Low Power Regulator low voltage mode.
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
- * @param None
* @retval None
*/
void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
@@ -263,7 +407,7 @@
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/**
* @brief Activates the Over-Drive mode.
* @note This function can be used only for STM32F42xx/STM32F43xx devices.
@@ -273,14 +417,13 @@
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
- * @param None
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void)
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
uint32_t tickstart = 0;
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
__HAL_PWR_OVERDRIVE_ENABLE();
@@ -321,14 +464,13 @@
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
- * @param None
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void)
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
{
uint32_t tickstart = 0;
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Disable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_DISABLE();
@@ -380,7 +522,7 @@
*
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
*
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
+ * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
* the HSI RC oscillator is selected as system clock.
*
* @note When the voltage regulator operates in low power mode, an additional
@@ -402,7 +544,7 @@
*/
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
uint32_t tickstart = 0;
/* Check the parameters */
@@ -410,7 +552,7 @@
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Enable Power ctrl clock */
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable the Under-drive Mode ---------------------------------------------*/
/* Clear Under-drive flag */
__HAL_PWR_CLEAR_ODRUDR_FLAG();
@@ -431,15 +573,15 @@
}
/* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
+ tmpreg1 = PWR->CR;
/* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
- tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
+ tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
- tmpreg |= Regulator;
+ tmpreg1 |= Regulator;
/* Store the new value */
- PWR->CR = tmpreg;
+ PWR->CR = tmpreg1;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@@ -461,7 +603,7 @@
return HAL_OK;
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,48 +56,22 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/* ------------- PWR registers bit address in the alias region ---------------*/
-/* --- CR Register ---*/
-/* Alias word address of FPDS bit */
-#define FPDS_BitNumber 0x09
-#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
-
-/* Alias word address of ODEN bit */
-#define ODEN_BitNumber 0x10
-#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
-/* Alias word address of ODSWEN bit */
-#define ODSWEN_BitNumber 0x11
-#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
-
-/* Alias word address of MRLVDS bit */
-#define MRLVDS_BitNumber 0x0B
-#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
-
-/* Alias word address of LPLVDS bit */
-#define LPLVDS_BitNumber 0x0A
-#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of BRE bit */
-#define BRE_BitNumber 0x09
-#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
-/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
* @{
*/
#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
-
-#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
/**
* @}
*/
-/** @defgroup PWREx_Over_Under_Drive_Flag
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
* @{
*/
#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
@@ -106,14 +80,34 @@
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F17xx)
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00000000) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
+ 180 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
+ 168 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+/**
+ * @}
+ */
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/** @brief Macros to enable or disable the Over drive mode.
* @note These macros can be used only for STM32F42xx/STM3243xx devices.
*/
@@ -158,13 +152,25 @@
*/
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void);
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1
+ * @{
+ */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
@@ -173,11 +179,99 @@
void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void);
-HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWREx Private Constants
+ * @{
+ */
+
+/** @defgroup PWREx_register_alias_address PWREx Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+/* Alias word address of FPDS bit */
+#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
+#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
+
+/* Alias word address of ODEN bit */
+#define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
+#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODEN_BIT_NUMBER * 4))
+
+/* Alias word address of ODSWEN bit */
+#define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
+#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODSWEN_BIT_NUMBER * 4))
+
+/* Alias word address of MRLVDS bit */
+#define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
+#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (MRLVDS_BIT_NUMBER * 4))
+
+/* Alias word address of LPLVDS bit */
+#define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
+#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPLVDS_BIT_NUMBER * 4))
+
+ /**
+ * @}
+ */
+
+/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
+ * @{
+ */
+/* --- CSR Register ---*/
+/* Alias word address of BRE bit */
+#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
+#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+ * @{
+ */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F17xx)
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#else
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,1942 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_qspi.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief QSPI HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the QuadSPI interface (QSPI).
+ * + Initialization and de-initialization functions
+ * + Indirect functional mode management
+ * + Memory-mapped functional mode management
+ * + Auto-polling functional mode management
+ * + Interrupts and flags management
+ * + DMA channel configuration for indirect functional mode
+ * + Errors management and abort functionality
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ *** Initialization ***
+ ======================
+ [..]
+ (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
+ (+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+ (+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+ (+) If interrupt mode is used, enable and configure QuadSPI global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (#) Configure the flash size, the clock prescaler, the fifo threshold, the
+ clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
+
+ *** Indirect functional mode ***
+ ================================
+ [..]
+ (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
+ functions :
+ (+) Instruction phase : the mode used and if present the instruction opcode.
+ (+) Address phase : the mode used and if present the size and the address value.
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used and if present the number of bytes.
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (#) If no data is required for the command, it is sent directly to the memory :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+ (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
+ HAL_QSPI_Transmit_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+ HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+ (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
+ HAL_QSPI_Receive_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+ HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+
+ *** Auto-polling functional mode ***
+ ====================================
+ [..]
+ (#) Configure the command sequence and the auto-polling functional mode using the
+ HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
+ (+) Instruction phase : the mode used and if present the instruction opcode.
+ (+) Address phase : the mode used and if present the size and the address value.
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used.
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+ the polling interval and the automatic stop activation.
+ (#) After the configuration :
+ (+) In polling mode, the output of the function is done when the status match is reached. The
+ automatic stop is activated to avoid an infinite loop.
+ (+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+ *** Memory-mapped functional mode ***
+ =====================================
+ [..]
+ (#) Configure the command sequence and the memory-mapped functional mode using the
+ HAL_QSPI_MemoryMapped() functions :
+ (+) Instruction phase : the mode used and if present the instruction opcode.
+ (+) Address phase : the mode used and the size.
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used.
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (+) The timeout activation and the timeout period.
+ (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
+ the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
+
+ *** Errors management and abort functionality ***
+ ==================================================
+ [..]
+ (#) HAL_QSPI_GetError() function gives the error rised during the last operation.
+ (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
+ (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
+
+ *** Workarounds linked to Silicon Limitation ***
+ ====================================================
+ [..]
+ (#) Workarounds Implemented inside HAL Driver
+ (+) Extra data written in the FIFO at the end of a read transfer
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup QSPI QSPI
+ * @brief HAL QSPI module driver
+ * @{
+ */
+#ifdef HAL_QSPI_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup QSPI_Private_Constants
+ * @{
+ */
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup QSPI_Private_Macros QSPI Private Macros
+ * @{
+ */
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
+ * @{
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Initialize the QuadSPI.
+ (+) De-initialize the QuadSPI.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the QSPI mode according to the specified parameters
+ * in the QSPI_InitTypeDef and creates the associated handle.
+ * @param hqspi: qspi handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the QSPI handle allocation */
+ if(hqspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
+ assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
+ assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
+ assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
+ assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
+ assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
+ assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
+ assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
+
+ if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
+ {
+ assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hqspi->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_QSPI_MspInit(hqspi);
+
+ /* Configure the default timeout for the QSPI memory access */
+ HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+ }
+
+ /* Configure QSPI FIFO Threshold */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if(status == HAL_OK)
+ {
+
+ /* Configure QSPI Clock Prescaler and Sample Shift */
+ MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
+
+ /* Configure QSPI Flash Size, CS High Time and Clock Mode */
+ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+ ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
+ /* Enable the QSPI peripheral */
+ __HAL_QSPI_ENABLE(hqspi);
+
+ /* Set QSPI error code to none */
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Initialize the QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DeInitializes the QSPI peripheral
+ * @param hqspi: qspi handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* Check the QSPI handle allocation */
+ if(hqspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ /* Disable the QSPI Peripheral Clock */
+ __HAL_QSPI_DISABLE(hqspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_QSPI_MspDeInit(hqspi);
+
+ /* Set QSPI error code to none */
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Initialize the QSPI state */
+ hqspi->State = HAL_QSPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief QSPI MSP Init
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_QSPI_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief QSPI MSP DeInit
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_QSPI_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
+ * @brief QSPI Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### I/O operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Handle the interrupts.
+ (+) Handle the command sequence.
+ (+) Transmit data in blocking, interrupt or DMA mode.
+ (+) Receive data in blocking, interrupt or DMA mode.
+ (+) Manage the auto-polling functional mode.
+ (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles QSPI interrupt request.
+ * @param hqspi: QSPI handle
+ * @retval None.
+ */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
+{
+ __IO uint32_t *data_reg;
+ uint32_t flag = 0, itsource = 0;
+
+ /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ data_reg = &hqspi->Instance->DR;
+
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ {
+ /* Transmission process */
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+ {
+ if (hqspi->TxXferCount > 0)
+ {
+ /* Fill the FIFO until it is full */
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ hqspi->TxXferCount--;
+ }
+ else
+ {
+ /* No more data available for the transfer */
+ break;
+ }
+ }
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ {
+ /* Receiving Process */
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+ {
+ if (hqspi->RxXferCount > 0)
+ {
+ /* Read the FIFO until it is empty */
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+ else
+ {
+ /* All data have been received for the transfer */
+ break;
+ }
+ }
+ }
+
+ /* FIFO Threshold callback */
+ HAL_QSPI_FifoThresholdCallback(hqspi);
+ }
+
+ /* QSPI Transfer Complete interrupt occurred -------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+ /* Transfer complete callback */
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ {
+ /* Clear Busy bit */
+ HAL_QSPI_Abort(hqspi);
+
+ /* TX Complete callback */
+ HAL_QSPI_TxCpltCallback(hqspi);
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ {
+ data_reg = &hqspi->Instance->DR;
+ while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
+ {
+ if (hqspi->RxXferCount > 0)
+ {
+ /* Read the last data received in the FIFO until it is empty */
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+ else
+ {
+ /* All data have been received for the transfer */
+ break;
+ }
+ }
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ HAL_QSPI_Abort(hqspi);
+
+ /* RX Complete callback */
+ HAL_QSPI_RxCpltCallback(hqspi);
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY)
+ {
+ /* Command Complete callback */
+ HAL_QSPI_CmdCpltCallback(hqspi);
+ }
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* QSPI Status Match interrupt occurred ------------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+
+ /* Check if the automatic poll mode stop is activated */
+ if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
+ {
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* Status match callback */
+ HAL_QSPI_StatusMatchCallback(hqspi);
+ }
+
+ /* QSPI Transfer Error interrupt occurred ----------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
+
+ /* Disable all the QSPI Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+ /* Set error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+
+ /* Error callback */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+
+ /* QSPI Time out interrupt occurred -----------------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
+
+ /* Time out callback */
+ HAL_QSPI_TimeOutCallback(hqspi);
+ }
+}
+
+/**
+ * @brief Sets the command configuration.
+ * @param hqspi: QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param Timeout : Time out duration
+ * @note This function is used only in Indirect Read or Write Modes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ if (cmd->DataMode == QSPI_DATA_NONE)
+ {
+ /* When there is no data phase, the transfer start as soon as the configuration is done
+ so wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ }
+ else
+ {
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Sets the command configuration in interrupt mode.
+ * @param hqspi: QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @note This function is used only in Indirect Read or Write Modes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ if (cmd->DataMode == QSPI_DATA_NONE)
+ {
+ /* When there is no data phase, the transfer start as soon as the configuration is done
+ so activate TC and TE interrupts */
+ /* Enable the QSPI Transfer Error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+ }
+
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ if (cmd->DataMode != QSPI_DATA_NONE)
+ {
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @param Timeout : Time out duration
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ while(hqspi->TxXferCount > 0)
+ {
+ /* Wait until FT flag is set to send data */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ hqspi->TxXferCount--;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Clear Busy bit */
+ status = HAL_QSPI_Abort(hqspi);
+ }
+ }
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @param Timeout : Time out duration
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ while(hqspi->RxXferCount > 0)
+ {
+ /* Wait until FT or TC flag is set to read received data */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ status = HAL_QSPI_Abort(hqspi);
+ }
+ }
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Receive an amount of data in no-blocking mode with Interrupt
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode with DMA.
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional mode as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
+
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Enable the QSPI transmit DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_OK;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode with DMA.
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer.
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
+
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Enable the DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information.
+ * @param cfg: structure that contains the polling configuration information.
+ * @param Timeout : Time out duration
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: PSMAR register with the status match value */
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+ /* Configure QSPI: PSMKR register with the status mask value */
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+ /* Configure QSPI: PIR register with the interval value */
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop enabled
+ (otherwise there will be an infinite loop in blocking mode) */
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+
+ /* Call the configuration function */
+ cmd->NbData = cfg->StatusBytesSize;
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+ /* Wait until SM flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information.
+ * @param cfg: structure that contains the polling configuration information.
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: PSMAR register with the status match value */
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+ /* Configure QSPI: PSMKR register with the status mask value */
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+ /* Configure QSPI: PIR register with the interval value */
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop mode */
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ (cfg->MatchMode | cfg->AutomaticStop));
+
+ /* Call the configuration function */
+ cmd->NbData = cfg->StatusBytesSize;
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+ /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE));
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the Memory Mapped mode.
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information.
+ * @param cfg: structure that contains the memory mapped configuration information.
+ * @note This function is used only in Memory mapped Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: CR register with time out counter enable */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+
+ if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+ {
+ assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+
+ /* Configure QSPI: LPTR register with the low-power time out value */
+ WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
+
+ /* Enable the QSPI TimeOut Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
+ }
+
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
+
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transfer Error callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Command completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_CmdCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FIFO Threshold callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Status Match callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_StatusMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timeout callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TimeOutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
+ * @brief QSPI control and State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control and State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Check in run-time the state of the driver.
+ (+) Check the error code set during last operation.
+ (+) Abort any operation.
+.....
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the QSPI state.
+ * @param hqspi: QSPI handle
+ * @retval HAL state
+ */
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+{
+ return hqspi->State;
+}
+
+/**
+* @brief Return the QSPI error code
+* @param hqspi: QSPI handle
+* @retval QSPI Error Code
+*/
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+{
+ return hqspi->ErrorCode;
+}
+
+/**
+* @brief Abort the current transmission
+* @param hqspi: QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Configure QSPI: CR register with Abort request */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+
+ /* Wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Wait until BUSY flag is reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ return status;
+}
+
+/** @brief Set QSPI timeout
+ * @param hqspi: QSPI handle.
+ * @param Timeout: Timeout for the QSPI memory access.
+ * @retval None
+ */
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+ hqspi->Timeout = Timeout;
+}
+
+/**
+* @}
+*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief DMA QSPI receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hqspi->RxXferCount = 0;
+
+ /* Wait for QSPI TC Flag */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
+ {
+ /* Time out Occurred */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+ else
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ HAL_QSPI_Abort(hqspi);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ HAL_QSPI_RxCpltCallback(hqspi);
+ }
+}
+
+/**
+ * @brief DMA QSPI transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hqspi->TxXferCount = 0;
+
+ /* Wait for QSPI TC Flag */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
+ {
+ /* Time out Occurred */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+ else
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Clear Busy bit */
+ HAL_QSPI_Abort(hqspi);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ HAL_QSPI_TxCpltCallback(hqspi);
+ }
+}
+
+/**
+ * @brief DMA QSPI receive process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_QSPI_RxHalfCpltCallback(hqspi);
+}
+
+/**
+ * @brief DMA QSPI transmit process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_QSPI_TxHalfCpltCallback(hqspi);
+}
+
+/**
+ * @brief DMA QSPI communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hqspi->RxXferCount = 0;
+ hqspi->TxXferCount = 0;
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+ HAL_QSPI_ErrorCallback(hqspi);
+}
+
+/**
+ * @brief This function wait a flag state until time out.
+ * @param hqspi: QSPI handle
+ * @param Flag: Flag checked
+ * @param State: Value of the flag expected
+ * @param Timeout: Duration of the time out
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+ FlagStatus State, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is in expected state */
+ while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function configures the communication registers
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information
+ * @param FunctionalMode: functional mode to configured
+ * This parameter can be one of the following values:
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
+ * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
+ * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
+ * @retval None
+ */
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
+{
+ assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
+
+ if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+ {
+ /* Configure QSPI: DLR register with the number of data to read or write */
+ WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
+ }
+
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ /* Configure QSPI: ABR register with alternate bytes value */
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with instruction, address and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with instruction and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
+ }
+ }
+ else
+ {
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with instruction and address ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only instruction ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
+ FunctionalMode));
+ }
+ }
+ }
+ else
+ {
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ /* Configure QSPI: ABR register with alternate bytes value */
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with address and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ FunctionalMode));
+ }
+ }
+ else
+ {
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with only address ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only data phase ----*/
+ if (cmd->DataMode != QSPI_DATA_NONE)
+ {
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+ }
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#endif /* HAL_QSPI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,788 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_qspi.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Header file of QSPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_QSPI_H
+#define __STM32F4xx_HAL_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup QSPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Types QSPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief QSPI Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
+ This parameter can be a value between 1 and 32 */
+
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+ take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
+ This parameter can be a value of @ref QSPI_SampleShifting */
+
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+ required to address the flash memory. The flash capacity can be up to 4GB
+ (addressed using 32 bits) in indirect mode, but the addressable space in
+ memory-mapped mode is limited to 256MB
+ This parameter can be a number between 0 and 31 */
+
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+ of clock cycles which the chip select must remain high between commands.
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */
+
+ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
+ This parameter can be a value of @ref QSPI_ClockMode */
+
+ uint32_t FlashID; /* Specifies the Flash which will be used,
+ This parameter can be a value of @ref QSPI_Flash_Select */
+
+ uint32_t DualFlash; /* Specifies the Dual Flash Mode State
+ This parameter can be a value of @ref QSPI_DualFlash_Mode */
+}QSPI_InitTypeDef;
+
+/**
+ * @brief HAL QSPI State structures definition
+ */
+typedef enum
+{
+ HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
+ HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
+ HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
+ HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
+ HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
+ HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
+ HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
+ HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
+}HAL_QSPI_StateTypeDef;
+
+/**
+ * @brief QSPI Handle Structure definition
+ */
+typedef struct
+{
+ QUADSPI_TypeDef *Instance; /* QSPI registers base address */
+ QSPI_InitTypeDef Init; /* QSPI communication parameters */
+ uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
+ __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
+ __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
+ uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
+ __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
+ __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
+ DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
+ __IO HAL_LockTypeDef Lock; /* Locking object */
+ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
+ __IO uint32_t ErrorCode; /* QSPI Error code */
+ uint32_t Timeout; /* Timeout for the QSPI memory access */
+}QSPI_HandleTypeDef;
+
+/**
+ * @brief QSPI Command structure definition
+ */
+typedef struct
+{
+ uint32_t Instruction; /* Specifies the Instruction to be sent
+ This parameter can be a value (8-bit) between 0x00 and 0xFF */
+ uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+ uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+ uint32_t AddressSize; /* Specifies the Address Size
+ This parameter can be a value of @ref QSPI_AddressSize */
+ uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
+ This parameter can be a value of @ref QSPI_AlternateBytesSize */
+ uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
+ This parameter can be a number between 0 and 31 */
+ uint32_t InstructionMode; /* Specifies the Instruction Mode
+ This parameter can be a value of @ref QSPI_InstructionMode */
+ uint32_t AddressMode; /* Specifies the Address Mode
+ This parameter can be a value of @ref QSPI_AddressMode */
+ uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
+ This parameter can be a value of @ref QSPI_AlternateBytesMode */
+ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
+ This parameter can be a value of @ref QSPI_DataMode */
+ uint32_t NbData; /* Specifies the number of data to transfer.
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
+ until end of memory)*/
+ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
+ This parameter can be a value of @ref QSPI_DdrMode */
+ uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
+ system clock in DDR mode.
+ This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode
+ This parameter can be a value of @ref QSPI_SIOOMode */
+}QSPI_CommandTypeDef;
+
+/**
+ * @brief QSPI Auto Polling mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
+ This parameter can be any value between 0 and 0xFFFF */
+ uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
+ This parameter can be any value between 1 and 4 */
+ uint32_t MatchMode; /* Specifies the method used for determining a match.
+ This parameter can be a value of @ref QSPI_MatchMode */
+ uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
+ This parameter can be a value of @ref QSPI_AutomaticStop */
+}QSPI_AutoPollingTypeDef;
+
+/**
+ * @brief QSPI Memory Mapped mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
+ uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ This parameter can be a value of @ref QSPI_TimeOutActivation */
+}QSPI_MemoryMappedTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
+ * @{
+ */
+/** @defgroup QSPI_ErrorCode QSPI Error Code
+ * @{
+ */
+#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
+ * @{
+ */
+#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
+ * @{
+ */
+#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_ClockMode QSPI Clock Mode
+ * @{
+ */
+#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Flash_Select QSPI Flash Select
+ * @{
+ */
+#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
+#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
+/**
+ * @}
+ */
+
+ /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+ * @{
+ */
+#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
+#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AddressSize QSPI Address Size
+ * @{
+ */
+#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
+#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
+#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
+#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
+ * @{
+ */
+#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
+* @{
+*/
+#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
+#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
+#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
+#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AddressMode QSPI Address Mode
+* @{
+*/
+#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
+#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
+#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
+#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
+*/
+#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
+#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
+#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DataMode QSPI Data Mode
+ * @{
+ */
+#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
+#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
+#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
+#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DdrMode QSPI Ddr Mode
+ * @{
+ */
+#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
+ * @{
+ */
+#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
+ * @{
+ */
+#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_MatchMode QSPI Match Mode
+ * @{
+ */
+#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
+ * @{
+ */
+#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
+ * @{
+ */
+#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Flags QSPI Flags
+ * @{
+ */
+#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+ * @{
+ */
+#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+ * @{
+ */
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset QSPI handle state
+ * @param __HANDLE__: QSPI handle.
+ * @retval None
+ */
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+
+/** @brief Enable QSPI
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @retval None
+ */
+#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief Disable QSPI
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @retval None
+ */
+#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief Enables the specified QSPI interrupt.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief Disables the specified QSPI interrupt.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief Checks whether the specified QSPI interrupt source is enabled.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Get the selected QSPI's flag status.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __FLAG__: specifies the QSPI flag to check.
+ * This parameter can be one of the following values:
+ * @arg QSPI_FLAG_BUSY: QSPI Busy flag
+ * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_SM: QSPI Status match flag
+ * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
+
+/** @brief Clears the specified QSPI's flag status.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
+ * This parameter can be one of the following values:
+ * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_SM: QSPI Status match flag
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup QSPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+/* QSPI IRQ handler method */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+
+/* QSPI status flag polling mode */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
+
+/* QSPI memory-mapped mode */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group3
+ * @{
+ */
+/* Callback functions in non-blocking modes ***********************************/
+void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI status flag polling mode */
+void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI memory-mapped mode */
+void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup QSPI_Private_Constants QSPI Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+ * @{
+ */
+/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
+ * @{
+ */
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
+ * @{
+ */
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
+/**
+ * @}
+ */
+
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+/** @defgroup QSPI_FlashSize QSPI Flash Size
+ * @{
+ */
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
+/**
+ * @}
+ */
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
+ ((FLA) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+ ((MODE) == QSPI_DUALFLASH_DISABLE))
+
+
+/** @defgroup QSPI_Instruction QSPI Instruction
+ * @{
+ */
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
+/**
+ * @}
+ */
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+
+/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
+ * @{
+ */
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
+/**
+ * @}
+ */
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+ ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \
+ ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
+ ((MODE) == QSPI_DATA_1_LINE) || \
+ ((MODE) == QSPI_DATA_2_LINES) || \
+ ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+/** @defgroup QSPI_Interval QSPI Interval
+ * @{
+ */
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
+ * @{
+ */
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
+/**
+ * @}
+ */
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
+ ((MODE) == QSPI_MATCH_MODE_OR))
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
+ * @{
+ */
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
+/**
+ * @}
+ */
+
+#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
+ ((FLAG) == QSPI_FLAG_TO) || \
+ ((FLAG) == QSPI_FLAG_SM) || \
+ ((FLAG) == QSPI_FLAG_FT) || \
+ ((FLAG) == QSPI_FLAG_TC) || \
+ ((FLAG) == QSPI_FLAG_TE))
+
+#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_QSPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -35,11 +35,30 @@
(+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+ after the clock enable bit is set on the hardware register
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+ after the clock enable bit is set on the hardware register
+
+ [..]
+ Possible Workarounds:
+ (#) Enable the peripheral clock sometimes before the peripheral read/write
+ register is required.
+ (#) For AHB peripheral, insert two dummy read to the peripheral register.
+ (#) For APB peripheral, insert a dummy read to the peripheral register.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -73,7 +92,7 @@
* @{
*/
-/** @defgroup RCC
+/** @defgroup RCC RCC
* @brief RCC HAL module driver
* @{
*/
@@ -82,32 +101,40 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
/* Private macro -------------------------------------------------------------*/
-#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
+#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define MCO1_GPIO_PORT GPIOA
#define MCO1_PIN GPIO_PIN_8
-#define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
+#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define MCO2_GPIO_PORT GPIOC
#define MCO2_PIN GPIO_PIN_9
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Functions
- * @{
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
*/
-/** @defgroup RCC_Group1 Initialization and de-initialization functions
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -138,7 +165,7 @@
(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
and if a HSE clock failure occurs(HSE used directly or through PLL as System
- clock source), the System clockis automatically switched to HSI and an interrupt
+ clock source), the System clocks automatically switched to HSI and an interrupt
is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
(Non-Maskable Interrupt) exception vector.
@@ -202,7 +229,6 @@
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
- * @param None
* @retval None
*/
void HAL_RCC_DeInit(void)
@@ -239,9 +265,9 @@
* @note The PLL is not disabled when used as system clock.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
@@ -251,9 +277,10 @@
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@@ -279,7 +306,7 @@
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
- if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
+ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
@@ -316,8 +343,9 @@
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
@@ -422,7 +450,7 @@
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Enable Power Clock*/
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
@@ -432,7 +460,7 @@
while((PWR->CR & PWR_CR_DBP) == RESET)
{
- if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -447,7 +475,7 @@
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -456,7 +484,7 @@
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
@@ -464,7 +492,7 @@
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -478,7 +506,7 @@
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
- if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -501,7 +529,7 @@
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
@@ -518,11 +546,11 @@
}
/* Configure the main PLL clock source, multiplication and division factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
+ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
+ RCC_OscInitStruct->PLL.PLLM | \
+ (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+ (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
@@ -636,7 +664,8 @@
}
}
/* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@@ -653,14 +682,14 @@
return HAL_ERROR;
}
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -670,7 +699,17 @@
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -680,7 +719,7 @@
}
else
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -715,7 +754,8 @@
}
}
/* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@@ -732,14 +772,13 @@
return HAL_ERROR;
}
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -749,7 +788,17 @@
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -759,7 +808,7 @@
}
else
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -804,7 +853,7 @@
* @}
*/
-/** @defgroup RCC_Group2 Peripheral Control functions
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
*
@verbatim
@@ -859,7 +908,7 @@
/* MCO1 Clock Enable */
__MCO1_CLK_ENABLE();
- /* Configue the MCO1 pin in alternate function mode */
+ /* Configure the MCO1 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO1_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
@@ -877,7 +926,7 @@
/* MCO2 Clock Enable */
__MCO2_CLK_ENABLE();
- /* Configue the MCO2 pin in alternate function mode */
+ /* Configure the MCO2 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO2_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
@@ -897,22 +946,20 @@
* software about the failure (Clock Security System Interrupt, CSSI),
* allowing the MCU to perform rescue operations. The CSSI is linked to
* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @param None
* @retval None
*/
void HAL_RCC_EnableCSS(void)
{
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables the Clock Security System.
- * @param None
* @retval None
*/
void HAL_RCC_DisableCSS(void)
{
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
}
/**
@@ -943,10 +990,9 @@
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
*
- * @param None
* @retval SYSCLK frequency
*/
-uint32_t HAL_RCC_GetSysClockFreq(void)
+__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
uint32_t pllm = 0, pllvco = 0, pllp = 0;
uint32_t sysclockfreq = 0;
@@ -969,7 +1015,7 @@
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- if (__RCC_PLLSRC() != 0)
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
@@ -1000,7 +1046,6 @@
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
- * @param None
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
@@ -1013,7 +1058,6 @@
* @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @param None
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
@@ -1026,7 +1070,6 @@
* @brief Returns the PCLK2 frequency
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @param None
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
@@ -1042,7 +1085,7 @@
* will be configured.
* @retval None
*/
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
@@ -1116,7 +1159,7 @@
/**
* @brief Configures the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
* will be configured.
* @param pFLatency: Pointer on the Flash Latency.
* @retval None
@@ -1145,7 +1188,6 @@
/**
* @brief This function handles the RCC CSS interrupt request.
* @note This API should be called under the NMI_Handler().
- * @param None
* @retval None
*/
void HAL_RCC_NMI_IRQHandler(void)
@@ -1154,7 +1196,7 @@
if(__HAL_RCC_GET_IT(RCC_IT_CSS))
{
/* RCC Clock Security System interrupt user callback */
- HAL_RCC_CCSCallback();
+ HAL_RCC_CSSCallback();
/* Clear RCC CSS pending bit */
__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
@@ -1163,13 +1205,12 @@
/**
* @brief RCC Clock Security System interrupt callback
- * @param none
- * @retval none
+ * @retval None
*/
-__weak void HAL_RCC_CCSCallback(void)
+__weak void HAL_RCC_CSSCallback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RCC_CCSCallback could be implemented in the user file
+ the HAL_RCC_CSSCallback could be implemented in the user file
*/
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,41 +46,23 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+/* Include RCC HAL Extended module */
+/* (include on top of file since RCC structures are defined in extended file) */
+#include "stm32f4xx_hal_rcc_ex.h"
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @addtogroup RCC
+/** @addtogroup RCC
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief RCC PLL configuration structure definition
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
*/
-typedef struct
-{
- uint32_t PLLState; /*!< The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
- This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
-
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
-
- uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-
- uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
- This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
-
-}RCC_PLLInitTypeDef;
-
+
/**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
@@ -130,72 +112,16 @@
}RCC_ClkInitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_BitAddress_AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BitNumber 0x1A
-#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-/* BDCR register base address */
-#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
-
-
-#define DBP_TIMEOUT_VALUE ((uint32_t)100)
-#define LSE_TIMEOUT_VALUE ((uint32_t)5000)
/**
* @}
*/
-/** @defgroup RCC_Oscillator_Type
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
@@ -203,73 +129,59 @@
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
-
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
/**
* @}
*/
-/** @defgroup RCC_HSE_Config
+/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_BYPASS ((uint8_t)0x05)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_BYPASS))
/**
* @}
*/
-/** @defgroup RCC_LSE_Config
+/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_BYPASS ((uint8_t)0x05)
-
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_BYPASS))
/**
* @}
*/
-/** @defgroup RCC_HSI_Config
+/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint8_t)0x00)
#define RCC_HSI_ON ((uint8_t)0x01)
-
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
/**
* @}
*/
-/** @defgroup RCC_LSI_Config
+/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
#define RCC_LSI_OFF ((uint8_t)0x00)
#define RCC_LSI_ON ((uint8_t)0x01)
-
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
/**
* @}
*/
-/** @defgroup RCC_PLL_Config
+/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
#define RCC_PLL_NONE ((uint8_t)0x00)
#define RCC_PLL_OFF ((uint8_t)0x01)
#define RCC_PLL_ON ((uint8_t)0x02)
-
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
/**
* @}
*/
-/** @defgroup RCC_PLLP_Clock_Divider
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
@@ -280,54 +192,49 @@
* @}
*/
-/** @defgroup RCC_PLL_Clock_Source
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-
/**
* @}
*/
-/** @defgroup RCC_System_Clock_Type
+/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
-
-#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
/**
* @}
*/
-/** @defgroup RCC_System_Clock_Source
+/** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
/**
* @}
- */
+ */
-/** @defgroup RCC_AHB_Clock_Source
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
* @{
*/
#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
@@ -339,17 +246,11 @@
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
-
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
- ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
- ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
- ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
- ((HCLK) == RCC_SYSCLK_DIV512))
/**
* @}
*/
-/** @defgroup RCC_APB1_APB2_Clock_Source
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
* @{
*/
#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
@@ -357,15 +258,11 @@
#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
-
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
- ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
- ((PCLK) == RCC_HCLK_DIV16))
/**
* @}
*/
-/** @defgroup RCC_RTC_Clock_Source
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
@@ -404,7 +301,7 @@
* @}
*/
-/** @defgroup RCC_I2S_Clock_Source
+/** @defgroup RCC_I2S_Clock_Source I2S Clock Source
* @{
*/
#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
@@ -413,46 +310,38 @@
* @}
*/
-/** @defgroup RCC_MCO_Index
+/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
#define RCC_MCO1 ((uint32_t)0x00000000)
#define RCC_MCO2 ((uint32_t)0x00000001)
-
-#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
/**
* @}
*/
-/** @defgroup RCC_MCO1_Clock_Source
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
-
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
/**
* @}
*/
-/** @defgroup RCC_MCO2_Clock_Source
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
* @{
*/
#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
-
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
- ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
/**
* @}
*/
-/** @defgroup RCC_MCOx_Clock_Prescaler
+/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
* @{
*/
#define RCC_MCODIV_1 ((uint32_t)0x00000000)
@@ -460,15 +349,11 @@
#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
- ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
- ((DIV) == RCC_MCODIV_5))
/**
* @}
*/
-/** @defgroup RCC_Interrupt
+/** @defgroup RCC_Interrupt Interrupts
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
@@ -482,7 +367,7 @@
* @}
*/
-/** @defgroup RCC_Flag
+/** @defgroup RCC_Flag Flags
* Elements values convention: 0XXYYYYYb
* - YYYYY : Flag position in the register
* - 0XX : Register index
@@ -509,346 +394,610 @@
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
-
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
/**
* @}
- */
+ */
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
-/** @brief Enable or disable the AHB1 peripheral clock.
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
-#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
-#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
-#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
-#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
-#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
-#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
-#define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
-#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
-#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
-#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
-#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
-#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
-#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
-#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
-#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
-#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
-/** @brief Enable or disable the AHB2 peripheral clock.
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
- __SYSCFG_CLK_ENABLE();\
- }while(0)
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0)
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_DISABLE();\
+ }while(0)
-#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
- __SYSCFG_CLK_DISABLE();\
- }while(0)
+#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-#define __RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
-#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
-#define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
-#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
-#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
-#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+/**
+ * @}
+ */
-#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
-#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
-#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
-#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
-#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
-#define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
-#define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
-#define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
-#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+/**
+ * @}
+ */
-/** @brief Force or release AHB1 peripheral reset.
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
*/
-#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
-#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
-#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
-#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
-#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
-#define __CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
-#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-
-#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
-#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
-#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
-#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
-#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
-#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
-#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
-
-/** @brief Force or release AHB2 peripheral reset.
- */
-#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
-#define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
-#define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-/* alias define maintained for legacy */
-#define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET
-
-#define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+/**
+ * @}
+ */
-/** @brief Force or release APB1 peripheral reset.
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
*/
-#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
-#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+/**
+ * @}
+ */
-/** @brief Force or release APB2 peripheral reset.
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
*/
-#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
-#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
-#define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
-#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
-#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+/**
+ * @}
+ */
-/** @brief Force or release AHB3 peripheral reset.
- */
-#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
-#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+/**
+ * @}
+ */
-/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
-#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
-#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
-#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
-#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
-#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
-#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
-#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
-#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
-#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
-#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
-#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-/* alias define maintained for legacy */
-#define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+/**
+ * @}
+ */
-#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
-#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
-#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
-#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
-#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+/**
+ * @}
+ */
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
* It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
* of the HSE used directly or indirectly as system clock (if the Clock
* Security System CSS is enabled).
* @note HSI can not be stopped if it is used as system clock source. In this case,
@@ -860,8 +1009,8 @@
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
* clock cycles.
*/
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
@@ -871,6 +1020,13 @@
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+ * @{
+ */
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
@@ -880,11 +1036,20 @@
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
* clock cycles.
*/
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+ * @{
+ */
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
+ * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
@@ -902,10 +1067,19 @@
* @arg RCC_HSE_ON: turn ON the HSE oscillator.
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
*/
-#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
+#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+ * @{
+ */
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
@@ -920,13 +1094,21 @@
* @arg RCC_LSE_ON: turn ON the LSE oscillator.
* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
*/
-#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
+#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
+
+/**
+ * @}
+ */
-/** @brief Macros to enable or disable the the RTC clock.
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the RTC clock.
* @note These macros must be used only after the RTC clock source was selected.
*/
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
/** @brief Macros to configure the RTC clock (RTCCLK).
* @note As the RTC clock configuration bits are in the Backup domain and write
@@ -943,7 +1125,7 @@
* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
* as RTC clock, where x:[2,31]
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * work in STOP and STANDBY modes, and can be used as wake-up source.
* However, when the HSE clock is used as RTC clock source, the RTC
* cannot be used in STOP and STANDBY modes.
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
@@ -961,8 +1143,15 @@
* and the RTC clock source selection in RCC_CSR register.
* @note The BKPSRAM is not affected by this reset.
*/
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
/** @brief Macros to enable or disable the main PLL.
* @note After enabling the main PLL, the application software should wait on
@@ -971,78 +1160,67 @@
* @note The main PLL can not be disabled if it is used as system clock source
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
*/
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+/**
+ * @}
+ */
-/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+/** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * @param __PLLSOURCE__: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ *
+ */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief Macro to configure the PLL multiplication factor.
+ * @note This function must be used only when the main PLL is disabled.
* @param __PLLM__: specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
- * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
- * the System clock frequency.
- * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
+ *
*/
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
- (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
- ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
-
-/** @brief Macro to configure the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param __SOURCE__: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
- * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source.
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
+
+/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
+ * @{
*/
-#define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
/** @brief Macros to enable or disable the PLLI2S.
* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
*/
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
+/**
+ * @}
+ */
-/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
- * @note This macro must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * HAL_RCC_ClockConfig() API).
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLI2SR__: specifies the division factor for I2S clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
*/
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
* of the following:
- * - RCC_CFGR_SWS_HSI: HSI used as system clock.
- * - RCC_CFGR_SWS_HSE: HSE used as system clock.
- * - RCC_CFGR_SWS_PLL: PLL used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
*/
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
@@ -1053,6 +1231,14 @@
* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
*/
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
* the selected interrupts).
@@ -1065,7 +1251,7 @@
* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
*/
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
* the selected interrupts).
@@ -1078,7 +1264,7 @@
* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
*/
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
* bits to clear the selected interrupt pending bits.
@@ -1092,7 +1278,7 @@
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
* @arg RCC_IT_CSS: Clock Security System interrupt
*/
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
/** @brief Check the RCC's interrupt has occurred or not.
* @param __INTERRUPT__: specifies the RCC interrupt source to check.
@@ -1134,19 +1320,33 @@
#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
-#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
-
-
-/* Include RCC HAL Extension module */
-#include "stm32f4xx_hal_rcc_ex.h"
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-
+ /** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions ******************************/
void HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/**
+ * @}
+ */
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
/* Peripheral Control functions ************************************************/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void HAL_RCC_EnableCSS(void);
@@ -1162,7 +1362,163 @@
void HAL_RCC_NMI_IRQHandler(void);
/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CCSCallback(void);
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
+#define RCC_HSION_BIT_NUMBER 0x00
+#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER 0x13
+#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER 0x18
+#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
+/* Alias word address of PLLI2SON bit */
+#define RCC_PLLI2SON_BIT_NUMBER 0x1A
+#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of I2SSRC bit */
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
+#define RCC_I2SSRC_BIT_NUMBER 0x17
+#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
+#define RCC_RTCEN_BIT_NUMBER 0x0F
+#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER 0x10
+#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
+#define RCC_LSION_BIT_NUMBER 0x00
+#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+/* BDCR register base address */
+#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
+#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
+
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
+#define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+ * @{
+ */
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
+
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+ ((HCLK) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+ ((PCLK) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+ ((DIV) == RCC_MCODIV_5))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,8 +46,8 @@
* @{
*/
-/** @defgroup RCC
- * @brief RCC HAL module driver
+/** @defgroup RCCEx RCCEx
+ * @brief RCCEx HAL module driver
* @{
*/
@@ -55,18 +55,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
-#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
+/** @addtogroup RCCEx_Private_Constants
+ * @{
+ */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Private_Functions
- * @{
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
*/
-/** @defgroup RCCEx_Group1 Extended Peripheral Control functions
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
@@ -85,7 +88,7 @@
@endverbatim
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F446xx)
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
@@ -103,7 +106,604 @@
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
+ uint32_t plli2sp = 0;
+ uint32_t plli2sq = 0;
+ uint32_t plli2sr = 0;
+ uint32_t pllsaip = 0;
+ uint32_t pllsaiq = 0;
+ uint32_t plli2sused = 0;
+ uint32_t pllsaiused = 0;
+
+ /* Check the peripheral clock selection parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*----------------------------------- I2S APB1 configuration ----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ }
+
+ /*----------------------------------- I2S APB2 configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ }
+
+ /*------------------------------------ SAI1 configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+ /* Configure SAI1 Clock source */
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+ {
+ pllsaiused = 1;
+ }
+ }
+
+ /*------------------------------------ SAI2 configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+ /* Configure SAI2 Clock source */
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+ {
+ pllsaiused = 1;
+ }
+ }
+
+ /*------------------------------------ RTC configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selction is modified */
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+ }
+
+ /* If LSE is selected as RTC clock source, wait for LSE reactivation */
+ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+
+ /*------------------------------------ TIM configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ /* Configure Timer Prescaler */
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+
+ /*------------------------------------- FMPI2C1 Configuration ----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+ /* Configure the FMPI2C1 clock source */
+ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+ }
+
+ /*--------------------------------------- CEC Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+
+ /*-------------------------------------- CK48 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+ /* Enable the PLLSAI when it's used as clock source for CK48 */
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
+ {
+ pllsaiused = 1;
+ }
+ }
+
+ /*------------------------------------- SDIO Configuration ------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+ }
+
+ /*------------------------------------- SPDIFRX Configuration --------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
+
+ /* Configure the SPDIFRX clock source */
+ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
+ if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
+ {
+ plli2sused = 1;
+ }
+ }
+
+ /*-------------------------------------- PLLI2S Configuration --------------*/
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
+ I2S on APB2 or SPDIFRX */
+ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+ {
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check for common PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+ /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+ /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
+ plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+ {
+ /* Check for PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ /* Check for PLLI2S/DIVQ parameters */
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+ /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /*----------------- In Case of PLLI2S is selected as source clock for SPDIFRX -------------------*/
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
+ }
+
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ {
+ /* Check for Parameters */
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
+ if(pllsaiused == 1)
+ {
+ /* Disable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is disabled */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+ {
+ /* check for PLLSAIQ Parameter */
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ /* check for PLLSAI/DIVQ Parameter */
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ }
+
+ /*----------------- In Case of PLLSAI is selected as source clock for CK48 -------------------*/
+ /* In Case of PLLI2S is selected as source clock for CK48 */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+ /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* Configure the PLLSAI division factors */
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) × (PLLI2SN/PLLSAIM) */
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0);
+ }
+
+ /* Enable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is ready */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\
+ RCC_PERIPHCLK_CK48 | RCC_PERIPHCLK_SDIO |\
+ RCC_PERIPHCLK_SPDIFRX;
+
+ /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
+
+ /* Get the SAI1 clock configuration ----------------------------------------------*/
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+ /* Get the SAI2 clock configuration ----------------------------------------------*/
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+ /* Get the I2S APB1 clock configuration ------------------------------------------*/
+ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+ /* Get the I2S APB2 clock configuration ------------------------------------------*/
+ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+ /* Get the RTC Clock configuration -----------------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ /* Get the CEC clock configuration -----------------------------------------------*/
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+ /* Get the FMPI2C1 clock configuration -----------------------------------------------*/
+ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+ /* Get the CK48 clock configuration -----------------------------------------------*/
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+ /* Get the SDIO clock configuration -----------------------------------------------*/
+ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+ /* Get the SPDIFRX clock configuration ----------------------------------------------*/
+ PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
+
+ /* Get the TIM Prescaler configuration --------------------------------------------*/
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+}
+
+/**
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk: Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
+ * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t tmpreg1 = 0;
+ /* This variable used to store the SAI clock frequency (value in Hz) */
+ uint32_t frequency = 0;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0;
+ /* This variable used to store the SAI clock source */
+ uint32_t saiclocksource = 0;
+ if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
+ {
+ saiclocksource = RCC->DCKCFGR;
+ saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
+ switch (saiclocksource)
+ {
+ case 0: /* PLLSAI is the clock source for SAI*/
+ {
+ /* Configure the PLLSAI division factor */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
+ }
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg1);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
+ frequency = frequency/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
+ case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg1);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
+ frequency = frequency/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
+ case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ /* SAI_CLK_x = PLL_VCO Output/PLLR */
+ tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28;
+ frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6))/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
+ {
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ frequency = (uint32_t)(HSI_VALUE);
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ frequency = (uint32_t)(HSE_VALUE);
+ }
+ break;
+ }
+ default :
+ {
+ break;
+ }
+ }
+ }
+ return frequency;
+}
+
+#endif /* STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals
+ * clocks(I2S, SAI, LTDC RTC and TIM).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
@@ -156,12 +756,12 @@
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
- tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
}
@@ -215,11 +815,11 @@
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
}
@@ -231,11 +831,11 @@
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
}
@@ -259,7 +859,7 @@
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Enable Power Clock*/
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
@@ -269,22 +869,22 @@
while((PWR->CR & PWR_CR_DBP) == RESET)
{
- if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selction is modified */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
/* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg;
+ RCC->BDCR = tmpreg1;
}
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
@@ -296,7 +896,7 @@
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -352,6 +952,7 @@
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
}
}
+
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
@@ -371,7 +972,7 @@
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
@@ -430,7 +1031,7 @@
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Enable Power Clock*/
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
@@ -440,22 +1041,22 @@
while((PWR->CR & PWR_CR_DBP) == RESET)
{
- if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selction is modified */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
/* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg;
+ RCC->BDCR = tmpreg1;
}
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
@@ -467,7 +1068,7 @@
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -506,7 +1107,7 @@
}
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F411xE)
+#if defined(STM32F411xE) || defined(STM32F446xx)
/**
* @brief Select LSE mode
*
@@ -532,7 +1133,534 @@
}
}
-#endif /* STM32F411xE */
+#endif /* STM32F411xE || STM32F446xx */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note This function add the PLL/PLLR factor management during PLL configuration this feature is only available in STM32F446xx devices
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division factors. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ,
+ RCC_OscInitStruct->PLL.PLLR);
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
+ *
+ * @note This function is only available in case of STM32F446xx devices.
+ * @note This function add the PLL/PLLR factor management
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note This function is only available in case of STM32F446xx devices.
+ * @note This function add the PLL/PLLR System clock source
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t pllm = 0;
+ uint32_t pllvco = 0;
+ uint32_t pllp = 0;
+ uint32_t pllr = 0;
+ uint32_t sysclockfreq = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
+
+ sysclockfreq = pllvco/pllp;
+ break;
+ }
+ case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
+
+ sysclockfreq = pllvco/pllr;
+ break;
+ }
+ default:
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+#endif /* STM32F446xx */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,8 +54,141 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
+ This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
+#if defined(STM32F446xx)
+ uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+ This parameter is only available in STM32F446xx devices.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
+#endif /* STM32F446xx */
+}RCC_PLLInitTypeDef;
+
+#if defined(STM32F446xx)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
+
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
+ This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
+
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief PLLSAI Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
+
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
+ This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
+
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+}RCC_PLLSAIInitTypeDef;
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+
+ uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+ uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+ uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+ uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+ uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+ This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
/**
* @brief PLLI2S Clock structure definition
*/
@@ -165,106 +298,100 @@
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
* @{
*/
-/** @defgroup RCCEx_Periph_Clock_Selection
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/*------------------------------- Peripheral Clock source for STM32F446xx -----------------------------*/
+#if defined(STM32F446xx)
+#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
+#endif /* STM32F446xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/*-----------------------------------------------------------------------------------------------------*/
+/*------------------------ Peripheral Clock source for STM32F40xxx/STM32F41xxx ------------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_BitAddress_AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-/* --- CR Register ---*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-/* Alias word address of PLLSAION bit */
-#define PLLSAION_BitNumber 0x1C
-#define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
-
-/* --- DCKCFGR Register ---*/
-/* Alias word address of TIMPRE bit */
-#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
-#define TIMPRE_BitNumber 0x18
-#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
+/*-----------------------------------------------------------------------------------------------------*/
/**
* @}
*/
-/** @defgroup RCCEx_PLLI2S_Clock_Source
+/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
* @{
- */
-#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
+#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
+#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
+#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/
-/** @defgroup RCCEx_PLLSAI_Clock_Source
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
* @{
*/
-#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_PLLSAI_DIVQ
- * @{
- */
-#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+#if defined(STM32F446xx)
+#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
+#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
+#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
+#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
+#endif /* STM32F446xx */
/**
* @}
*/
-/** @defgroup RCCEx_PLLI2S_DIVQ
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
* @{
- */
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-
+ */
+#if defined(STM32F446xx)
+#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
+#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
+#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
+#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
+#endif /* STM32F446xx */
/**
* @}
*/
-/** @defgroup RCCEx_PLLSAI_DIVR
- * @{
- */
-#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
-#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
-#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
-#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
-#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
- ((VALUE) == RCC_PLLSAIDIVR_4) ||\
- ((VALUE) == RCC_PLLSAIDIVR_8) ||\
- ((VALUE) == RCC_PLLSAIDIVR_16))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_SAI_BlockA_Clock_Source
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
* @{
*/
#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
@@ -274,7 +401,7 @@
* @}
*/
-/** @defgroup RCCEx_SAI_BlockB_Clock_Source
+/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
* @{
*/
#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
@@ -283,8 +410,104 @@
/**
* @}
*/
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-/** @defgroup RCCEx_TIM_PRescaler_Selection
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
+ * @{
+ */
+#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
+#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
+#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
+ * @{
+ */
+#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
+#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
+#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
+#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
+#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
+ * @{
+ */
+#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
+#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
+ * @{
+ */
+#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
+#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
+ * @{
+ */
+#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
+#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
+ * @{
+ */
+#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
+#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
* @{
*/
#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
@@ -292,84 +515,148 @@
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
-#if defined(STM32F411xE)
-/** @defgroup RCCEx_PLLI2S_PLLI2SM
- * @{
- */
-#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_LSE_Dual_Mode_Selection
+#if defined(STM32F411xE) || defined(STM32F446xx)
+/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
* @{
*/
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
-#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
- ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
/**
* @}
*/
-
-#endif /* STM32F411xE */
+#endif /* STM32F411xE || STM32F446xx */
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
-/*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+/*------------------------------- STM32F42xxx/STM32F43xxx ----------------------------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
/** @brief Enables or disables the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
-#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
-#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
-#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
-#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
-#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
-#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
-#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
-#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
-#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
-#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
-#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
-#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
-#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
-#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
/**
* @brief Enable ETHERNET clock.
*/
-#define __ETH_CLK_ENABLE() do { \
- __ETHMAC_CLK_ENABLE(); \
- __ETHMACTX_CLK_ENABLE(); \
- __ETHMACRX_CLK_ENABLE(); \
- } while(0)
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0)
/**
* @brief Disable ETHERNET clock.
*/
-#define __ETH_CLK_DISABLE() do { \
- __ETHMACTX_CLK_DISABLE(); \
- __ETHMACRX_CLK_DISABLE(); \
- __ETHMAC_CLK_DISABLE(); \
- } while(0)
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
+ } while(0)
/** @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
@@ -377,15 +664,33 @@
* using it.
*/
-#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
-#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
#if defined(STM32F437xx)|| defined(STM32F439xx)
-#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
-#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
#endif /* STM32F437xx || STM32F439xx */
/** @brief Enables or disables the AHB3 peripheral clock.
@@ -393,152 +698,277 @@
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
-#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
-#define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
-#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
-#define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
-#define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
-#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
-#define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
-#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
-#define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
-#define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
-#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
-#define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
-#define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
-#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
#if defined(STM32F429xx)|| defined(STM32F439xx)
-#define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
+#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
-#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
#endif /* STM32F429xx || STM32F439xx */
/** @brief Force or release AHB1 peripheral reset.
*/
-#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
-#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
-#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
-#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
-#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
-#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
/** @brief Force or release AHB2 peripheral reset.
*/
-#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-#if defined(STM32F437xx)|| defined(STM32F439xx)
-#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#if defined(STM32F437xx)|| defined(STM32F439xx)
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
#endif /* STM32F437xx || STM32F439xx */
/** @brief Force or release AHB3 peripheral reset
*/
-#define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
-#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
/** @brief Force or release APB1 peripheral reset.
*/
-#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
-#define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
-#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
-#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
/** @brief Force or release APB2 peripheral reset.
*/
-#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
-#define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
-#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
-#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
#if defined(STM32F429xx)|| defined(STM32F439xx)
-#define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
-#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
#endif /* STM32F429xx|| STM32F439xx */
/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
@@ -547,34 +977,34 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
-#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
-#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
-#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
-#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
-#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
-#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -582,15 +1012,15 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-#if defined(STM32F437xx)|| defined(STM32F439xx)
-#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#if defined(STM32F437xx)|| defined(STM32F439xx)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
#endif /* STM32F437xx || STM32F439xx */
/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
@@ -599,8 +1029,8 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
-#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -608,33 +1038,33 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
-#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
-#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
-#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -642,25 +1072,26 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
-#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
-#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
-#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
#if defined(STM32F429xx)|| defined(STM32F439xx)
-#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
-#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
#endif /* STM32F429xx || STM32F439xx */
+
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
/*---------------------------------------------------------------------------------------------*/
@@ -671,43 +1102,97 @@
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
-#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
-#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
-#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
#if defined(STM32F407xx)|| defined(STM32F417xx)
/**
* @brief Enable ETHERNET clock.
*/
-#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
-#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
-#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
-#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
-#define __ETH_CLK_ENABLE() do { \
- __ETHMAC_CLK_ENABLE(); \
- __ETHMACTX_CLK_ENABLE(); \
- __ETHMACRX_CLK_ENABLE(); \
- } while(0)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0)
/**
* @brief Disable ETHERNET clock.
*/
-#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
-#define __ETH_CLK_DISABLE() do { \
- __ETHMACTX_CLK_DISABLE(); \
- __ETHMACRX_CLK_DISABLE(); \
- __ETHMAC_CLK_DISABLE(); \
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
} while(0)
#endif /* STM32F407xx || STM32F417xx */
@@ -717,16 +1202,33 @@
* using it.
*/
#if defined(STM32F407xx)|| defined(STM32F417xx)
-#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
-#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
#endif /* STM32F407xx || STM32F417xx */
#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
-#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
-
-#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
#endif /* STM32F415xx || STM32F417xx */
/** @brief Enables or disables the AHB3 peripheral clock.
@@ -734,118 +1236,206 @@
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
-#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
-#define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
-#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
-#define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
-#define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
-#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-
-#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
-#define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
-#define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
/** @brief Force or release AHB1 peripheral reset.
*/
-#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
/** @brief Force or release AHB2 peripheral reset.
*/
#if defined(STM32F407xx)|| defined(STM32F417xx)
-#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
#endif /* STM32F407xx || STM32F417xx */
#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
#endif /* STM32F415xx || STM32F417xx */
/** @brief Force or release AHB3 peripheral reset
*/
-#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
-#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
/** @brief Force or release APB1 peripheral reset.
*/
-#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
/** @brief Force or release APB2 peripheral reset.
*/
-#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -853,27 +1443,27 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -882,16 +1472,16 @@
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
#if defined(STM32F407xx)|| defined(STM32F417xx)
-#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
#endif /* STM32F407xx || STM32F417xx */
#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
#endif /* STM32F415xx || STM32F417xx */
/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
@@ -900,8 +1490,8 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
-#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -909,29 +1499,454 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+/*---------------------------------------------------------------------------------------------*/
+
+/*------------------------------------------ STM32F411xx --------------------------------------*/
+#if defined(STM32F411xE)
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ */
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+
+/** @brief Force or release APB2 peripheral reset.
+ */
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+
+#endif /* STM32F411xE */
+/*---------------------------------------------------------------------------------------------*/
+
+/*----------------------------------------- STM32F446xx ---------------------------------------*/
+#if defined(STM32F446xx)
+/** @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+
+/** @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+
+/** @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
+
+/** @brief Force or release AHB1 peripheral reset.
+ */
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+
+/** @brief Force or release AHB2 peripheral reset.
+ */
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+
+/** @brief Force or release AHB3 peripheral reset
+ */
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+
+/** @brief Force or release APB1 peripheral reset.
+ */
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+
+/** @brief Force or release APB2 peripheral reset.
+ */
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
+
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+
+/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -939,38 +1954,524 @@
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
+
+#endif /* STM32F446xx */
+/*------------------------------------------------------------------------------------------------------------*/
+
+/*------------------------------------------------- PLL Configuration ----------------------------------------*/
+#if defined(STM32F446xx)
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 192 and 432 MHz.
+ *
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ * @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note This parameter is only available in STM32F446xx devices.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
+ (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
+ ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
+ ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
+#else
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 192 and 432 MHz.
+ *
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
+ (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
+ ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+ #endif /* STM32F446xx */
+/*-------------------------------------------------------------------------------------------------------*/
-#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-/*---------------------------------------------------------------------------------------------*/
+/*------------------------------------------- PLLI2S Configuration --------------------------------------*/
+#if defined(STM32F446xx)
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 1 MHz to limit PLLI2S jitter.
+ * @note The PLLI2SM parameter is only used with STM32F411xE and STM32F446xx Devices
+ *
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ *
+ * @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note the PLLI2SP parameter is only available with STM32F446xx Devices
+ *
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ * @param __PLLI2SQ__: specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note the PLLI2SQ parameter is only available with STM32F427/437/429x/439xx Devices
+ *
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
+ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
+ ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
+ ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
+ ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
+ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+#else
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
+ (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | \
+ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+#endif /* STM32F446xx */
-/*------------------------------------------ STM32F411xx --------------------------------------*/
#if defined(STM32F411xE)
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note The PLLI2SM parameter is only used with STM32F411xE Devices
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLLI2S jitter.
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
+ ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
+ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+#endif /* STM32F411xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API)
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx Devices
+ * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) |\
+ ((__PLLI2SQ__) << 24) |\
+ ((__PLLI2SR__) << 28))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------------- PLLSAI Configuration ---------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+/** @brief Macros to Enable or Disable the PLLISAI.
+ * @note The PLLSAI is only available with STM32F429x/439x Devices.
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
+#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
+
+#if defined(STM32F446xx)
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ *
+ * @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 1 MHz to limit PLLI2S jitter.
+ * @note The PLLSAIM parameter is only used with STM32F446xx Devices
+ *
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ *
+ * @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note the PLLSAIP parameter is only available with STM32F446xx Devices
+ *
+ * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = ((__PLLSAIM__) | \
+ ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
+ ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \
+ ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
+#endif /* STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ *
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ *
+ * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
*/
-#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
-#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-
-/** @brief Force or release APB2 peripheral reset.
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
+ ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | \
+ ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+/*----------------------------------------------------------------------------------------------------------------------*/
+
+/*----------------------------------------- PLLSAI/PLLI2S Dividers Configuration ---------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
+ * @note This function must be called before enabling the PLLI2S.
+ * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
+ */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
+
+/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+ * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
+ *
+ * @note The LTDC peripheral is only available with STM32F427/437/429/439xx Devices.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+ * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/*-----------------------------------------------------------------------------------------------------------------------------------*/
+
+/*-------------------------------------------------- Peripheral Clock selection -----------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __SOURCE__: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source.
*/
-#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/** @brief Macro to configure SAI1BlockA clock source selection.
+ * @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block A clock.
+ */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief Macro to configure SAI1BlockB clock source selection.
+ * @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block B clock.
+ */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F446xx)
+/** @brief Macro to configure SAI1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ */
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
+
+/** @brief Macro to Get SAI1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ */
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
+
+/** @brief Macro to configure SAI2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+ */
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
- */
-#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+/** @brief Macro to Get SAI2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+ */
+#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
+
+/** @brief Macro to configure I2S APB1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
+ * @param __SOURCE__: specifies the I2S APB1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief Macro to configure I2S APB2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
+ * @param __SOURCE__: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief Macro to configure the CEC clock.
+ * @param __SOURCE__: specifies the CEC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
-#endif /* STM32F411xE */
-/*---------------------------------------------------------------------------------------------*/
+/** @brief Macro to Get the CEC clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
+
+/** @brief Macro to configure the FMPI2C1 clock.
+ * @param __SOURCE__: specifies the FMPI2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
+ */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the FMPI2C1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
+ */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief Macro to configure the CLK48 clock.
+ * @param __SOURCE__: specifies the CK48 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
+ * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
+ */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CLK48 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
+ * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
+ */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief Macro to configure the SDIO clock.
+ * @param __SOURCE__: specifies the SDIO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SDIO clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+/** @brief Macro to configure the SPDIFRX clock.
+ * @param __SOURCE__: specifies the SPDIFRX clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
+ */
+#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SPDIFRX clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
+ */
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
+#endif /* STM32F446xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
/** @brief Macro to configure the Timers clocks prescalers
* @note This feature is only available with STM32F429x/439x Devices.
@@ -985,138 +2486,13 @@
* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
* to division by 8 or more.
*/
-#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
-#if defined(STM32F411xE)
-
-/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
- * @note This macro must be used only when the PLLI2S is disabled.
- * @note This macro must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * HAL_RCC_ClockConfig() API).
- * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLLI2S jitter.
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLI2SR__: specifies the division factor for I2S clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- */
-#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
-#endif /* STM32F411xE */
-
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
-/** @brief Macros to Enable or Disable the PLLISAI.
- * @note The PLLSAI is only available with STM32F429x/439x Devices.
- * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
-#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
-
-/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
- * @note The PLLSAI is only available with STM32F429x/439x Devices.
- * @note This function must be used only when the PLLSAI is disabled.
- * @note PLLSAI clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
- * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @param __PLLSAIR__: specifies the division factor for LTDC clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
-/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
- * @note This macro must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * HAL_RCC_ClockConfig() API)
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
- * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
- * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
- * @param __PLLI2SR__: specifies the division factor for I2S clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- */
-#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
-
-/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
- * @note This function must be called before enabling the PLLI2S.
- * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
- * This parameter must be a number between 1 and 32.
- * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
- */
-#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
-
-/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
- * @note This function must be called before enabling the PLLSAI.
- * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
- * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
- * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
- */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
+/*-------------------------------------------------------------------------------------------------------------------*/
-/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
- *
- * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
- * @note This function must be called before enabling the PLLSAI.
- * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
- * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
- * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
- */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
-
-/** @brief Macro to configure SAI1BlockA clock source selection.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
- * @note This function must be called before enabling PLLSAI, PLLI2S and
- * the SAI clock.
- * @param __SOURCE__: specifies the SAI Block A clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
- * as SAI1 Block A clock.
- * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
- * as SAI1 Block A clock.
- * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
- * used as SAI1 Block A clock.
- */
-#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
-
-/** @brief Macro to configure SAI1BlockB clock source selection.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
- * @note This function must be called before enabling PLLSAI, PLLI2S and
- * the SAI clock.
- * @param __SOURCE__: specifies the SAI Block B clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
- * as SAI1 Block B clock.
- * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
- * as SAI1 Block B clock.
- * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
- * used as SAI1 Block B clock.
- */
-#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
-
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/** @brief Enable PLLSAI_RDY interrupt.
*/
#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
@@ -1139,15 +2515,30 @@
*/
#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-#if defined(STM32F411xE)
+#if defined(STM32F446xx)
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+#endif /* STM32F446xx */
+
+#if defined(STM32F411xE) || defined(STM32F446xx)
void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
-#endif /* STM32F411xE */
+#endif /* STM32F411xE || STM32F446xx */
/**
* @}
*/
@@ -1155,7 +2546,158 @@
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+/* --- CR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+/* Alias word address of PLLSAION bit */
+#define RCC_PLLSAION_BIT_NUMBER 0x1C
+#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
+
+/* --- DCKCFGR Register ---*/
+/* Alias word address of TIMPRE bit */
+#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
+#define RCC_TIMPRE_BIT_NUMBER 0x18
+#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+ * @{
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000007FF))
+#endif /* STM32F446xx */
+
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
+
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_4) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_8) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_16))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F446xx) || defined(STM32F411xE)
+#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
+
+#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+ ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F446xx || STM32F411xE */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV4) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV6) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV8))
+
+#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
+
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV8))
+
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
+
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+
+#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
+ ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
+ ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+#endif /* STM32F446xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rng.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -15,20 +15,21 @@
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
+ [..]
The RNG HAL driver can be used as follows:
- (#) Enable the RNG controller clock using __RNG_CLK_ENABLE() macro.
- (#) Activate the RNG peripheral using __HAL_RNG_ENABLE() macro.
- (#) Wait until the 32 bit Random Number Generator contains a valid
- random data using (polling/interrupt) mode.
- (#) Get the 32 bit random number using HAL_RNG_GetRandomNumber() function.
+ (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
+ in HAL_RNG_MspInit().
+ (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+ (#) Wait until the 32 bit Random Number Generator contains a valid
+ random data using (polling/interrupt) mode.
+ (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -62,8 +63,7 @@
* @{
*/
-/** @defgroup RNG
- * @brief RNG HAL module driver.
+/** @addtogroup RNG
* @{
*/
@@ -72,22 +72,31 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define RNG_TIMEOUT_VALUE 1000
-/* Private macro -------------------------------------------------------------*/
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Constants
+ * @{
+ */
+#define RNG_TIMEOUT_VALUE 2
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions
+/** @addtogroup RNG_Exported_Functions
* @{
*/
-/** @defgroup RNG_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @addtogroup RNG_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@@ -97,14 +106,13 @@
(+) DeInitialize the RNG peripheral
(+) Initialize the RNG MSP
(+) DeInitialize RNG MSP
-
+
@endverbatim
* @{
*/
-
+
/**
- * @brief Initializes the RNG according to the specified
- * parameters in the RNG_InitTypeDef and creates the associated handle.
+ * @brief Initializes the RNG peripheral and creates the associated handle.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
@@ -116,12 +124,17 @@
{
return HAL_ERROR;
}
-
+
+ __HAL_LOCK(hrng);
+
if(hrng->State == HAL_RNG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
+
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
@@ -130,7 +143,9 @@
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
-
+
+ __HAL_UNLOCK(hrng);
+
/* Return function status */
return HAL_OK;
}
@@ -143,22 +158,16 @@
*/
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
- /* Check the RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_BUSY)
+ /* Check the RNG handle allocation */
+ if(hrng == HAL_NULL)
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
+ /* Disable the RNG Peripheral */
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
- /* Update the RNG state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
- /* Disable the RNG Peripheral */
- __HAL_RNG_DISABLE(hrng);
-
- /* Set the RNG registers to their reset values */
- hrng->Instance->CR &= 0xFFFFFFF3;
- hrng->Instance->SR &= 0xFFFFFF98;
- hrng->Instance->DR &= 0x0;
+ /* Clear RNG interrupt status flags */
+ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
@@ -181,8 +190,8 @@
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_MspInit could be implemented in the user file
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspInit must be implemented in the user file.
*/
}
@@ -194,8 +203,8 @@
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_MspDeInit could be implemented in the user file
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspDeInit must be implemented in the user file.
*/
}
@@ -203,8 +212,8 @@
* @}
*/
-/** @defgroup RNG_Group2 Peripheral Control functions
- * @brief management functions.
+/** @addtogroup RNG_Exported_Functions_Group2
+ * @brief Peripheral Control functions
*
@verbatim
===============================================================================
@@ -215,51 +224,182 @@
(+) Get the 32 bit Random number with interrupt enabled
(+) Handle RNG interrupt request
-
@endverbatim
* @{
*/
-
+
/**
- * @brief Returns a 32-bit random number.
+ * @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @retval 32-bit random number
+ * @param random32bit: pointer to generated random number variable if successful.
+ * @retval HAL status
*/
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
- uint32_t random32bit = 0;
uint32_t tickstart = 0;
-
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Process Locked */
__HAL_LOCK(hrng);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if data register contains valid random data */
- while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ /* Check RNG peripheral state */
+ if(hrng->State == HAL_RNG_STATE_READY)
{
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if data register contains valid random data */
+ while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get a 32bit Random number */
+ hrng->RandomNumber = hrng->Instance->DR;
+ *random32bit = hrng->RandomNumber;
+
+ hrng->State = HAL_RNG_STATE_READY;
}
-
- /* Get a 32bit Random number */
- random32bit = hrng->Instance->DR;
+ else
+ {
+ status = HAL_ERROR;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hrng);
- /* Return the 32 bit random number */
- return random32bit;
+ return status;
+}
+
+/**
+ * @brief Generates a 32-bit random number in interrupt mode.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hrng);
+
+ /* Check RNG peripheral state */
+ if(hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ status = HAL_ERROR;
+ }
+
+ return status;
}
/**
- * @brief Returns a 32-bit random number with interrupt enabled.
+ * @brief Handles RNG interrupt request.
+ * @note In the case of a clock error, the RNG is no more able to generate
+ * random numbers because the PLL48CLK clock is not correct. User has
+ * to check that the clock controller is correctly configured to provide
+ * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
+ * The clock error has no impact on the previously generated
+ * random numbers, and the RNG_DR register contents can be used.
+ * @note In the case of a seed error, the generation of random numbers is
+ * interrupted as long as the SECS bit is '1'. If a number is
+ * available in the RNG_DR register, it must not be used because it may
+ * not have enough entropy. In this case, it is recommended to clear the
+ * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
+ * the RNG peripheral to reinitialize and restart the RNG.
+ * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+ * or CEIS are set.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+
+ */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+ /* RNG clock error interrupt occurred */
+ if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_ERROR;
+
+ HAL_RNG_ErrorCallback(hrng);
+
+ /* Clear the clock error flag */
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
+
+ }
+
+ /* Check RNG data ready interrupt occurred */
+ if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ {
+ /* Generate random number once, so disable the IT */
+ __HAL_RNG_DISABLE_IT(hrng);
+
+ /* Get the 32bit Random number (DRDY flag automatically cleared) */
+ hrng->RandomNumber = hrng->Instance->DR;
+
+ if(hrng->State != HAL_RNG_STATE_ERROR)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* Data Ready callback */
+ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+ }
+ }
+}
+
+/**
+ * @brief Returns generated random number in polling mode (Obsolete)
+ * Use HAL_RNG_GenerateRandomNumber() API instead.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval Random value
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+ {
+ return hrng->RandomNumber;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
+ * Use HAL_RNG_GenerateRandomNumber_IT() API instead.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval 32-bit random number
@@ -268,7 +408,7 @@
{
uint32_t random32bit = 0;
- /* Process Locked */
+ /* Process locked */
__HAL_LOCK(hrng);
/* Change RNG peripheral state */
@@ -285,84 +425,27 @@
}
/**
- * @brief Handles RNG interrupt request.
- * @note In the case of a clock error, the RNG is no more able to generate
- * random numbers because the PLL48CLK clock is not correct. User has
- * to check that the clock controller is correctly configured to provide
- * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_FLAG().
- * The clock error has no impact on the previously generated
- * random numbers, and the RNG_DR register contents can be used.
- * @note In the case of a seed error, the generation of random numbers is
- * interrupted as long as the SECS bit is '1'. If a number is
- * available in the RNG_DR register, it must not be used because it may
- * not have enough entropy. In this case, it is recommended to clear the
- * SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable
- * the RNG peripheral to reinitialize and restart the RNG.
+ * @brief Read latest generated random number.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @retval None
-
+ * @retval random value
*/
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
{
- /* RNG clock error interrupt occurred */
- if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET)
- {
- HAL_RNG_ErrorCallback(hrng);
-
- /* Clear the clock error flag */
- __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_CEI);
-
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- }
-
- /* RNG seed error interrupt occurred */
- if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET)
- {
- HAL_RNG_ErrorCallback(hrng);
-
- /* Clear the seed error flag */
- __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_SEI);
-
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- }
-
- /* Check RNG data ready flag */
- if(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != RESET)
- {
- /* Data Ready callback */
- HAL_RNG_ReadyCallback(hrng);
-
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_READY;
-
- /* Clear the RNG Data Ready flag */
- __HAL_RNG_CLEAR_FLAG(hrng, RNG_FLAG_DRDY);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- }
-}
+ return(hrng->RandomNumber);
+}
/**
* @brief Data Ready callback in non-blocking mode.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
+ * @param random32bit: generated random number.
* @retval None
*/
-
-__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng)
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_ReadyCallback could be implemented in the user file
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
}
@@ -374,17 +457,17 @@
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_ErrorCallback could be implemented in the user file
- */
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ErrorCallback must be implemented in the user file.
+ */
}
-
/**
* @}
- */
+ */
-/** @defgroup RNG_Group3 Peripheral State functions
- * @brief Peripheral State functions.
+
+/** @addtogroup RNG_Exported_Functions_Group3
+ * @brief Peripheral State functions
*
@verbatim
===============================================================================
@@ -397,7 +480,7 @@
@endverbatim
* @{
*/
-
+
/**
* @brief Returns the RNG state.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
@@ -412,7 +495,7 @@
/**
* @}
*/
-
+
/**
* @}
*/
@@ -420,6 +503,7 @@
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* HAL_RNG_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rng.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_RNG_H
@@ -45,6 +45,7 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -52,15 +53,20 @@
* @{
*/
-/** @addtogroup RNG
+/** @defgroup RNG RNG
+ * @brief RNG HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
-/**
- * @brief RNG HAL State Structure definition
- */
+/** @defgroup RNG_Exported_Types RNG Exported Types
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
+ * @{
+ */
typedef enum
{
HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */
@@ -72,47 +78,55 @@
}HAL_RNG_StateTypeDef;
/**
- * @brief RNG Handle Structure definition
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
+ * @{
*/
typedef struct
{
- RNG_TypeDef *Instance; /*!< Register base address */
+ RNG_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< RNG locking object */
- HAL_LockTypeDef Lock; /*!< RNG locking object */
+ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
- __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+ uint32_t RandomNumber; /*!< Last Generated RNG Data */
}RNG_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Constants
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
* @{
*/
-/** @defgroup RNG_Interrupt_definition
+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
* @{
- */
-#define RNG_IT_CEI ((uint32_t)0x20) /*!< Clock error interrupt */
-#define RNG_IT_SEI ((uint32_t)0x40) /*!< Seed error interrupt */
-
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
- ((IT) == RNG_IT_SEI))
+ */
+#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
+#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
+#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
/**
* @}
*/
-
-/** @defgroup RNG_Flag_definition
+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
* @{
- */
-#define RNG_FLAG_DRDY ((uint32_t)0x0001) /*!< Data ready */
-#define RNG_FLAG_CECS ((uint32_t)0x0002) /*!< Clock error current status */
-#define RNG_FLAG_SECS ((uint32_t)0x0004) /*!< Seed error current status */
+ */
+#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
+#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
+#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
/**
* @}
*/
@@ -121,7 +135,11 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+ * @{
+ */
/** @brief Reset RNG handle state
* @param __HANDLE__: RNG Handle
@@ -144,21 +162,29 @@
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
/**
- * @brief Gets the selected RNG's flag status.
+ * @brief Check the selected RNG flag status.
* @param __HANDLE__: RNG Handle
* @param __FLAG__: RNG flag
- * @retval The new state of RNG_FLAG (SET or RESET).
+ * This parameter can be one of the following values:
+ * @arg RNG_FLAG_DRDY: Data ready
+ * @arg RNG_FLAG_CECS: Clock error current status
+ * @arg RNG_FLAG_SECS: Seed error current status
+ * @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
- * @brief Clears the RNG's pending flags.
- * @param __HANDLE__: RNG Handle
- * @param __FLAG__: RNG flag
+ * @brief Clears the selected RNG flag status.
+ * @param __HANDLE__: RNG handle
+ * @param __FLAG__: RNG flag to clear
+ * @note WARNING: This is a dummy macro for HAL code alignment,
+ * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
* @retval None
*/
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
+
+
+
/**
* @brief Enables the RNG interrupts.
* @param __HANDLE__: RNG Handle
@@ -176,34 +202,147 @@
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
* @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt source to check.
+ * @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
* This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data ready interrupt
- * @arg RNG_FLAG_CECS: Clock error interrupt
- * @arg RNG_FLAG_SECS: Seed error interrupt
- * @retval The new state of RNG_FLAG (SET or RESET).
+ * @arg RNG_IT_DRDY: Data ready interrupt
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-/* Exported functions --------------------------------------------------------*/
+/**
+ * @brief Clear the RNG interrupt status flags.
+ * @param __HANDLE__: RNG Handle
+ * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-/* Initialization/de-initialization functions **********************************/
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-/* Peripheral Control functions ************************************************/
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng);
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
-/* Peripheral State functions **************************************************/
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup RNG_Private_Types RNG Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_Private_Defines RNG Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Variables RNG Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_Private_Macros RNG Private Macros
+ * @{
+ */
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+ ((IT) == RNG_IT_SEI))
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -213,10 +352,13 @@
* @}
*/
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
#ifdef __cplusplus
}
#endif
+
#endif /* __STM32F4xx_HAL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -61,7 +61,7 @@
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
- __PWR_CLK_ENABLE() function.
+ __HAL_RCC_PWR_CLK_ENABLE() function.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
(+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
(+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
@@ -93,22 +93,22 @@
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
[..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
+ on an external interrupt (Auto-wake-up mode), by using the RTC alarm
+ or the RTC wake-up events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
- Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
+ Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -142,7 +142,7 @@
* @{
*/
-/** @defgroup RTC
+/** @defgroup RTC RTC
* @brief RTC HAL module driver
* @{
*/
@@ -156,11 +156,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
-/** @defgroup RTC_Group1 Initialization and de-initialization functions
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -183,7 +183,7 @@
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
(#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
+ initialization, calendar update or after wake-up from low power modes
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
@@ -218,6 +218,8 @@
if(hrtc->State == HAL_RTC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
@@ -376,7 +378,7 @@
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implenetd in the user file
+ the HAL_RTC_MspInit could be implemented in the user file
*/
}
@@ -389,7 +391,7 @@
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implenetd in the user file
+ the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@@ -397,7 +399,7 @@
* @}
*/
-/** @defgroup RTC_Group2 RTC Time and Date functions
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @brief RTC Time and Date functions
*
@verbatim
@@ -418,8 +420,8 @@
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -436,7 +438,7 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -543,10 +545,11 @@
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
- * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers.
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -569,7 +572,7 @@
sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the time structure parameters to Binary format */
sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
@@ -587,8 +590,8 @@
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -603,14 +606,14 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
@@ -696,8 +699,11 @@
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -717,7 +723,7 @@
sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to Binary format */
sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
@@ -731,7 +737,7 @@
* @}
*/
-/** @defgroup RTC_Group3 RTC Alarm functions
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @brief RTC Alarm functions
*
@verbatim
@@ -751,8 +757,8 @@
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@@ -762,8 +768,8 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(sAlarm->Alarm));
- assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
@@ -773,7 +779,7 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -937,8 +943,8 @@
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@@ -948,8 +954,8 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(sAlarm->Alarm));
- assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
@@ -959,7 +965,7 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -1106,7 +1112,7 @@
}
/* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT);
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
@@ -1122,7 +1128,7 @@
}
/**
- * @brief Deactive the specified RTC Alarm
+ * @brief Deactivate the specified RTC Alarm
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
@@ -1136,7 +1142,7 @@
uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_ALARM(Alarm));
+ assert_param(IS_RTC_ALARM(Alarm));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1224,8 +1230,8 @@
* @arg RTC_ALARM_B: AlarmB
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
@@ -1234,7 +1240,7 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(Alarm));
+ assert_param(IS_RTC_ALARM(Alarm));
if(Alarm == RTC_ALARM_A)
{
@@ -1262,7 +1268,7 @@
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
@@ -1308,7 +1314,7 @@
}
/* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT);
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1366,7 +1372,7 @@
* @}
*/
-/** @defgroup RTC_Group4 Peripheral Control functions
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -1387,7 +1393,7 @@
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
+ * initialization, calendar update or after wake-up from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
@@ -1418,7 +1424,11 @@
return HAL_OK;
}
-/** @defgroup RTC_Group5 Peripheral State functions
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+
/**
* @brief HAL State structures definition
*/
@@ -165,7 +169,7 @@
}RTC_AlarmTypeDef;
/**
- * @brief Time Handle Structure definition
+ * @brief RTC Handle Structure definition
*/
typedef struct
{
@@ -179,165 +183,93 @@
}RTC_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants
- * @{
- */
+/**
+ * @}
+ */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
- RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+ * @{
+ */
-#define RTC_TIMEOUT_VALUE 1000
-
-/** @defgroup RTC_Hour_Formats
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
-
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
- ((FORMAT) == RTC_HOURFORMAT_24))
/**
* @}
*/
-/** @defgroup RTC_Output_selection_Definitions
+/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
* @{
*/
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
/**
* @}
*/
-/** @defgroup RTC_Output_Polarity_Definitions
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
- ((POL) == RTC_OUTPUT_POLARITY_LOW))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT
- * @{
- */
-#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
-#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
- ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
/**
* @}
*/
-/** @defgroup RTC_Asynchronous_Predivider
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
/**
* @}
*/
-/** @defgroup RTC_Time_Definitions
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
/**
* @}
*/
-/** @defgroup RTC_AM_PM_Definitions
- * @{
- */
-#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
-
-#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
/**
* @}
*/
-/** @defgroup RTC_StoreOperation_Definitions
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
- ((OPERATION) == RTC_STOREOPERATION_SET))
/**
* @}
*/
-/** @defgroup RTC_Input_parameter_format_definitions
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
-#define FORMAT_BIN ((uint32_t)0x000000000)
-#define FORMAT_BCD ((uint32_t)0x000000001)
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
/**
* @}
*/
-/** @defgroup RTC_Year_Date_Definitions
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
*/
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
- * @{
- */
-
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
@@ -351,14 +283,11 @@
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
/**
* @}
*/
-/** @defgroup RTC_WeekDay_Definitions
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
@@ -368,48 +297,20 @@
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
/**
* @}
*/
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
- ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
/**
* @}
*/
-
-/** @defgroup RTC_AlarmMask_Definitions
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
@@ -418,32 +319,20 @@
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
-
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
/**
* @}
*/
-/** @defgroup RTC_Alarms_Definitions
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
-
-#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
/**
* @}
*/
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
- * @{
- */
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
-/**
- * @}
- */
-
- /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
@@ -477,30 +366,13 @@
comparison. Only SS[12:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
+#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
to activate alarm. */
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_None))
/**
* @}
*/
-/** @defgroup RTC_Interrupts_Definitions
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS ((uint32_t)0x00008000)
@@ -514,7 +386,7 @@
* @}
*/
-/** @defgroup RTC_Flags_Definitions
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
@@ -541,6 +413,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+ * @{
+ */
/** @brief Reset RTC handle state
* @param __HANDLE__: specifies the RTC handle.
@@ -622,18 +497,18 @@
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC Alarm Flag to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
@@ -655,81 +530,133 @@
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-
/**
- * @brief Enable the RTC Exti line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
-
-/* alias define maintained for legacy */
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
- * @brief Disable the RTC Exti line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-/* alias define maintained for legacy */
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+/**
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
- * @retval None
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
*/
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
/**
- * @brief Clear the RTC Exti flags.
- * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
- * @retval None
+ * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Clear the RTC Alarm associated Exti line flag.
+ * @retval None.
*/
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
-/* alias define maintained for legacy */
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
-
+/**
+ * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
+/**
+ * @}
+ */
/* Include RTC HAL Extension module */
#include "stm32f4xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @{
+ */
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @{
+ */
/* RTC Alarm functions ********************************************************/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
@@ -738,16 +665,146 @@
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group5
+ * @{
+ */
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -22,13 +22,13 @@
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
- *** RTC Wakeup configuration ***
+ *** RTC Wake-up configuration ***
================================
[..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer in interrupt mode
+ (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
+ function. You can also configure the RTC Wake-up timer in interrupt mode
using the HAL_RTC_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
+ (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer()
function.
*** TimeStamp configuration ***
@@ -40,7 +40,7 @@
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
function.
(+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
- or RTC_AF2 (PI8) depending on the value of TSINSEL bit in
+ or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in
RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
or HAL_RTC_SetTimeStamp_IT() function.
@@ -53,7 +53,7 @@
HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
mode using HAL_RTC_SetTamper_IT() function.
(+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
- or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
+ or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in
RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
or HAL_RTC_SetTamper_IT() function.
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -103,7 +103,7 @@
* @{
*/
-/** @defgroup RTCEx
+/** @defgroup RTCEx RTCEx
* @brief RTC HAL module driver
* @{
*/
@@ -117,12 +117,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Functions
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
- */
-
+ */
-/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
* @brief RTC TimeStamp and Tamper functions
*
@verbatim
@@ -151,7 +150,8 @@
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices)
+ * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -210,7 +210,8 @@
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices)
+ * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -246,7 +247,7 @@
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
/* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
@@ -307,8 +308,8 @@
* @param sTimeStampDate: Pointer to Date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * FORMAT_BIN: Binary data format
- * FORMAT_BCD: BCD data format
+ * RTC_FORMAT_BIN: Binary data format
+ * RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
@@ -336,7 +337,7 @@
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the TimeStamp structure parameters to Binary format */
sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
@@ -368,14 +369,14 @@
uint32_t tmpreg = 0;
/* Check the parameters */
- assert_param(IS_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
- assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -418,14 +419,14 @@
uint32_t tmpreg = 0;
/* Check the parameters */
- assert_param(IS_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
- assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -452,7 +453,7 @@
hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
@@ -474,7 +475,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
{
- assert_param(IS_TAMPER(Tamper));
+ assert_param(IS_RTC_TAMPER(Tamper));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -541,7 +542,7 @@
}
}
/* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
- __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -604,7 +605,7 @@
{
if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
{
- /* Clear the TIMESTAMP OverRun Flag */
+ /* Clear the TIMESTAMP Overrun Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
/* Change TIMESTAMP state */
@@ -705,7 +706,7 @@
* @}
*/
-/** @defgroup RTCEx_Group2 RTC Wake-up functions
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
* @brief RTC Wake-up functions
*
@verbatim
@@ -732,8 +733,8 @@
uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -765,16 +766,16 @@
}
}
- /* Clear the Wakeup Timer clock source bits in CR register */
+ /* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
- /* Configure the Wakeup Timer counter */
+ /* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Enable the Wakeup Timer */
+ /* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -801,8 +802,8 @@
uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -834,24 +835,24 @@
}
}
- /* Configure the Wakeup Timer counter */
+ /* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Clear the Wakeup Timer clock source bits in CR register */
+ /* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
- /* Enable the Wakeup Timer */
+ /* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -883,7 +884,7 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Disable the Wakeup Timer */
+ /* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
@@ -954,8 +955,8 @@
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
- __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
-
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@@ -1014,7 +1015,7 @@
*/
-/** @defgroup RTCEx_Group3 Extension Peripheral Control functions
+/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
* @brief Extension Peripheral Control functions
*
@verbatim
@@ -1213,12 +1214,12 @@
* the configuration information for RTC.
* @param SmoothCalibPeriod: Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
- * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
- * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s.
- * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
* @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
- * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
* @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
@@ -1625,7 +1626,7 @@
* @}
*/
- /** @defgroup RTCEx_Group4 Extended features functions
+ /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
* @brief Extended features functions
*
@verbatim
@@ -1633,7 +1634,7 @@
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) RTC Alram B callback
+ (+) RTC Alarm B callback
(+) RTC Poll for Alarm B request
@endverbatim
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,9 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+ * @{
+ */
/**
* @brief RTC Tamper structure definition
@@ -85,13 +88,16 @@
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
}RTC_TamperTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
*/
-/** @defgroup RTCEx_Backup_Registers_Definitions
+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
* @{
*/
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
@@ -114,96 +120,66 @@
#define RTC_BKP_DR17 ((uint32_t)0x00000011)
#define RTC_BKP_DR18 ((uint32_t)0x00000012)
#define RTC_BKP_DR19 ((uint32_t)0x00000013)
-
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15) || \
- ((BKP) == RTC_BKP_DR16) || \
- ((BKP) == RTC_BKP_DR17) || \
- ((BKP) == RTC_BKP_DR18) || \
- ((BKP) == RTC_BKP_DR19))
/**
* @}
*/
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
- ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pins_Definitions
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
* @{
*/
#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
-
-#define IS_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pins_Selection
+/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
* @{
*/
#define RTC_TAMPERPIN_PC13 ((uint32_t)0x00000000)
-#define RTC_TAMPERPIN_PI8 ((uint32_t)0x00010000)
-
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
- ((PIN) == RTC_TAMPERPIN_PI8))
+#if defined (STM32F446xx)
+ #define RTC_TAMPERPIN_PA0 ((uint32_t)0x00010000)
+#else
+ #define RTC_TAMPERPIN_PI8 ((uint32_t)0x00010000)
+#endif /* STM32F446xx */
/**
* @}
*/
-/** @defgroup RTCEx_TimeStamp_Pin_Selection
+/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
* @{
*/
#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00020000)
-
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
- ((PIN) == RTC_TIMESTAMPPIN_PI8))
+#if defined (STM32F446xx)
+ #define RTC_TIMESTAMPPIN_PA0 ((uint32_t)0x00020000)
+#else
+ #define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00020000)
+#endif /* STM32F446xx */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Trigger_Definitions
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
-
-#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Filter_Definitions
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
* @{
*/
#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
@@ -213,17 +189,12 @@
#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4
consecutive samples at the active level */
#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active leve. */
-
-#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
- ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+ consecutive samples at the active level. */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
* @{
*/
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
@@ -242,20 +213,11 @@
with a frequency = RTCCLK / 512 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 256 */
-
-#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
* @{
*/
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
@@ -266,40 +228,29 @@
sampling during 4 RTCCLK cycles */
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
sampling during 8 RTCCLK cycles */
-
-#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
* @{
*/
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
-
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
* @{
*/
#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
-
-#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
- ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
/**
* @}
*/
-/** @defgroup RTCEx_Wakeup_Timer_Definitions
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
@@ -308,51 +259,33 @@
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
-
-#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
/**
* @}
*/
-/** @defgroup RTCEx_Digital_Calibration_Definitions
+/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
* @{
*/
#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000)
#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080)
-
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
- ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
-
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_period_Definitions
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration
period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration
period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration
period is 8s, else 2exp18 RTCCLK seconds */
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
* @{
*/
#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
@@ -360,49 +293,25 @@
with Y = 512, 256, 128 when X = 32, 16, 8 */
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0] */
-
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
- ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions
- * @{
- */
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
/**
* @}
*/
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
* @{
*/
#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
-
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
- ((SEL) == RTC_SHIFTADD1S_SET))
/**
* @}
*/
-/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-/**
- * @}
- */
- /** @defgroup RTCEx_Calib_Output_selection_Definitions
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
* @{
*/
#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
-
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
- ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
* @}
*/
@@ -412,6 +321,14 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+ * @{
+ */
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+ * @{
+ */
/**
* @brief Enable the RTC WakeUp Timer peripheral.
@@ -421,6 +338,162 @@
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
+ * @brief Disable the RTC Wake-up Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the RTC Wake-up Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Timestamp
+ * @{
+ */
+
+/**
* @brief Enable the RTC TimeStamp peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
@@ -428,13 +501,6 @@
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
/**
- * @brief Disable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
* @brief Disable the RTC TimeStamp peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
@@ -442,6 +508,242 @@
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TAMPER------------------------------------*/
+/** @defgroup RTCEx_Tamper RTC Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Disable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Enable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
+
+/**
+ * @brief Disable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1
+ * @arg RTC_IT_TAMP2
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+/**
+ * @}
+ */
+
+/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
+ * @{
+ */
+
+/**
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+/**
+ * @}
+ */
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Calibration
+ * @{
+ */
+
+/**
* @brief Enable the Coarse calibration process.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
@@ -484,108 +786,6 @@
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
/**
- * @brief Enable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Enable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Disable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TAMP1
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC TimeStamp's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
* @brief Get the selected RTC shift operation's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
@@ -594,39 +794,22 @@
* @retval None
*/
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
/**
- * @brief Clear the RTC Time Stamp's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @retval None
+ * @}
*/
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
+ * @}
*/
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Clear the RTC Wake Up timer's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @{
+ */
/* RTC TimeStamp and Tamper functions *****************************************/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
@@ -636,27 +819,39 @@
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @{
+ */
/* RTC Wake-up functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @{
+ */
/* Extension Control functions ************************************************/
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
@@ -668,11 +863,140 @@
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group4
+ * @{
+ */
/* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4) || \
+ ((BKP) == RTC_BKP_DR5) || \
+ ((BKP) == RTC_BKP_DR6) || \
+ ((BKP) == RTC_BKP_DR7) || \
+ ((BKP) == RTC_BKP_DR8) || \
+ ((BKP) == RTC_BKP_DR9) || \
+ ((BKP) == RTC_BKP_DR10) || \
+ ((BKP) == RTC_BKP_DR11) || \
+ ((BKP) == RTC_BKP_DR12) || \
+ ((BKP) == RTC_BKP_DR13) || \
+ ((BKP) == RTC_BKP_DR14) || \
+ ((BKP) == RTC_BKP_DR15) || \
+ ((BKP) == RTC_BKP_DR16) || \
+ ((BKP) == RTC_BKP_DR17) || \
+ ((BKP) == RTC_BKP_DR18) || \
+ ((BKP) == RTC_BKP_DR19))
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+#if defined (STM32F446xx)
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
+ ((PIN) == RTC_TAMPERPIN_PA0))
+#else
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
+ ((PIN) == RTC_TAMPERPIN_PI8))
+#endif /* STM32F446xx */
+
+#if defined (STM32F446xx)
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
+ ((PIN) == RTC_TIMESTAMPPIN_PA0))
+#else
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
+ ((PIN) == RTC_TIMESTAMPPIN_PI8))
+#endif /* STM32F446xx */
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
+ ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
+
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sai.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
@@ -47,7 +47,15 @@
-@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
inside the transmit and receive process.
-
+
+ [..]
+ (@) SAI Clock Source configuration is managed differently depending on the selected
+ STM32F4 devices :
+ (+@) For STM32F446xx devices, the configuration is managed through RCCEx_PeriphCLKConfig()
+ function in the HAL RCC drivers
+ (+@) For STM32F439xx/STM32F437xx/STM32F429xx/STM32F427xx devices, the configuration
+ is managed within HAL SAI drivers through HAL_SAI_Init() function using
+ ClockSource field of SAI_InitTypeDef structure.
[..]
(@) Make sure that either:
(+@) I2S PLL is configured or
@@ -124,7 +132,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -158,19 +166,38 @@
* @{
*/
-/** @defgroup SAI
+/** @defgroup SAI SAI
* @brief SAI HAL module driver
* @{
*/
#ifdef HAL_SAI_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
+/** @defgroup SAI_Private_Typedefs SAI Private Typedefs
+ * @{
+ */
+typedef enum {
+ SAI_MODE_DMA,
+ SAI_MODE_IT
+}SAI_ModeTypedef;
+/**
+ * @}
+ */
/* Private define ------------------------------------------------------------*/
+/** @defgroup SAI_Private_Constants SAI Private Constants
+ * @{
+ */
+#define SAI_FIFO_SIZE 8
+#define SAI_DEFAULT_TIMEOUT 4
+/**
+ * @}
+ */
+
/* SAI registers Masks */
-#define CR1_CLEAR_MASK ((uint32_t)0xFF07C010)
+#define CR1_CLEAR_MASK ((uint32_t)0xFF04C010)
#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000)
#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020)
@@ -178,19 +205,32 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
+
static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMAError(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
-/** @defgroup SAI_Private_Functions
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
* @{
*/
-/** @defgroup SAI_Group1 Initialization and de-initialization functions
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -222,6 +262,50 @@
*/
/**
+ * @brief Initializes the structure FrameInit, SlotInit and the low part of
+ * Init according to the specified parameters and call the function
+ * HAL_SAI_Init to initialize the SAI block.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol : one of the supported protocol @ref SAI_Protocol
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize
+ * the configuration information for SAI module.
+ * @param nbslot : Number of slot.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ switch(protocol)
+ {
+ case SAI_I2S_STANDARD :
+ case SAI_I2S_MSBJUSTIFIED :
+ case SAI_I2S_LSBJUSTIFIED :
+ status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
+ break;
+ case SAI_PCM_LONG :
+ case SAI_PCM_SHORT :
+ status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
+ break;
+ default :
+ status = HAL_ERROR;
+ break;
+ }
+
+ if(status == HAL_OK)
+ {
+ status = HAL_SAI_Init(hsai);
+ }
+
+ return status;
+}
+
+/**
* @brief Initializes the SAI according to the specified parameters
* in the SAI_InitTypeDef and create the associated handle.
* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
@@ -230,12 +314,10 @@
*/
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
{
- uint32_t tmpreg = 0;
- uint32_t tmpclock = 0, tmp2clock = 0;
- /* This variable used to store the VCO Input (value in Hz) */
- uint32_t vcoinput = 0;
+ uint32_t tmpclock = 0;
+
/* This variable used to store the SAI_CK_x (value in Hz) */
- uint32_t saiclocksource = 0;
+ uint32_t freq = 0;
/* Check the SAI handle allocation */
if(hsai == HAL_NULL)
@@ -244,8 +326,10 @@
}
/* Check the SAI Block parameters */
+ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+ assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
@@ -253,7 +337,9 @@
assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
- assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+ assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
+ assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
+ assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
/* Check the SAI Block Frame parameters */
assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
@@ -270,6 +356,9 @@
if(hsai->State == HAL_SAI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsai->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_SAI_MspInit(hsai);
}
@@ -277,179 +366,76 @@
hsai->State = HAL_SAI_STATE_BUSY;
/* Disable the selected SAI peripheral */
- __HAL_SAI_DISABLE(hsai);
-
- /* SAI Block Configuration ------------------------------------------------------------*/
- /* SAI Block_x CR1 Configuration */
- /* Get the SAI Block_x CR1 value */
- tmpreg = hsai->Instance->CR1;
- /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SAI_Block_x: Audio Protocol, Data Size, first transmitted bit, Clock strobing
- edge, Synchronization mode, Output drive, Master Divider and FIFO level */
- /* Set PRTCFG bits according to Protocol value */
- /* Set DS bits according to DataSize value */
- /* Set LSBFIRST bit according to FirstBit value */
- /* Set CKSTR bit according to ClockStrobing value */
- /* Set SYNCEN bit according to Synchro value */
- /* Set OUTDRIV bit according to OutputDrive value */
- /* Set NODIV bit according to NoDivider value */
- tmpreg |= (uint32_t)(hsai->Init.Protocol |
- hsai->Init.AudioMode |
- hsai->Init.DataSize |
- hsai->Init.FirstBit |
- hsai->Init.ClockStrobing |
- hsai->Init.Synchro |
- hsai->Init.OutputDrive |
- hsai->Init.NoDivider);
- /* Write to SAI_Block_x CR1 */
- hsai->Instance->CR1 = tmpreg;
+ SAI_Disable(hsai);
- /* SAI Block_x CR2 Configuration */
- /* Get the SAIBlock_x CR2 value */
- tmpreg = hsai->Instance->CR2;
- /* Clear FTH bits */
- tmpreg &= ~(SAI_xCR2_FTH);
- /* Configure the FIFO Level */
- /* Set FTH bits according to SAI_FIFOThreshold value */
- tmpreg |= (uint32_t)(hsai->Init.FIFOThreshold);
- /* Write to SAI_Block_x CR2 */
- hsai->Instance->CR2 = tmpreg;
-
- /* SAI Block_x Frame Configuration -----------------------------------------*/
- /* Get the SAI Block_x FRCR value */
- tmpreg = hsai->Instance->FRCR;
- /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */
- tmpreg &= FRCR_CLEAR_MASK;
- /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization
- Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */
- /* Set FRL bits according to SAI_FrameLength value */
- /* Set FSALL bits according to SAI_ActiveFrameLength value */
- /* Set FSDEF bit according to SAI_FSDefinition value */
- /* Set FSPOL bit according to SAI_FSPolarity value */
- /* Set FSOFF bit according to SAI_FSOffset value */
- tmpreg |= (uint32_t)((uint32_t)(hsai->FrameInit.FrameLength - 1) |
- hsai->FrameInit.FSOffset |
- hsai->FrameInit.FSDefinition |
- hsai->FrameInit.FSPolarity |
- (uint32_t)((hsai->FrameInit.ActiveFrameLength - 1) << 8));
-
- /* Write to SAI_Block_x FRCR */
- hsai->Instance->FRCR = tmpreg;
-
- /* SAI Block_x SLOT Configuration ------------------------------------------*/
- /* Get the SAI Block_x SLOTR value */
- tmpreg = hsai->Instance->SLOTR;
- /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */
- tmpreg &= SLOTR_CLEAR_MASK;
- /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in
- audio frame and slots activated in audio frame */
- /* Set FBOFF bits according to SAI_FirstBitOffset value */
- /* Set SLOTSZ bits according to SAI_SlotSize value */
- /* Set NBSLOT bits according to SAI_SlotNumber value */
- /* Set SLOTEN bits according to SAI_SlotActive value */
- tmpreg |= (uint32_t)(hsai->SlotInit.FirstBitOffset |
- hsai->SlotInit.SlotSize |
- hsai->SlotInit.SlotActive |
- (uint32_t)((hsai->SlotInit.SlotNumber - 1) << 8));
-
- /* Write to SAI_Block_x SLOTR */
- hsai->Instance->SLOTR = tmpreg;
-
- /* SAI Block_x Clock Configuration -----------------------------------------*/
- /* Check the Clock parameters */
- assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
-
- /* SAI Block clock source selection */
- if(hsai->Instance == SAI1_Block_A)
- {
- __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
- }
- else
- {
- __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2));
- }
-
- /* VCO Input Clock value calculation */
- if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
- {
- /* In Case the PLL Source is HSI (Internal Clock) */
- vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
- }
- else
- {
- /* In Case the PLL Source is HSE (External Clock) */
- vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
- }
-
- /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
- if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
- {
- /* Configure the PLLI2S division factor */
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
- saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+ /* SAI Block Synchro Configuration -----------------------------------------*/
+ SAI_BlockSynchroConfig(hsai);
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
- tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
- saiclocksource = saiclocksource/(tmpreg);
-
- }
- else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
- {
- /* Configure the PLLI2S division factor */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
- /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
- /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
- saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
- saiclocksource = saiclocksource/(tmpreg);
- }
- else /* sConfig->ClockSource == SAI_CLKSource_Ext */
- {
- /* Enable the External Clock selection */
- __HAL_RCC_I2SCLK(RCC_I2SCLKSOURCE_EXT);
-
- saiclocksource = EXTERNAL_CLOCK_VALUE;
- }
-
/* Configure Master Clock using the following formula :
MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
MCKDIV[3:0] = SAI_CK_x / FS * 512 */
- if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_ENABLED)
+ if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
{
+ /* Get SAI clock source based on Source clock selection from RCC */
+ freq = SAI_GetInputClock(hsai);
+
/* (saiclocksource x 10) to keep Significant digits */
- tmpclock = (((saiclocksource * 10) / ((hsai->Init.AudioFrequency) * 512)));
-
- /* Get the result of modulo division */
- tmp2clock = (tmpclock % 10);
+ tmpclock = (((freq * 10) / ((hsai->Init.AudioFrequency) * 512)));
- /* Round result to the nearest integer*/
- if (tmp2clock > 8)
+ hsai->Init.Mckdiv = tmpclock / 10;
+
+ /* Round result to the nearest integer */
+ if((tmpclock % 10) > 8)
{
- tmpclock = ((tmpclock / 10) + 1);
+ hsai->Init.Mckdiv+= 1;
}
- else
- {
- tmpclock = (tmpclock / 10);
- }
- /*Set MCKDIV value in CR1 register*/
- hsai->Instance->CR1 |= (tmpclock << 20);
-
}
+ /* SAI Block Configuration ------------------------------------------------------------*/
+ /* SAI CR1 Configuration */
+ hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
+ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
+ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
+ SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
+
+ hsai->Instance->CR1|= (hsai->Init.AudioMode | hsai->Init.Protocol | \
+ hsai->Init.DataSize | hsai->Init.FirstBit | \
+ hsai->Init.ClockStrobing | hsai->Init.Synchro | \
+ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
+ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | hsai->Init.CompandingMode);
+
+ /* SAI CR2 Configuration */
+ hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP);
+ hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
+
+
+ /* SAI Frame Configuration -----------------------------------------*/
+ hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+ SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF));
+ hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) |
+ hsai->FrameInit.FSOffset |
+ hsai->FrameInit.FSDefinition |
+ hsai->FrameInit.FSPolarity |
+ ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
+
+ /* SAI Block_x SLOT Configuration ------------------------------------------*/
+ /* This register has no meaning in AC97 and SPDIF audio protocol */
+ hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
+ SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
+
+ hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize
+ | hsai->SlotInit.SlotActive | ((hsai->SlotInit.SlotNumber - 1) << 8);
+
/* Initialise the error code */
hsai->ErrorCode = HAL_SAI_ERROR_NONE;
-
+
/* Initialize the SAI state */
hsai->State= HAL_SAI_STATE_READY;
-
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
return HAL_OK;
}
@@ -469,6 +455,16 @@
hsai->State = HAL_SAI_STATE_BUSY;
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0;
+ hsai->Instance->CLRFR = 0xFFFFFFFF;
+
+ /* Disable the SAI */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_SAI_MspDeInit(hsai);
@@ -514,7 +510,7 @@
* @}
*/
-/** @defgroup SAI_Group2 IO operation functions
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -568,7 +564,7 @@
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = 0;
@@ -583,22 +579,45 @@
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_TX;
-
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->pBuffPtr = pData;
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
+ /* fill the fifo with data before to enabled the SAI */
+ SAI_FillFifo(hsai);
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
- while(Size > 0)
+ while(hsai->XferCount > 0)
{
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the FIFO to be empty */
- while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET)
+ /* Write data if the FIFO is not full */
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
{
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 2;
+ }
+ else
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 4;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
@@ -616,11 +635,9 @@
return HAL_TIMEOUT;
}
}
- }
- hsai->Instance->DR = (*pData++);
- Size--;
+ }
}
-
+
hsai->State = HAL_SAI_STATE_READY;
/* Process Unlocked */
@@ -643,10 +660,10 @@
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = 0;
-
+
if((pData == HAL_NULL ) || (Size == 0))
{
return HAL_ERROR;
@@ -658,23 +675,44 @@
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_RX;
-
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
+
/* Receive data */
- while(Size > 0)
+ while(hsai->XferCount > 0)
{
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until RXNE flag is set */
- while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET)
+
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
{
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+ hsai->pBuffPtr+= 2;
+ }
+ else
+ {
+ *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+ hsai->pBuffPtr+= 4;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
@@ -693,11 +731,8 @@
}
}
}
-
- (*pData++) = hsai->Instance->DR;
- Size--;
}
-
+
hsai->State = HAL_SAI_STATE_READY;
/* Process Unlocked */
@@ -719,70 +754,54 @@
* @param Size: Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
-{
- if(hsai->State == HAL_SAI_STATE_READY)
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if(hsai->State == HAL_SAI_STATE_READY)
{
if((pData == HAL_NULL) || (Size == 0))
{
return HAL_ERROR;
}
- hsai->pTxBuffPtr = pData;
- hsai->TxXferSize = Size;
- hsai->TxXferCount = Size;
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
/* Process Locked */
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_TX;
- /* Transmit data */
- hsai->Instance->DR = (*hsai->pTxBuffPtr++);
- hsai->TxXferCount--;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
+ }
/* Enable FRQ and OVRUDR interrupts */
- __HAL_SAI_ENABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
-
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
+ /* Fill the fifo before starting the communication */
+ SAI_FillFifo(hsai);
+
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
-
- return HAL_OK;
- }
- else if(hsai->State == HAL_SAI_STATE_BUSY_TX)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Transmit data */
- hsai->Instance->DR = (*hsai->pTxBuffPtr++);
-
- hsai->TxXferCount--;
-
- if(hsai->TxXferCount == 0)
- {
- /* Disable FREQ and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
-
- hsai->State = HAL_SAI_STATE_READY;
-
- HAL_SAI_TxCpltCallback(hsai);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(hsai);
return HAL_OK;
}
-
else
{
return HAL_BUSY;
@@ -797,8 +816,9 @@
* @param Size: Amount of data to be received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
+
if(hsai->State == HAL_SAI_STATE_READY)
{
if((pData == HAL_NULL) || (Size == 0))
@@ -806,17 +826,29 @@
return HAL_ERROR;
}
- hsai->pRxBuffPtr = pData;
- hsai->RxXferSize = Size;
- hsai->RxXferCount = Size;
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
/* Process Locked */
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_RX;
-
+
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
+ }
/* Enable TXE and OVRUDR interrupts */
- __HAL_SAI_ENABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
@@ -830,31 +862,6 @@
return HAL_OK;
}
- else if(hsai->State == HAL_SAI_STATE_BUSY_RX)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Receive data */
- (*hsai->pRxBuffPtr++) = hsai->Instance->DR;
-
- hsai->RxXferCount--;
-
- if(hsai->RxXferCount == 0)
- {
- /* Disable TXE and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
-
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_RxCpltCallback(hsai);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
-
else
{
return HAL_BUSY;
@@ -875,7 +882,6 @@
/* Pause the audio file playing by disabling the SAI DMA requests */
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hsai);
@@ -896,9 +902,8 @@
/* Enable the SAI DMA requests */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
/* If the SAI peripheral is still not enabled, enable it */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
@@ -912,7 +917,7 @@
/**
* @brief Stops the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -936,7 +941,7 @@
}
/* Disable SAI peripheral */
- __HAL_SAI_DISABLE(hsai);
+ SAI_Disable(hsai);
hsai->State = HAL_SAI_STATE_READY;
@@ -945,6 +950,47 @@
return HAL_OK;
}
+
+/**
+ * @brief Abort the current transfer and disbaled the SAI.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
+{
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Abort the SAI DMA Tx Stream */
+ if(hsai->hdmatx != HAL_NULL)
+ {
+ HAL_DMA_Abort(hsai->hdmatx);
+ }
+ /* Abort the SAI DMA Rx Stream */
+ if(hsai->hdmarx != HAL_NULL)
+ {
+ HAL_DMA_Abort(hsai->hdmarx);
+ }
+
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0;
+ hsai->Instance->CLRFR = 0xFFFFFFFF;
+
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
/**
* @brief Transmits an amount of data in no-blocking mode with DMA.
* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
@@ -953,52 +999,55 @@
* @param Size: Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
-
+
if((pData == HAL_NULL) || (Size == 0))
{
return HAL_ERROR;
}
-
+
if(hsai->State == HAL_SAI_STATE_READY)
{
- hsai->pTxBuffPtr = pData;
- hsai->TxXferSize = Size;
- hsai->TxXferCount = Size;
-
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+
/* Process Locked */
__HAL_LOCK(hsai);
-
+
hsai->State = HAL_SAI_STATE_BUSY_TX;
-
- /* Set the SAI Tx DMA Half transfert complete callback */
+
+ /* Set the SAI Tx DMA Half transfer complete callback */
hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
-
+
/* Set the SAI TxDMA transfer complete callback */
hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
-
+
/* Set the DMA error callback */
hsai->hdmatx->XferErrorCallback = SAI_DMAError;
-
+
/* Enable the Tx DMA Stream */
tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->TxXferSize);
-
+ HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize);
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
/* Enable SAI Tx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsai);
-
+
return HAL_OK;
}
else
@@ -1015,7 +1064,7 @@
* @param Size: Amount of data to be received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
@@ -1023,44 +1072,47 @@
{
return HAL_ERROR;
}
-
+
if(hsai->State == HAL_SAI_STATE_READY)
{
- hsai->pRxBuffPtr = pData;
- hsai->RxXferSize = Size;
- hsai->RxXferCount = Size;
-
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+
/* Process Locked */
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_RX;
-
- /* Set the SAI Rx DMA Half transfert complete callback */
+
+ /* Set the SAI Rx DMA Half transfer complete callback */
hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
-
- /* Set the SAI Rx DMA transfert complete callback */
+
+ /* Set the SAI Rx DMA transfer complete callback */
hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
-
+
/* Set the DMA error callback */
hsai->hdmarx->XferErrorCallback = SAI_DMAError;
-
+
/* Enable the Rx DMA Stream */
tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->RxXferSize);
-
+ HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize);
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
/* Enable SAI Rx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsai);
-
+
return HAL_OK;
}
else
@@ -1070,66 +1122,158 @@
}
/**
+ * @brief Enable the tx mute mode.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param val : value sent during the mute @ref SAI_Block_Mute_Value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
+{
+ assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
+
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disable the tx mute mode.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enable the rx mute detection.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param callback : function called when the mute is detected
+ * @param counter : number a data before mute detection max 63.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
+{
+ assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
+
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mute counter */
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << 6));
+ hsai->mutecallback = callback;
+ /* enable the IT interrupt */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disable the rx mute detection.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mutecallback to NULL */
+ hsai->mutecallback = (SAIcallback)NULL;
+ /* enable the IT interrupt */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
* @brief This function handles SAI interrupt request.
* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
-{
- uint32_t tmp1 = 0, tmp2 = 0;
-
- if(hsai->State == HAL_SAI_STATE_BUSY_RX)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
{
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_FREQ);
- /* SAI in mode Receiver --------------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ uint32_t tmpFlag = hsai->Instance->SR;
+ uint32_t tmpItSource = hsai->Instance->IMR;
+
+ if(((tmpFlag & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((tmpItSource & SAI_IT_FREQ) == SAI_IT_FREQ))
+ {
+ hsai->InterruptServiceRoutine(hsai);
+ }
+
+ /* check the flag only if one of them is set */
+ if(tmpFlag != 0x00000000)
{
- HAL_SAI_Receive_IT(hsai, HAL_NULL, 0);
- }
+ /* SAI Overrun error interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((tmpItSource & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+ {
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+ /* Change the SAI error code */
+ hsai->ErrorCode = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+ /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+
+ /* SAI mutedet interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((tmpItSource & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+ {
+ /* Clear the SAI mutedet flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+ /* call the call back function */
+ if(hsai->mutecallback != (SAIcallback)NULL)
+ {
+ /* inform the user that an RX mute event has been detected */
+ hsai->mutecallback();
+ }
+ }
+
+ /* SAI AFSDET interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((tmpItSource & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_AFSDET;
+ HAL_SAI_Abort(hsai);
+ HAL_SAI_ErrorCallback(hsai);
+ }
+
+ /* SAI LFSDET interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((tmpItSource & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_LFSDET;
+ HAL_SAI_Abort(hsai);
+ HAL_SAI_ErrorCallback(hsai);
+ }
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_FLAG_OVRUDR);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_OVRUDR);
- /* SAI Overrun error interrupt occurred ----------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- /* Change the SAI error code */
- hsai->ErrorCode = HAL_SAI_ERROR_OVR;
-
- /* Clear the SAI Overrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
- /* Set the SAI state ready to be able to start again the process */
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_ErrorCallback(hsai);
+ /* SAI WCKCFG interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((tmpItSource & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_WCKCFG;
+ HAL_SAI_Abort(hsai);
+ HAL_SAI_ErrorCallback(hsai);
+ }
}
}
-
- if(hsai->State == HAL_SAI_STATE_BUSY_TX)
- {
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_FREQ);
- /* SAI in mode Transmitter -----------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- HAL_SAI_Transmit_IT(hsai, HAL_NULL, 0);
- }
-
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_FLAG_OVRUDR);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_OVRUDR);
- /* SAI Underrun error interrupt occurred ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- /* Change the SAI error code */
- hsai->ErrorCode = HAL_SAI_ERROR_UDR;
-
- /* Clear the SAI Underrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
- /* Set the SAI state ready to be able to start again the process */
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_ErrorCallback(hsai);
- }
- }
}
/**
@@ -1154,7 +1298,7 @@
__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SAI_TxHalfCpltCallback could be implenetd in the user file
+ the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
*/
}
@@ -1180,7 +1324,7 @@
__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SAI_RxCpltCallback could be implenetd in the user file
+ the HAL_SAI_RxCpltCallback could be implemented in the user file
*/
}
@@ -1202,7 +1346,7 @@
*/
-/** @defgroup SAI_Group3 Peripheral State functions
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -1243,6 +1387,398 @@
*/
/**
+ * @brief Initializes the SAI I2S protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol : one of the supported protocol
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize
+ * the configuration information for SAI module.
+ * @param nbslot : number of slot minimum value is 2 and max is 16.
+ * the value must be a multiple of 2.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+ hsai->SlotInit.FirstBitOffset = 0;
+ hsai->SlotInit.SlotNumber = nbslot;
+
+ /* in IS2 the number of slot must be even */
+ if((nbslot & 0x1) != 0 )
+ {
+ return HAL_ERROR;
+ }
+
+ switch(protocol)
+ {
+ case SAI_I2S_STANDARD :
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ break;
+ case SAI_I2S_MSBJUSTIFIED :
+ case SAI_I2S_LSBJUSTIFIED :
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ /* Frame definition */
+ hsai->Init.DataSize = 0xFFFFFFFF;
+ switch(datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32*(nbslot/2);
+ hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ if(hsai->Init.DataSize == 0xFFFFFFFF)
+ {
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ }
+ break;
+ case SAI_PROTOCOL_DATASIZE_24BIT:
+ if(hsai->Init.DataSize == 0xFFFFFFFF)
+ {
+ hsai->Init.DataSize = SAI_DATASIZE_24;
+ }
+ break;
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ if(hsai->Init.DataSize == 0xFFFFFFFF)
+ {
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ }
+ hsai->FrameInit.FrameLength = 64*(nbslot/2);
+ hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ if(protocol == SAI_I2S_LSBJUSTIFIED)
+ {
+ if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+ {
+ hsai->SlotInit.FirstBitOffset = 16;
+ }
+ if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+ {
+ hsai->SlotInit.FirstBitOffset = 8;
+ }
+ }
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the SAI PCM protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol : one of the supported protocol
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param nbslot : number of slot minimum value is 1 and the max is 16.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME;
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ hsai->SlotInit.FirstBitOffset = 0;
+ hsai->SlotInit.SlotNumber = nbslot;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+
+ switch(protocol)
+ {
+ case SAI_PCM_SHORT :
+ hsai->FrameInit.ActiveFrameLength = 1;
+ break;
+ case SAI_PCM_LONG :
+ hsai->FrameInit.ActiveFrameLength = 13;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ switch(datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 16 * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32 * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ hsai->FrameInit.FrameLength = 32 * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Fill the fifo
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
+{
+ /* fill the fifo with data before to enabled the SAI */
+ while((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+ {
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 2;
+ }
+ else
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 4;
+ }
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief return the interrupt flag to set according the SAI setup
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param mode : SAI_MODE_DMA or SAI_MODE_IT
+ * @retval the list of the IT flag to enable
+ */
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
+{
+ uint32_t tmpIT = SAI_IT_OVRUDR;
+
+ if(mode == SAI_MODE_IT)
+ {
+ tmpIT|= SAI_IT_FREQ;
+ }
+
+ if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
+ }
+ else
+ {
+ /* hsai has been configured in master mode */
+ tmpIT|= SAI_IT_WCKCFG;
+ }
+ return tmpIT;
+}
+
+/**
+ * @brief disabled the SAI and wait the disabling
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
+{
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_SAI_DISABLE(hsai);
+ while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+ status = HAL_TIMEOUT;
+
+ /* Change the SAI state */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode 8Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Write data on DR register */
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ hsai->XferCount--;
+
+ /* Handle the end of the transmission */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 16Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Write data on DR register */
+ hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
+ hsai->pBuffPtr+=2;
+ hsai->XferCount--;
+
+ /* Handle the end of the transmission */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 32Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Write data on DR register */
+ hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
+ hsai->pBuffPtr+=4;
+ hsai->XferCount--;
+
+ /* Handle the end of the transmission */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode 8Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 16Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
+ hsai->pBuffPtr+=2;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 32Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
+ hsai->pBuffPtr+=4;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+
+/**
* @brief DMA SAI transmit process complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
@@ -1253,18 +1789,17 @@
uint32_t tickstart = 0;
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
-
+
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- hsai->TxXferCount = 0;
- hsai->RxXferCount = 0;
+ hsai->XferCount = 0;
/* Disable SAI Tx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
/* Set timeout: 10 is the max delay to send the remaining data in the SAI FIFO */
/* Wait until FIFO is empty */
while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FLVL) != RESET)
@@ -1280,6 +1815,9 @@
}
}
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
hsai->State= HAL_SAI_STATE_READY;
}
HAL_SAI_TxCpltCallback(hsai);
@@ -1311,7 +1849,10 @@
{
/* Disable Rx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
- hsai->RxXferCount = 0;
+ hsai->XferCount = 0;
+
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
hsai->State = HAL_SAI_STATE_READY;
}
@@ -1339,19 +1880,22 @@
static void SAI_DMAError(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Stop the DMA transfer */
+ HAL_SAI_DMAStop(hsai);
+
/* Set the SAI state ready to be able to start again the process */
hsai->State= HAL_SAI_STATE_READY;
HAL_SAI_ErrorCallback(hsai);
- hsai->TxXferCount = 0;
- hsai->RxXferCount = 0;
+ hsai->XferCount = 0;
}
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_SAI_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sai.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,69 +43,107 @@
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/** @addtogroup SAI
* @{
*/
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Types SAI Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SAI_STATE_RESET = 0x00, /*!< SAI not yet initialized or disabled */
+ HAL_SAI_STATE_READY = 0x01, /*!< SAI initialized and ready for use */
+ HAL_SAI_STATE_BUSY = 0x02, /*!< SAI internal process is ongoing */
+ HAL_SAI_STATE_BUSY_TX = 0x12, /*!< Data transmission process is ongoing */
+ HAL_SAI_STATE_BUSY_RX = 0x22, /*!< Data reception process is ongoing */
+ HAL_SAI_STATE_TIMEOUT = 0x03, /*!< SAI timeout state */
+ HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */
+}HAL_SAI_StateTypeDef;
-/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief SAI Callback prototype
+ */
+typedef void (*SAIcallback)(void);
/**
* @brief SAI Init Structure definition
*/
typedef struct
{
+ uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
+ This parameter can be a value of @ref SAI_Block_Mode */
+
+ uint32_t Synchro; /*!< Specifies SAI Block synchronization
+ This parameter can be a value of @ref SAI_Block_Synchronization */
+
+ uint32_t SynchroExt; /*!< Specifies SAI Block synchronization, this setup is common
+ for BLOCKA and BLOCKB
+ This parameter can be a value of @ref SAI_Block_SyncExt */
+
+ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
+ This parameter can be a value of @ref SAI_Block_Output_Drive
+ @note this value has to be set before enabling the audio block
+ but after the audio block configuration. */
+
+ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
+ This parameter can be a value of @ref SAI_Block_NoDivider
+ @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+ should be aligned to a number equal to a power of 2, from 8 to 256.
+ If bit NODIV in the SAI_xCR1 register is set, the frame length can
+ take any of the values without constraint since the input clock of
+ the audio block should be equal to the bit clock.
+ There is no MCLK_x clock which can be output. */
+
+ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
+ This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+ uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
+ This parameter is not used for STM32F446xx devices. */
+
+ uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
+ This parameter can be a value of @ref SAI_Audio_Frequency */
+
+ uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
+ AudioFrequency the user choice
+ This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+
+ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
+ This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
+
+ uint32_t CompandingMode; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_Block_Companding_Mode */
+
+ uint32_t TriState; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_TRIState_Management */
+
+ /* This part of the structure is automatically filled if your are using the high level intialisation
+ function HAL_SAI_InitProtocol */
+
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
- This parameter can be a value of @ref SAI_Block_Protocol */
-
- uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
- This parameter can be a value of @ref SAI_Block_Mode */
-
+ This parameter can be a value of @ref SAI_Block_Protocol */
+
uint32_t DataSize; /*!< Specifies the SAI Block data size.
- This parameter can be a value of @ref SAI_Block_Data_Size */
+ This parameter can be a value of @ref SAI_Block_Data_Size */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+ This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
- This parameter can be a value of @ref SAI_Block_Clock_Strobing */
-
- uint32_t Synchro; /*!< Specifies SAI Block synchronization
- This parameter can be a value of @ref SAI_Block_Synchronization */
-
- uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
- This parameter can be a value of @ref SAI_Block_Output_Drive
- @note this value has to be set before enabling the audio block
- but after the audio block configuration. */
-
- uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
- This parameter can be a value of @ref SAI_Block_NoDivider
- @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
- should be aligned to a number equal to a power of 2, from 8 to 256.
- If bit NODIV in the SAI_xCR1 register is set, the frame length can
- take any of the values without constraint since the input clock of
- the audio block should be equal to the bit clock.
- There is no MCLK_x clock which can be output. */
-
- uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
- This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
-
- uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
- This parameter can be a value of @ref SAI_Clock_Source
- @note: If ClockSource is equal to SAI_CLKSource_Ext, the PLLI2S
- and PLLSAI divisions factors will be ignored. */
-
- uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
- This parameter can be a value of @ref SAI_Audio_Frequency */
-
+ This parameter can be a value of @ref SAI_Block_Clock_Strobing */
}SAI_InitTypeDef;
/**
@@ -157,24 +195,9 @@
}SAI_SlotInitTypeDef;
/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_SAI_STATE_RESET = 0x00, /*!< SAI not yet initialized or disabled */
- HAL_SAI_STATE_READY = 0x01, /*!< SAI initialized and ready for use */
- HAL_SAI_STATE_BUSY = 0x02, /*!< SAI internal process is ongoing */
- HAL_SAI_STATE_BUSY_TX = 0x12, /*!< Data transmission process is ongoing */
- HAL_SAI_STATE_BUSY_RX = 0x22, /*!< Data reception process is ongoing */
- HAL_SAI_STATE_TIMEOUT = 0x03, /*!< SAI timeout state */
- HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */
-
-}HAL_SAI_StateTypeDef;
-
-/**
* @brief SAI handle Structure definition
*/
-typedef struct
+typedef struct __SAI_HandleTypeDef
{
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
@@ -184,22 +207,20 @@
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
- uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SAI Tx transfer size */
-
- uint16_t TxXferCount; /*!< SAI Tx transfer counter */
+ uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
- uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */
+ uint16_t XferSize; /*!< SAI transfer size */
- uint16_t RxXferSize; /*!< SAI Rx transfer size */
-
- uint16_t RxXferCount; /*!< SAI Rx transfer counter */
+ uint16_t XferCount; /*!< SAI transfer counter */
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+ SAIcallback mutecallback;/*!< SAI mute callback */
+
+ void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
+
HAL_LockTypeDef Lock; /*!< SAI locking object */
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
@@ -207,37 +228,77 @@
__IO uint32_t ErrorCode; /*!< SAI Error code */
}SAI_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SAI_Exported_Constants
+/** @defgroup SAI_Exported_Constants SAI Exported Constants
+ * @{
+ */
+
+/** @defgroup SAI_Error_Code SAI Error Code
* @{
*/
-/** @defgroup SAI Error Code
+#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004) /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008) /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010) /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020) /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
* @{
- */
-#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */
-#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
-#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+ */
+#define SAI_SYNCEXT_DISABLE ((uint32_t)0x00000000)
+#define SAI_SYNCEXT_IN_ENABLE ((uint32_t)0x00000001)
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE ((uint32_t)0x00000002)
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE ((uint32_t)0x00000004)
/**
* @}
*/
-/** @defgroup SAI_Clock_Source
+/** @defgroup SAI_Protocol SAI Supported protocol
* @{
*/
-#define SAI_CLKSOURCE_PLLSAI ((uint32_t)RCC_SAIACLKSOURCE_PLLSAI)
-#define SAI_CLKSOURCE_PLLI2S ((uint32_t)RCC_SAIACLKSOURCE_PLLI2S)
-#define SAI_CLKSOURCE_EXT ((uint32_t)RCC_SAIACLKSOURCE_EXT)
-
-#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
- ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
- ((SOURCE) == SAI_CLKSOURCE_EXT))
+#define SAI_I2S_STANDARD ((uint32_t)0x00000000)
+#define SAI_I2S_MSBJUSTIFIED ((uint32_t)0x00000001)
+#define SAI_I2S_LSBJUSTIFIED ((uint32_t)0x00000002)
+#define SAI_PCM_LONG ((uint32_t)0x00000004)
+#define SAI_PCM_SHORT ((uint32_t)0x00000008)
/**
* @}
*/
-/** @defgroup SAI_Audio_Frequency
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+ * @{
+ */
+#define SAI_PROTOCOL_DATASIZE_16BIT ((uint32_t)0x00000000)
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED ((uint32_t)0x00000001)
+#define SAI_PROTOCOL_DATASIZE_24BIT ((uint32_t)0x00000002)
+#define SAI_PROTOCOL_DATASIZE_32BIT ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Clock_Source SAI Clock Source
+ * @{
+ */
+#define SAI_CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define SAI_CLKSOURCE_PLLI2S ((uint32_t)0x00100000)
+#define SAI_CLKSOURCE_EXT ((uint32_t)0x00200000)
+#define SAI_CLKSOURCE_NA ((uint32_t)0x00400000) /*!< No applicable for STM32F446xx */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
* @{
*/
#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000)
@@ -248,217 +309,144 @@
#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)
#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)
#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)
-#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
+#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
+#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0)
-#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_8K))
/**
* @}
*/
-/** @defgroup SAI_Block_Mode
+/** @defgroup SAI_Block_Mode SAI Block Mode
* @{
*/
#define SAI_MODEMASTER_TX ((uint32_t)0x00000000)
-#define SAI_MODEMASTER_RX ((uint32_t)0x00000001)
-#define SAI_MODESLAVE_TX ((uint32_t)0x00000002)
-#define SAI_MODESLAVE_RX ((uint32_t)0x00000003)
-#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
- ((MODE) == SAI_MODEMASTER_RX) || \
- ((MODE) == SAI_MODESLAVE_TX) || \
- ((MODE) == SAI_MODESLAVE_RX))
+#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
+#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
+#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
+
/**
* @}
*/
-/** @defgroup SAI_Block_Protocol
+/** @defgroup SAI_Block_Protocol SAI Block Protocol
* @{
*/
-
#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000)
+#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
-#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
- ((PROTOCOL) == SAI_AC97_PROTOCOL))
/**
* @}
*/
-/** @defgroup SAI_Block_Data_Size
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size
* @{
*/
-#define SAI_DATASIZE_8 ((uint32_t)0x00000040)
-#define SAI_DATASIZE_10 ((uint32_t)0x00000060)
-#define SAI_DATASIZE_16 ((uint32_t)0x00000080)
-#define SAI_DATASIZE_20 ((uint32_t)0x000000A0)
-#define SAI_DATASIZE_24 ((uint32_t)0x000000C0)
-#define SAI_DATASIZE_32 ((uint32_t)0x000000E0)
+#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
+#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
+#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
+#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
-#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
- ((DATASIZE) == SAI_DATASIZE_10) || \
- ((DATASIZE) == SAI_DATASIZE_16) || \
- ((DATASIZE) == SAI_DATASIZE_20) || \
- ((DATASIZE) == SAI_DATASIZE_24) || \
- ((DATASIZE) == SAI_DATASIZE_32))
/**
* @}
*/
-/** @defgroup SAI_Block_MSB_LSB_transmission
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
* @{
*/
-
#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
-#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
- ((BIT) == SAI_FIRSTBIT_LSB))
/**
* @}
*/
-/** @defgroup SAI_Block_Clock_Strobing
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
* @{
*/
#define SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000)
#define SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)SAI_xCR1_CKSTR)
-#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
- ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
/**
* @}
*/
-/** @defgroup SAI_Block_Synchronization
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
* @{
*/
#define SAI_ASYNCHRONOUS ((uint32_t)0x00000000)
#define SAI_SYNCHRONOUS ((uint32_t)SAI_xCR1_SYNCEN_0)
-
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS))
-/**
- * @}
- */
+#define SAI_SYNCHRONOUS_EXT ((uint32_t)SAI_xCR1_SYNCEN_1)
-/** @defgroup SAI_Block_Output_Drive
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLED ((uint32_t)0x00000000)
-#define SAI_OUTPUTDRIVE_ENABLED ((uint32_t)SAI_xCR1_OUTDRIV)
-
-#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLED) || \
- ((DRIVE) == SAI_OUTPUTDRIVE_ENABLED))
/**
* @}
*/
-/** @defgroup SAI_Block_NoDivider
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
* @{
*/
-#define SAI_MASTERDIVIDER_ENABLED ((uint32_t)0x00000000)
-#define SAI_MASTERDIVIDER_DISABLED ((uint32_t)SAI_xCR1_NODIV)
+#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000)
+#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
+
+/**
+ * @}
+ */
-#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLED) || \
- ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLED))
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
+ * @{
+ */
+#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000)
+#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)
+
/**
* @}
*/
-/** @defgroup SAI_Block_Master_Divider
- * @{
- */
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Frame_Length
- * @{
- */
-#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Active_FrameLength
- * @{
- */
-#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
-/**
- * @}
- */
-/** @defgroup SAI_Block_FS_Definition
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
* @{
*/
#define SAI_FS_STARTFRAME ((uint32_t)0x00000000)
#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
-#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
- ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
/**
* @}
*/
-/** @defgroup SAI_Block_FS_Polarity
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
* @{
*/
#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000)
#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO)
-#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
- ((POLARITY) == SAI_FS_ACTIVE_HIGH))
/**
* @}
*/
-/** @defgroup SAI_Block_FS_Offset
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
* @{
*/
#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000)
#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
-#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
- ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
/**
* @}
*/
-/** @defgroup SAI_Block_Slot_FirstBit_Offset
- * @{
- */
-#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
-/**
- * @}
- */
- /** @defgroup SAI_Block_Slot_Size
+ /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
* @{
*/
#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000)
#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
-
-#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
- ((SIZE) == SAI_SLOTSIZE_16B) || \
- ((SIZE) == SAI_SLOTSIZE_32B))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Slot_Number
- * @{
- */
-#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
/**
* @}
*/
-/** @defgroup SAI_Block_Slot_Active
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
* @{
*/
#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)
@@ -480,93 +468,68 @@
#define SAI_SLOTACTIVE_15 ((uint32_t)0x80000000)
#define SAI_SLOTACTIVE_ALL ((uint32_t)0xFFFF0000)
-#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
+ * @{
+ */
+#define SAI_STEREOMODE ((uint32_t)0x00000000)
+#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
/**
* @}
*/
-/** @defgroup SAI_Mono_Stereo_Mode
- * @{
- */
-#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
-#define SAI_STREOMODE ((uint32_t)0x00000000)
-
-#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
- ((MODE) == SAI_STREOMODE))
-/**
- * @}
- */
-
-/** @defgroup SAI_TRIState_Management
+/** @defgroup SAI_TRIState_Management SAI TRIState Management
* @{
*/
#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000)
#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
-#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
- ((STATE) == SAI_OUTPUT_RELEASED))
/**
* @}
*/
-/** @defgroup SAI_Block_Fifo_Threshold
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
* @{
*/
#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)
-#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)0x00000001)
-#define SAI_FIFOTHRESHOLD_HF ((uint32_t)0x00000002)
-#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)0x00000003)
-#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)0x00000004)
+#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)SAI_xCR2_FTH_0)
+#define SAI_FIFOTHRESHOLD_HF ((uint32_t)SAI_xCR2_FTH_1)
+#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)SAI_xCR2_FTH_2)
-#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
/**
* @}
*/
-/** @defgroup SAI_Block_Companding_Mode
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
* @{
*/
#define SAI_NOCOMPANDING ((uint32_t)0x00000000)
-#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)0x00008000)
-#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)0x0000C000)
-#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)0x0000A000)
-#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)0x0000E000)
+#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)SAI_xCR2_COMP_1)
+#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
+#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
+#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
-#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
- ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
- ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
- ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
- ((MODE) == SAI_ALAW_2CPL_COMPANDING))
/**
* @}
*/
-/** @defgroup SAI_Block_Mute_Value
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
* @{
*/
#define SAI_ZERO_VALUE ((uint32_t)0x00000000)
#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
-#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
- ((VALUE) == SAI_LAST_SENT_VALUE))
/**
* @}
*/
-/** @defgroup SAI_Block_Mute_Frame_Counter
- * @{
- */
-#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
-/**
- * @}
- */
-/** @defgroup SAI_Block_Interrupts_Definition
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
* @{
*/
#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
@@ -577,18 +540,11 @@
#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
-#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \
- ((IT) == SAI_IT_MUTEDET) || \
- ((IT) == SAI_IT_WCKCFG) || \
- ((IT) == SAI_IT_FREQ) || \
- ((IT) == SAI_IT_CNRDY) || \
- ((IT) == SAI_IT_AFSDET) || \
- ((IT) == SAI_IT_LFSDET))
/**
* @}
*/
-/** @defgroup SAI_Block_Flags_Definition
+/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
* @{
*/
#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
@@ -599,51 +555,35 @@
#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
-#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
- ((FLAG) == SAI_FLAG_MUTEDET) || \
- ((FLAG) == SAI_FLAG_WCKCFG) || \
- ((FLAG) == SAI_FLAG_FREQ) || \
- ((FLAG) == SAI_FLAG_CNRDY) || \
- ((FLAG) == SAI_FLAG_AFSDET) || \
- ((FLAG) == SAI_FLAG_LFSDET))
-
-#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
- ((FLAG) == SAI_FLAG_MUTEDET) || \
- ((FLAG) == SAI_FLAG_WCKCFG) || \
- ((FLAG) == SAI_FLAG_FREQ) || \
- ((FLAG) == SAI_FLAG_CNRDY) || \
- ((FLAG) == SAI_FLAG_AFSDET) || \
- ((FLAG) == SAI_FLAG_LFSDET))
/**
* @}
*/
-/** @defgroup SAI_Block_Fifo_Status_Level
+/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
* @{
*/
-#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000)
-#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000)
-#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000)
-#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000)
-#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000)
-#define SAI_FIFOStatus_Full ((uint32_t)0x00050000)
+#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000)
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000)
+#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000)
+#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000)
+#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000)
+#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000)
-#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
- ((STATUS) == SAI_FIFOStatus_HalfFull) || \
- ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
- ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
- ((STATUS) == SAI_FIFOStatus_Full) || \
- ((STATUS) == SAI_FIFOStatus_Empty))
/**
* @}
*/
-
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Macros SAI Exported Macros
+ * @brief macros to handle interrupts and specific configurations
+ * @{
+ */
+
/** @brief Reset SAI handle state
* @param __HANDLE__: specifies the SAI Handle.
* @retval None
@@ -712,31 +652,62 @@
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
-
+
+ /**
+ * @}
+ */
+
+/* Include RCC SAI Extension module */
+#include "stm32f4xx_hal_sai_ex.h"
+
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAI_Exported_Functions
+ * @{
+ */
+
/* Initialization/de-initialization functions **********************************/
+/** @addtogroup SAI_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
/* I/O operation functions *****************************************************/
+/** @addtogroup SAI_Exported_Functions_Group2
+ * @{
+ */
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
@@ -744,12 +715,182 @@
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+/** @addtogroup SAI_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SAI_Private_Types SAI Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Variables SAI Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Constants SAI Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SAI_Private_Macros
+ * @{
+ */
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
+ ((STATE) == SAI_SYNCEXT_IN_ENABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
+ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_PCM_LONG) ||\
+ ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == SAI_CLKSOURCE_EXT))
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
+
+#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
+ ((MODE) == SAI_MODEMASTER_RX) || \
+ ((MODE) == SAI_MODESLAVE_TX) || \
+ ((MODE) == SAI_MODESLAVE_RX))
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
+ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \
+ ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
+ ((DATASIZE) == SAI_DATASIZE_10) || \
+ ((DATASIZE) == SAI_DATASIZE_16) || \
+ ((DATASIZE) == SAI_DATASIZE_20) || \
+ ((DATASIZE) == SAI_DATASIZE_24) || \
+ ((DATASIZE) == SAI_DATASIZE_32))
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+ ((BIT) == SAI_FIRSTBIT_LSB))
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT))
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
+ ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
+ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
+
+#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOSTATUS_LESS1QUARTERFULL ) || \
+ ((STATUS) == SAI_FIFOSTATUS_HALFFULL) || \
+ ((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL) || \
+ ((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL) || \
+ ((STATUS) == SAI_FIFOSTATUS_FULL) || \
+ ((STATUS) == SAI_FIFOSTATUS_EMPTY))
+
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
+ ((VALUE) == SAI_LAST_SENT_VALUE))
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
+ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+ ((STATE) == SAI_OUTPUT_RELEASED))
+
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+ ((MODE) == SAI_STEREOMODE))
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((((ACTIVE) >> 16 ) > 0) && (((ACTIVE) >> 16 ) <= (SAI_SLOTACTIVE_ALL >> 16)))
+
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+ ((SIZE) == SAI_SLOTSIZE_16B) || \
+ ((SIZE) == SAI_SLOTSIZE_32B))
+
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+ ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai_ex.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief SAI Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SAI extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SAI peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SAI interface for STM32F446xx
+ devices contains the following additional features :
+
+ (+) Possibility to be clocked from PLLR
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to manage several sources to clock SAI
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SAIEx SAIEx
+ * @brief SAI Extension HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SAI registers Masks */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+ /**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
+ * @brief Extension features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension features Functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the possible
+ SAI clock sources.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure SAI Block synchronization mode
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval SAI Clock Input
+ */
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
+{
+ uint32_t tmpregisterGCR = 0;
+
+#if defined(STM32F446xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(hsai->Init.SynchroExt)
+ {
+ case SAI_SYNCEXT_DISABLE :
+ tmpregisterGCR = 0;
+ break;
+ case SAI_SYNCEXT_IN_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCIN_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ }
+
+ if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ SAI1->GCR = tmpregisterGCR;
+ }
+ else
+ {
+ SAI2->GCR = tmpregisterGCR;
+ }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(hsai->Init.SynchroExt)
+ {
+ case SAI_SYNCEXT_DISABLE :
+ tmpregisterGCR = 0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ }
+ SAI1->GCR = tmpregisterGCR;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+}
+ /**
+ * @brief Get SAI Input Clock based on SAI source clock selection
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval SAI Clock Input
+ */
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
+{
+ /* This variable used to store the SAI_CK_x (value in Hz) */
+ uint32_t saiclocksource = 0;
+
+#if defined(STM32F446xx)
+ if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+ }
+ else /* SAI2_Block_A || SAI2_Block_B*/
+ {
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
+ }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ uint32_t vcoinput = 0, tmpreg = 0;
+
+ /* Check the SAI Block parameters */
+ assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
+
+ /* SAI Block clock source selection */
+ if(hsai->Instance == SAI1_Block_A)
+ {
+ __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
+ }
+ else
+ {
+ __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2));
+ }
+
+ /* VCO Input Clock value calculation */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+
+ /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
+ if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+ saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
+ saiclocksource = saiclocksource/(tmpreg);
+
+ }
+ else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+ saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
+ saiclocksource = saiclocksource/(tmpreg);
+ }
+ else /* sConfig->ClockSource == SAI_CLKSource_Ext */
+ {
+ /* Enable the External Clock selection */
+ __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
+
+ saiclocksource = EXTERNAL_CLOCK_VALUE;
+ }
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ /* the return result is the value of SAI clock */
+ return saiclocksource;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai_ex.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Header file of SAI Extension HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_EX_H
+#define __STM32F4xx_HAL_SAI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SAIEx
+ * @{
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAIEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SAIEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Extended features functions ************************************************/
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sd.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@@ -30,14 +30,14 @@
It is used as follows:
(#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
- (##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE();
+ (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
(##) SDIO pins configuration for SD card
- (+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE();
+ (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
and HAL_SD_WriteBlocks_DMA() APIs).
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE();
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
(+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDIO and DMA interrupt priorities using functions
@@ -54,7 +54,7 @@
================================================
[..]
To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- the SD Card and put it into StandBy State (Ready for data transfer).
+ the SD Card and put it into Standby State (Ready for data transfer).
This function provide the following operations:
(#) Apply the SD Card initialization process at 400KHz and check the SD Card
@@ -90,14 +90,14 @@
==============================
[..]
(+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function support only 512-byte block length (the block size should be
- chosen as 512 byte).
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function support only 512-byte block length (the block size should be
- chosen as 512 byte).
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
@@ -107,13 +107,13 @@
===============================
[..]
(+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function support only 512-byte block length (the block size should be
- chosen as 512 byte).
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function support only 512-byte block length (the block size should be
+ This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
@@ -133,7 +133,7 @@
==================================
[..]
Below the list of most used macros in SD HAL driver.
-
+
(+) __HAL_SD_SDIO_ENABLE : Enable the SD device
(+) __HAL_SD_SDIO_DISABLE : Disable the SD device
(+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
@@ -149,7 +149,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -179,25 +179,27 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+#ifdef HAL_SD_MODULE_ENABLED
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @defgroup SD
- * @brief SD HAL module driver
+/** @addtogroup SD
* @{
*/
-#ifdef HAL_SD_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup SD_Private_Define
+/** @addtogroup SD_Private_Defines
* @{
*/
-
/**
- * @brief SDIO Static flags, TimeOut, FIFO Address
+ * @brief SDIO Data block size
+ */
+#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
+/**
+ * @brief SDIO Static flags, Timeout, FIFO Address
*/
#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
@@ -223,7 +225,7 @@
#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000)
+#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
@@ -271,6 +273,7 @@
* SDIO_APP_CMD should be sent before sending these commands.
*/
#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
+
/**
* @}
*/
@@ -278,8 +281,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
+/** @addtogroup SD_Private_Functions_Prototypes
* @{
*/
static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
@@ -305,15 +307,15 @@
/**
* @}
*/
-
-/** @defgroup SD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
* @{
*/
-/** @defgroup SD_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @addtogroup SD_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@@ -338,6 +340,8 @@
__IO HAL_SD_ErrorTypedef errorstate = SD_OK;
SD_InitTypeDef tmpinit;
+ /* Allocate lock resource and initialize it */
+ hsd->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SD_MspInit(hsd);
@@ -429,7 +433,7 @@
* @}
*/
-/** @defgroup SD_Group2 IO operation functions
+/** @addtogroup SD_Exported_Functions_Group2
* @brief Data transfer functions
*
@verbatim
@@ -451,7 +455,7 @@
* @param pReadBuffer: pointer to the buffer that will contain the received data
* @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
- * This parameter should be 512
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to read
* @retval SD Card error state
*/
@@ -490,7 +494,7 @@
/* Configure the SD DPSM (Data Path State Machine) */
sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
- sdio_datainitstructure.DataBlockSize = (uint32_t)(9 << 4);
+ sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
@@ -522,7 +526,11 @@
}
/* Poll on SDIO flags */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -547,7 +555,11 @@
}
/* In case of single block transfer, no need of stop transfer at all */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -559,7 +571,7 @@
tempbuff += 8;
}
- }
+ }
}
/* Send stop transmission command in case of multiblock read */
@@ -599,6 +611,7 @@
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -607,6 +620,7 @@
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -635,7 +649,7 @@
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
* @param WriteAddr: Address from where data is to be written
* @param BlockSize: SD card Data block size
- * This parameter should be 512.
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to write
* @retval SD Card error state
*/
@@ -717,7 +731,11 @@
/* Write block(s) in polling mode */
if(NumberOfBlocks > 1)
{
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
@@ -749,8 +767,12 @@
}
else
{
- /* In case of single data block transfer no need of stop command at all */
+ /* In case of single data block transfer no need of stop command at all */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
@@ -817,6 +839,7 @@
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -825,6 +848,7 @@
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -853,7 +877,7 @@
* @param pReadBuffer: Pointer to the buffer that will contain the received data
* @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
- * This paramater should be 512.
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to read.
* @retval SD Card error state
*/
@@ -882,11 +906,18 @@
}
/* Enable transfer interrupts */
+#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_RXOVERR |\
SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+ SDIO_IT_DTIMEOUT |\
+ SDIO_IT_DATAEND |\
+ SDIO_IT_RXOVERR));
+#endif /* SDIO_STA_STBITERR */
/* Enable SDIO DMA transfer */
__HAL_SD_SDIO_DMA_ENABLE();
@@ -896,7 +927,7 @@
hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks));
+ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
@@ -941,7 +972,7 @@
sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
}
- sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
+ sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
@@ -970,7 +1001,7 @@
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
* @param WriteAddr: Address from where data is to be read
* @param BlockSize: the SD card Data block size
- * This parameter should be 512.
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to write
* @retval SD Card error state
*/
@@ -999,18 +1030,25 @@
}
/* Enable transfer interrupts */
+#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_TXUNDERR |\
- SDIO_IT_STBITERR));
+ SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+ SDIO_IT_DTIMEOUT |\
+ SDIO_IT_DATAEND |\
+ SDIO_IT_TXUNDERR));
+#endif /* SDIO_STA_STBITERR */
/* Configure DMA user callbacks */
hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;
hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks));
+ HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
/* Enable SDIO DMA transfer */
__HAL_SD_SDIO_DMA_ENABLE();
@@ -1298,7 +1336,7 @@
{
}
- /* Wait untill the card is in programming state */
+ /* Wait until the card is in programming state */
errorstate = SD_IsCardProgramming(hsd, &cardstate);
delay = SD_DATATIMEOUT;
@@ -1365,6 +1403,7 @@
HAL_SD_XferErrorCallback(hsd);
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -1373,15 +1412,22 @@
HAL_SD_XferErrorCallback(hsd);
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
- }
+ }
/* Disable all SDIO peripheral interrupt sources */
+#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
- SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+ SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
+ SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
+ SDIO_IT_RXOVERR);
+#endif /* SDIO_STA_STBITERR */
}
@@ -1465,7 +1511,7 @@
* @}
*/
-/** @defgroup SD_Group3 Peripheral Control functions
+/** @addtogroup SD_Exported_Functions_Group3
* @brief management functions
*
@verbatim
@@ -1578,7 +1624,7 @@
/* Byte 10 */
tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
- pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
+ pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024);
pCardInfo->CardBlockSize = 512;
}
else
@@ -1586,7 +1632,7 @@
/* Not supported card type */
errorstate = SD_ERROR;
}
-
+
pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
@@ -1848,8 +1894,11 @@
{
return errorstate;
}
-
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -1886,6 +1935,7 @@
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -1894,11 +1944,12 @@
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
}
-
+
count = SD_DATATIMEOUT;
while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
@@ -1925,7 +1976,7 @@
* @}
*/
-/** @defgroup SD_Group4 Peripheral State functions
+/** @addtogroup SD_Exported_Functions_Group4
* @brief Peripheral State functions
*
@verbatim
@@ -2000,13 +2051,13 @@
sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
- /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
+ /* Send ACMD13 (SD_APP_STATUS) with argument as card's RCA */
sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STAUS;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS;
SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
if (errorstate != SD_OK)
{
@@ -2014,7 +2065,11 @@
}
/* Get status data */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -2051,6 +2106,7 @@
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -2059,6 +2115,7 @@
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -2195,7 +2252,8 @@
/**
* @}
*/
-
+
+/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
*/
@@ -2218,6 +2276,9 @@
{
}
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
/* Transfer complete user callback */
HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
}
@@ -2253,7 +2314,10 @@
while(hsd->SdTransferCplt == 0)
{
}
-
+
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
/* Transfer complete user callback */
HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
}
@@ -2384,7 +2448,7 @@
}
/**
- * @brief Selects od Deselects the corresponding card.
+ * @brief Selects of Deselects the corresponding card.
* @param hsd: SD handle
* @param addr: Address of the card to be selected
* @retval SD Card error state
@@ -2429,6 +2493,10 @@
/* Set Power State to ON */
SDIO_PowerState_ON(hsd->Instance);
+ /* 1ms: required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(1);
+
/* Enable SDIO Clock */
__HAL_SD_SDIO_ENABLE();
@@ -2446,7 +2514,7 @@
if(errorstate != SD_OK)
{
- /* CMD Response TimeOut (wait for CMDSENT flag) */
+ /* CMD Response Timeout (wait for CMDSENT flag) */
return errorstate;
}
@@ -2479,7 +2547,7 @@
/* Check for error conditions */
errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
- /* If errorstate is Command TimeOut, it is a MMC card */
+ /* If errorstate is Command Timeout, it is a MMC card */
/* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
or SD card 1.x */
if(errorstate == SD_OK)
@@ -2799,7 +2867,7 @@
return(SD_STREAM_WRITE_OVERRUN);
}
- if((response_r1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
+ if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
{
return(SD_CID_CSD_OVERWRITE);
}
@@ -2887,7 +2955,7 @@
else
{
/* No error flag set */
- }
+ }
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@@ -2931,7 +2999,7 @@
else
{
/* No error flag set */
- }
+ }
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
@@ -3174,8 +3242,11 @@
{
return errorstate;
}
-
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
{
@@ -3208,6 +3279,7 @@
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -3216,6 +3288,7 @@
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -3370,7 +3443,7 @@
return(SD_STREAM_WRITE_OVERRUN);
}
- if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
+ if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
{
return(SD_CID_CSD_OVERWRITE);
}
@@ -3403,6 +3476,7 @@
*/
#endif /* HAL_SD_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sd.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,20 +50,22 @@
* @{
*/
-/** @addtogroup SD
+/** @defgroup SD SD
+ * @brief SD HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
-/** @defgroup SD_Exported_Types
+/** @defgroup SD_Exported_Types SD Exported Types
+ * @{
+ */
+
+/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
* @{
*/
#define SD_InitTypeDef SDIO_InitTypeDef
#define SD_TypeDef SDIO_TypeDef
-/**
- * @brief SDIO Handle Structure definition
- */
typedef struct
{
SD_TypeDef *Instance; /*!< SDIO register base address */
@@ -93,9 +95,12 @@
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
}SD_HandleTypeDef;
+/**
+ * @}
+ */
-/**
- * @brief Card Specific Data: CSD Register
+/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
+ * @{
*/
typedef struct
{
@@ -138,10 +143,13 @@
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CSDTypedef;
+/**
+ * @}
+ */
-/**
- * @brief Card Identification Data: CID Register
- */
+/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
+ * @{
+ */
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
@@ -156,10 +164,13 @@
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CIDTypedef;
+/**
+ * @}
+ */
-/**
- * @brief SD Card Status returned by ACMD13
- */
+/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
+ * @{
+ */
typedef struct
{
__IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
@@ -174,10 +185,13 @@
__IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
}HAL_SD_CardStatusTypedef;
+/**
+ * @}
+ */
-/**
- * @brief SD Card information structure
- */
+/** @defgroup SD_Exported_Types_Group5 SD Card information structure
+ * @{
+ */
typedef struct
{
HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
@@ -188,10 +202,13 @@
uint8_t CardType; /*!< SD card type */
}HAL_SD_CardInfoTypedef;
+/**
+ * @}
+ */
-/**
- * @brief SD Error status enumeration Structure definition
- */
+/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
+ * @{
+ */
typedef enum
{
/**
@@ -245,10 +262,13 @@
SD_OK = (0)
}HAL_SD_ErrorTypedef;
+/**
+ * @}
+ */
-/**
- * @brief SD Transfer state enumeration structure
- */
+/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
+ * @{
+ */
typedef enum
{
SD_TRANSFER_OK = 0, /*!< Transfer success */
@@ -256,10 +276,13 @@
SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
}HAL_SD_TransferStateTypedef;
+/**
+ * @}
+ */
-/**
- * @brief SD Card State enumeration structure
- */
+/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
+ * @{
+ */
typedef enum
{
SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
@@ -273,10 +296,13 @@
SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
}HAL_SD_CardStateTypedef;
+/**
+ * @}
+ */
-/**
- * @brief SD Operation enumeration structure
- */
+/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
+ * @{
+ */
typedef enum
{
SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
@@ -285,10 +311,16 @@
SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
}HAL_SD_OperationTypedef;
+/**
+ * @}
+ */
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants
+/** @defgroup SD_Exported_Constants SD Exported Constants
* @{
*/
@@ -354,7 +386,7 @@
*/
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
-#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
+#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
@@ -396,11 +428,10 @@
*/
/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SD_Exported_macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+/** @defgroup SD_Exported_macros SD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/**
* @brief Enable the SD device.
@@ -609,12 +640,11 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
+/** @defgroup SD_Exported_Functions SD Exported Functions
* @{
*/
-
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup SD_Group1
+
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
@@ -624,9 +654,8 @@
/**
* @}
*/
-
-/* I/O operation functions ***************************************************/
-/** @addtogroup SD_Group2
+
+/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
* @{
*/
/* Blocking mode: Polling */
@@ -653,9 +682,8 @@
/**
* @}
*/
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup SD_Group3
+
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
@@ -667,7 +695,7 @@
*/
/* Peripheral State functions ************************************************/
-/** @addtogroup SD_Group4
+/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
@@ -681,19 +709,81 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
/**
* @}
- */
+ */
#ifdef __cplusplus
}
#endif
-
-#endif /* __STM32F4xx_HAL_SD_H */
+#endif /* __STM32F4xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -97,26 +97,24 @@
* @{
*/
-/** @defgroup SDRAM
+/** @defgroup SDRAM SDRAM
* @brief SDRAM driver modules
* @{
*/
#ifdef HAL_SDRAM_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SDRAM_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
* @{
*/
-
-/** @defgroup SDRAM_Group1 Initialization and de-initialization functions
+
+/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -148,6 +146,8 @@
if(hsdram->State == HAL_SDRAM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsdram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
}
@@ -272,12 +272,11 @@
the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
*/
}
-
/**
* @}
*/
-/** @defgroup SDRAM_Group2 Input and Output functions
+/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -330,8 +329,7 @@
return HAL_OK;
}
-
-
+
/**
* @brief Writes 8-bit data buffer to SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
@@ -375,7 +373,6 @@
return HAL_OK;
}
-
/**
* @brief Reads 16-bit data buffer from the SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
@@ -623,12 +620,11 @@
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup SDRAM_Group3 Control functions
+/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
@@ -717,7 +713,7 @@
/* Send SDRAM command */
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
- /* Update the SDRAM controller state state */
+ /* Update the SDRAM controller state */
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
{
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
@@ -800,7 +796,7 @@
* @}
*/
-/** @defgroup SDRAM_Group4 State functions
+/** @defgroup SDRAM_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
@@ -833,7 +829,7 @@
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_SDRAM_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_fmc.h"
@@ -57,6 +57,9 @@
*/
/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
+ * @{
+ */
/**
* @brief HAL SDRAM State structure definition
@@ -88,19 +91,35 @@
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
}SDRAM_HandleTypeDef;
-
-/* Exported types ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
+ * @{
+ */
/** @brief Reset SDRAM handle state
* @param __HANDLE__: specifies the SDRAM handle.
* @retval None
*/
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
+ * @{
+ */
-/* Initialization/de-initialization functions **********************************/
+/** @addtogroup SDRAM_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization/de-initialization functions *********************************/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
@@ -110,8 +129,14 @@
void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
-/* I/O operation functions *****************************************************/
+/** @addtogroup SDRAM_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
@@ -121,7 +146,13 @@
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
+/**
+ * @}
+ */
+
+/** @addtogroup SDRAM_Exported_Functions_Group3
+ * @{
+ */
/* SDRAM Control functions *****************************************************/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
@@ -129,14 +160,28 @@
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
+/**
+ * @}
+ */
+/** @addtogroup SDRAM_Exported_Functions_Group4
+ * @{
+ */
/* SDRAM State functions ********************************************************/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
+/**
+ * @}
+ */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -34,7 +34,7 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
@@ -42,11 +42,11 @@
(#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
(++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SMARTCARD_MspInit() API.
+ by calling the customized HAL_SMARTCARD_MspInit() API.
[..]
(@) The specific SMARTCARD interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
- __SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
[..]
Three operation modes are available within this driver :
@@ -100,7 +100,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -134,63 +134,77 @@
* @{
*/
-/** @defgroup SMARTCARD
+/** @defgroup SMARTCARD SMARTCARD
* @brief HAL USART SMARTCARD module driver
* @{
*/
#ifdef HAL_SMARTCARD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Constants
+ * @{
+ */
#define SMARTCARD_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SMARTCARD_Private_Functions
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
-/** @defgroup SMARTCARD_Group1 SmartCard Initialization and de-initialization functions
+/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in Smartcard mode.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- please refer to Reference manual for possible SMARTDARD frame formats.
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
- (++) Receiver/transmitter modes
- (++) Prescaler
- (++) GuardTime
- (++) NACKState: The Smartcard NACK state
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in Smartcard mode.
+ [..]
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ [..]
+ The USART can provide a clock to the smartcard through the SCLK output.
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
+ from the internal peripheral input clock through a 5-bit prescaler.
+ [..]
+ (+) For the Smartcard mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length => Should be 9 bits (8 bits + parity)
+ (++) Stop Bit
+ (++) Parity: => Should be enabled
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | SMARTCARD frame |
+ |---------------------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+ (++) Prescaler
+ (++) GuardTime
+ (++) NACKState: The Smartcard NACK state
(+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
(++) Word Length = 9 Bits
@@ -198,13 +212,13 @@
(++) Even parity
(++) BaudRate = 12096 baud
(++) Tx and Rx enabled
- [..]
- Please refer to the ISO 7816-3 specification for more details.
+ [..]
+ Please refer to the ISO 7816-3 specification for more details.
- -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
- [..]
+ -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
+ to use 1.5 stop bits for both transmitting and receiving to avoid switching
+ between the two configurations.
+ [..]
The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
procedure (details for the procedure are available in reference manual (RM0329)).
@@ -233,6 +247,8 @@
if(hsc->State == HAL_SMARTCARD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsc->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SMARTCARD_MspInit(hsc);
}
@@ -255,13 +271,13 @@
hsc->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_HDSEL);
/* Enable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Framing Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
- /* Enable the Peripharal */
- __SMARTCARD_ENABLE(hsc);
+ /* Enable the Peripheral */
+ __HAL_SMARTCARD_ENABLE(hsc);
/* Configure the Smartcard NACK state */
MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
@@ -295,6 +311,9 @@
hsc->State = HAL_SMARTCARD_STATE_BUSY;
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsc);
+
/* DeInit the low level hardware */
HAL_SMARTCARD_MspDeInit(hsc);
@@ -316,7 +335,7 @@
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit could be implenetd in the user file
+ the HAL_SMARTCARD_MspInit could be implemented in the user file
*/
}
@@ -329,7 +348,7 @@
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit could be implenetd in the user file
+ the HAL_SMARTCARD_MspDeInit could be implemented in the user file
*/
}
@@ -337,7 +356,7 @@
* @}
*/
-/** @defgroup SMARTCARD_Group2 IO operation functions
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
@@ -346,11 +365,11 @@
===============================================================================
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
(#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
@@ -362,7 +381,7 @@
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the Transmit or Receive process
+ will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
@@ -427,34 +446,16 @@
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0)
{
- hsc->TxXferCount--;
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+ hsc->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- pData +=2;
- }
- else
- {
- pData +=1;
- }
+ return HAL_TIMEOUT;
}
- else
- {
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hsc->Instance->DR = (*pData++ & (uint8_t)0xFF);
- }
+ tmp = (uint16_t*) pData;
+ hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ pData +=1;
}
-
+
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -519,43 +520,18 @@
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
+
/* Check the remain data to be received */
while(hsc->RxXferCount > 0)
{
hsc->RxXferCount--;
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
- pData +=2;
- }
- else
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
- pData +=1;
- }
+ return HAL_TIMEOUT;
}
- else
- {
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
- }
- }
+ tmp = (uint16_t*) pData;
+ *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+ pData +=1;
}
/* Check if a non-blocking transmit process is ongoing or not */
@@ -617,17 +593,17 @@
hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
- /* Enable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
-
/* Process Unlocked */
__HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Enable the SMARTCARD Transmit data register empty Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
return HAL_OK;
}
@@ -674,18 +650,17 @@
{
hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
-
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
/* Enable the SMARTCARD Data Register not empty Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
/* Enable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
return HAL_OK;
}
@@ -734,7 +709,7 @@
hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
- /* Set the SMARTCARD DMA transfert complete callback */
+ /* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
/* Set the DMA error callback */
@@ -744,6 +719,9 @@
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the SMARTCARD CR3 register */
hsc->Instance->CR3 |= USART_CR3_DMAT;
@@ -798,7 +776,7 @@
hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
- /* Set the SMARTCARD DMA transfert complete callback */
+ /* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
/* Set the DMA error callback */
@@ -836,7 +814,7 @@
tmp1 = hsc->Instance->SR;
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
- /* SMARTCARD parity error interrupt occured --------------------------------*/
+ /* SMARTCARD parity error interrupt occurred --------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
@@ -844,7 +822,7 @@
}
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
- /* SMARTCARD frame error interrupt occured ---------------------------------*/
+ /* SMARTCARD frame error interrupt occurred ---------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
@@ -852,7 +830,7 @@
}
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
- /* SMARTCARD noise error interrupt occured ---------------------------------*/
+ /* SMARTCARD noise error interrupt occurred ---------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
@@ -860,7 +838,7 @@
}
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
- /* SMARTCARD Over-Run interrupt occured ------------------------------------*/
+ /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/
if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
@@ -880,6 +858,13 @@
{
SMARTCARD_Transmit_IT(hsc);
}
+
+ tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsc);
+ }
/* Call the Error call Back in case of Errors */
if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
@@ -933,7 +918,7 @@
* @}
*/
-/** @defgroup SMARTCARD_Group3 Peripheral State and Errors functions
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SMARTCARD State and Errors functions
*
@verbatim
@@ -943,7 +928,7 @@
[..]
This subsection provides a set of functions allowing to control the SmartCard.
(+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
- (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occured durung communication.
+ (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
*/
@@ -990,27 +975,8 @@
in the USART CR3 register */
hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
- /* Wait for SMARTCARD TC Flag */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;
- HAL_SMARTCARD_ErrorCallback(hsc);
- }
- else
- {
- /* No Timeout */
- /* Check if a non-blocking receive process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_READY;
- }
- HAL_SMARTCARD_TxCpltCallback(hsc);
- }
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
}
/**
@@ -1086,8 +1052,8 @@
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
hsc->State= HAL_SMARTCARD_STATE_READY;
@@ -1109,8 +1075,8 @@
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
hsc->State= HAL_SMARTCARD_STATE_READY;
@@ -1139,64 +1105,57 @@
tmp1 = hsc->State;
if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hsc->pTxBuffPtr;
- hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- hsc->pTxBuffPtr += 2;
- }
- else
- {
- hsc->pTxBuffPtr += 1;
- }
- }
- else
- {
- hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF);
- }
+ tmp = (uint16_t*) hsc->pTxBuffPtr;
+ hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ hsc->pTxBuffPtr += 1;
if(--hsc->TxXferCount == 0)
{
/* Disable the SMARTCARD Transmit data register empty Interrupt */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-
- /* Disable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
-
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Check if a non-blocking receive process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_READY;
- }
-
- HAL_SMARTCARD_TxCpltCallback(hsc);
-
- return HAL_OK;
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
}
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
* @brief Receive an amount of data in non blocking mode
* @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
@@ -1210,41 +1169,19 @@
tmp1 = hsc->State;
if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hsc->pRxBuffPtr;
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
- hsc->pRxBuffPtr += 2;
- }
- else
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
- hsc->pRxBuffPtr += 1;
- }
- }
- else
- {
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
- }
- }
+ tmp = (uint16_t*) hsc->pRxBuffPtr;
+ *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+ hsc->pRxBuffPtr += 1;
if(--hsc->RxXferCount == 0)
{
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
/* Disable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Check if a non-blocking transmit process is ongoing or not */
if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
@@ -1342,11 +1279,11 @@
/*-------------------------- USART BRR Configuration -----------------------*/
if((hsc->Instance == USART1) || (hsc->Instance == USART6))
{
- hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
}
else
{
- hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
}
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
/**
* @brief SMARTCARD Init Structure definition
*/
@@ -78,7 +82,7 @@
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref SMARTCARD_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
@@ -91,11 +95,13 @@
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
- uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler.
- This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time.
- This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
+ to provide the smartcard clock
+ This parameter can be a value of @ref SMARTCARD_Prescaler */
+
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks
+ The value given in the register (5 significant bits) is multiplied by 2
+ to give the division factor of the source clock frequency */
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
This parameter can be a value of @ref SmartCard_NACK_State */
@@ -117,26 +123,13 @@
}HAL_SMARTCARD_StateTypeDef;
/**
- * @brief HAL SMARTCARD Error Code structure definition
- */
-typedef enum
-{
- HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
- HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
- HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
- HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
- HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_SMARTCARD_ErrorTypeDef;
-
-/**
* @brief SMARTCARD handle Structure definition
*/
typedef struct
{
USART_TypeDef *Instance; /* USART registers base address */
- SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+ SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
@@ -154,127 +147,160 @@
DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /* Locking object */
- __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
+ __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
- __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SMARTCARD Error code */
+ __IO uint32_t ErrorCode; /* SmartCard Error code */
+
}SMARTCARD_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants
- * @{
- */
-
-/** @defgroup SMARTCARD_Word_Length
- * @{
- */
-#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) (((LENGTH) == SMARTCARD_WORDLENGTH_8B) || \
- ((LENGTH) == SMARTCARD_WORDLENGTH_9B))
/**
* @}
*/
-/** @defgroup SMARTCARD_Stop_Bits
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
* @{
*/
-#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
-#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_1) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_1_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_2))
+/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
+ * @brief SMARTCARD Error Code
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
/**
* @}
*/
-/** @defgroup SMARTCARD_Parity
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_NONE) || \
- ((PARITY) == SMARTCARD_PARITY_EVEN) || \
- ((PARITY) == SMARTCARD_PARITY_ODD))
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
-/** @defgroup SMARTCARD_Mode
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Mode
* @{
*/
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
-/** @defgroup SMARTCARD_Clock_Polarity
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup SMARTCARD_Clock_Phase
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
/**
* @}
*/
-/** @defgroup SMARTCARD_Last_Bit
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
- ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
/**
* @}
*/
-/** @defgroup SmartCard_NACK_State
+/** @defgroup SmartCard_NACK_State SMARTCARD NACK State
* @{
*/
-#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000)
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
- ((NACK) == SMARTCARD_NACK_DISABLED))
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_DMA_Requests SMARTCARD DMA requests
+ * @{
+ */
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
/**
* @}
*/
-/** @defgroup SmartCard_DMA_Requests
+/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
* @{
*/
-
-#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
-
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001) /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002) /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003) /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004) /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005) /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006) /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007) /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008) /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009) /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000A) /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000B) /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000C) /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000D) /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000E) /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000F) /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010) /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011) /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012) /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013) /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014) /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015) /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016) /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017) /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018) /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019) /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001A) /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001B) /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001C) /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001D) /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001E) /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001F) /*!< SYSCLK divided by 62 */
/**
* @}
*/
-/** @defgroup SmartCard_Flags
+/** @defgroup SmartCard_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
@@ -287,23 +313,20 @@
* @}
*/
-/** @defgroup SmartCard_Interrupt_definition
+/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR3 register
-
- *
* @{
*/
-#define SMARTCARD_IT_PE ((uint32_t)0x10000100)
-#define SMARTCARD_IT_TXE ((uint32_t)0x10000080)
-#define SMARTCARD_IT_TC ((uint32_t)0x10000040)
-#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020)
-#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010)
-#define SMARTCARD_IT_ERR ((uint32_t)0x20000001)
-
+#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@@ -313,6 +336,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
/** @brief Reset SMARTCARD handle state
* @param __HANDLE__: specifies the SMARTCARD Handle.
@@ -333,7 +359,7 @@
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
- * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
+ * @arg SMARTCARD_FLAG_ORE: Overrun Error flag
* @arg SMARTCARD_FLAG_NE: Noise Error flag
* @arg SMARTCARD_FLAG_FE: Framing Error flag
* @arg SMARTCARD_FLAG_PE: Parity Error flag
@@ -348,7 +374,7 @@
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
*
- * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
+ * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
* error) flags are cleared by software sequence: a read operation to
* USART_SR register followed by a read operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
@@ -364,8 +390,14 @@
* UART peripheral.
* @retval None
*/
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
- (__HANDLE__)->Instance->DR;}while(0)
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
@@ -410,11 +442,10 @@
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
*/
-#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF)
-#define __SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-#define __SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__: specifies the SmartCard Handle.
@@ -430,11 +461,31 @@
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
-/** @brief Macros to enable or disable the SmartCard interface.
- * @param __HANDLE__: specifies the SmartCard Handle.
+/** @brief Macro to enable the SMARTCARD's one bit sample method
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Macro to disable the SMARTCARD's one bit sample method
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
*/
-#define __SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define __SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Macros to enable or disable the SmartCard DMA request.
* @param __HANDLE__: specifies the SmartCard Handle.
@@ -443,23 +494,34 @@
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
*/
-#define __SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
-#define __SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
+#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
+#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
-#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __SMARTCARD_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -471,10 +533,16 @@
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+/**
+ * @}
+ */
+/** @addtogroup SMARTCARD_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
@@ -483,7 +551,66 @@
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+/** @brief SMARTCARD interruptions flag mask
+ *
+ */
+#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR3_EIE )
+#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100)
+#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define SMARTCARD_BRR(_PCLK_, _BAUD_) ((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define SMARTCARD_CR1_REG_INDEX 1
+#define SMARTCARD_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
+ ((NACK) == SMARTCARD_NACK_DISABLE))
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,1210 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spdifrx.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the SPDIFRX audio interface:
+ * + Initialization and Configuration
+ * + Data transfers functions
+ * + DMA transfers management
+ * + Interrupts and flags management
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The SPDIFRX HAL driver can be used as follow:
+
+ (#) Declare SPDIFRX_HandleTypeDef handle structure.
+ (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
+ (##) Enable the SPDIFRX interface clock.
+ (##) SPDIFRX pins configuration:
+ (+++) Enable the clock for the SPDIFRX GPIOs.
+ (+++) Configure these SPDIFRX pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
+ (+++) Configure the SPDIFRX interrupt priority.
+ (+++) Enable the NVIC SPDIFRX IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
+ (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
+ (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
+ (+++) Configure the DMA Channel.
+ (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA CtrlRx/DataRx channel.
+
+ (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
+ using HAL_SPDIFRX_Init() function.
+
+ -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
+ __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
+ -@- Make sure that ck_spdif clock is configured.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode for reception operation (for debug purpose) ***
+ ================================================================
+ [..]
+ (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
+ (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
+
+ *** Interrupt mode for reception operation ***
+ =========================================
+ [..]
+ (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
+ (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+
+ *** DMA mode for reception operation ***
+ ========================================
+ [..]
+ (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
+ (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+ (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
+
+ *** SPDIFRX HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+ (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
+ (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
+ (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
+ (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
+ (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
+ (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
+
+ [..]
+ (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup SPDIFRX SPDIFRX
+ * @brief SPDIFRX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SPDIFRX_TIMEOUT_VALUE 0xFFFF
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SPDIFRX_Private_Functions
+ * @{
+ */
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
+ * @{
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPDIFRX peripheral:
+
+ (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
+ the selected configuration:
+ (++) Input Selection (IN0, IN1,...)
+ (++) Maximum allowed re-tries during synchronization phase
+ (++) Wait for activity on SPDIF selected input
+ (++) Channel status selection (from channel A or B)
+ (++) Data format (LSB, MSB, ...)
+ (++) Stereo mode
+ (++) User bits masking (PT,C,U,V,...)
+
+ (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
+ of the selected SPDIFRXx peripheral.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SPDIFRX according to the specified parameters
+ * in the SPDIFRX_InitTypeDef and create the associated handle.
+ * @param hspdif: SPDIFRX handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the SPDIFRX parameters */
+ assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
+ assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
+ assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
+ assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
+ assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
+ assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
+ assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
+ assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
+ assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
+ assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspdif->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_SPDIFRX_MspInit(hspdif);
+ }
+
+ /* SPDIFRX peripheral state is BUSY*/
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Disable SPDIFRX interface (IDLE State) */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ /* Reset the old SPDIFRX CR configuration */
+ tmpreg = hspdif->Instance->CR;
+
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
+ SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
+ SPDIFRX_CR_INSEL);
+
+ /* Sets the new configuration of the SPDIFRX peripheral */
+ tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
+ hspdif->Init.InputSelection |
+ hspdif->Init.Retries |
+ hspdif->Init.WaitForActivity |
+ hspdif->Init.ChannelSelection |
+ hspdif->Init.DataFormat |
+ hspdif->Init.PreambleTypeMask |
+ hspdif->Init.ChannelStatusMask |
+ hspdif->Init.ValidityBitMask |
+ hspdif->Init.ParityErrorMask);
+
+ hspdif->Instance->CR = tmpreg;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* SPDIFRX peripheral state is READY*/
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SPDIFRX peripheral
+ * @param hspdif: SPDIFRX handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Disable SPDIFRX interface (IDLE state) */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPDIFRX_MspDeInit(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* SPDIFRX peripheral state is RESET*/
+ hspdif->State = HAL_SPDIFRX_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SPDIFRX MSP Init
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPDIFRX MSP DeInit
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Sets the SPDIFRX dtat format according to the specified parameters
+ * in the SPDIFRX_InitTypeDef.
+ * @param hspdif: SPDIFRX handle
+ * @param sDataFormat: SPDIFRX data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the SPDIFRX parameters */
+ assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
+ assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
+ assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
+ assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
+ assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
+ assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
+
+ /* Reset the old SPDIFRX CR configuration */
+ tmpreg = hspdif->Instance->CR;
+
+ if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
+ (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
+ ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
+ {
+ return HAL_ERROR;
+ }
+
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
+
+ /* Sets the new configuration of the SPDIFRX peripheral */
+ tmpreg |= ((uint16_t) sDataFormat.StereoMode |
+ sDataFormat.DataFormat |
+ sDataFormat.PreambleTypeMask |
+ sDataFormat.ChannelStatusMask |
+ sDataFormat.ValidityBitMask |
+ sDataFormat.ParityErrorMask);
+
+ hspdif->Instance->CR = tmpreg;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+===============================================================================
+##### IO operation functions #####
+===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPDIFRX data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer start-up.
+ The end of the data processing will be indicated through the
+ dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_SPDIFRX_ReceiveDataFlow()
+ (++) HAL_SPDIFRX_ReceiveControlFlow()
+ (+@) Do not use blocking mode to receive both control and data flow at the same time.
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
+ (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
+ (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_SPDIFRX_RxCpltCallback()
+ (++) HAL_SPDIFRX_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Receives an amount of data (Data Flow) in blocking mode.
+ * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains
+ * the configuration information for SPDIFRX module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+{
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Start synchronisation */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+
+ /* Receive data flow */
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*pData++) = hspdif->Instance->DR;
+ Size--;
+ }
+
+ /* SPDIFRX ready */
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data (Control Flow) in blocking mode.
+ * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains
+ * the configuration information for SPDIFRX module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+{
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+
+ /* Receive control flow */
+ while(Size > 0)
+ {
+ /* Wait until CSRNE flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*pData++) = hspdif->Instance->CSR;
+ Size--;
+ }
+
+ /* SPDIFRX ready */
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be received .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->pRxBuffPtr = pData;
+ hspdif->RxXferSize = Size;
+ hspdif->RxXferCount = Size;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* Check if a receive process is ongoing or not */
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+
+ /* Enable the SPDIFRX PE Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+ /* Enable the SPDIFRX OVR Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ /* Enable the SPDIFRX RXNE interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample (Control Flow) to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->pCsBuffPtr = pData;
+ hspdif->CsXferSize = Size;
+ hspdif->CsXferCount = Size;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* Check if a receive process is ongoing or not */
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+
+ /* Enable the SPDIFRX PE Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+ /* Enable the SPDIFRX OVR Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ /* Enable the SPDIFRX CSRNE interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Data Flow) mode with DMA
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ {
+ hspdif->pRxBuffPtr = pData;
+ hspdif->RxXferSize = Size;
+ hspdif->RxXferCount = Size;
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+ hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
+
+ /* Set the SPDIFRX Rx DMA transfer complete callback */
+ hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
+
+ /* Enable the DMA request */
+ HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
+
+ /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
+ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with DMA
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data (Control Flow) sample to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ {
+ hspdif->pCsBuffPtr = pData;
+ hspdif->CsXferSize = Size;
+ hspdif->CsXferCount = Size;
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+ hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
+
+ /* Set the SPDIFRX Rx DMA transfer complete callback */
+ hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
+
+ /* Set the DMA error callback */
+ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
+
+ /* Enable the DMA request */
+ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
+
+ /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
+ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief stop the audio stream receive from the Media.
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ /* Disable the SPDIFRX DMA requests */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+
+ /* Disable the SPDIFRX DMA channel */
+ __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
+ __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+
+ /* Disable SPDIFRX peripheral */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SPDIFRX interrupt request.
+ * @param hspdif: SPDIFRX handle
+ * @retval HAL status
+ */
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
+ SPDIFRX_ReceiveDataFlow_IT(hspdif);
+ }
+
+ /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
+ SPDIFRX_ReceiveControlFlow_IT(hspdif);
+ }
+
+ /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
+
+ /* Change the SPDIFRX error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
+
+ /* the transfer is not stopped */
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+ }
+
+ /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
+
+ /* Change the SPDIFRX error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
+
+ /* the transfer is not stopped */
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+ }
+
+}
+
+/**
+ * @brief Rx Transfer (Data flow) half completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer (Data flow) completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx (Control flow) Transfer half completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer (Control flow) completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPDIFRX error callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+===============================================================================
+##### Peripheral State and Errors functions #####
+===============================================================================
+[..]
+This subsection permit to get in run-time the status of the peripheral
+and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPDIFRX state
+ * @param hspdif : SPDIFRX handle
+ * @retval HAL state
+ */
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
+{
+ return hspdif->State;
+}
+
+/**
+ * @brief Return the SPDIFRX error code
+ * @param hspdif : SPDIFRX handle
+ * @retval SPDIFRX Error Code
+ */
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
+{
+ return hspdif->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA SPDIFRX receive process (Data flow) complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+ hspdif->RxXferCount = 0;
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX receive process (Data flow) half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
+}
+
+
+/**
+ * @brief DMA SPDIFRX receive process (Control flow) complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Cb DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+ hspdif->CsXferCount = 0;
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX receive process (Control flow) half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX communication error callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Cb DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
+ hspdif->RxXferCount = 0;
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+}
+
+
+/**
+ * @brief Receive an amount of data (Data Flow) with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Receive data */
+ (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
+ hspdif->RxXferCount--;
+
+ if(hspdif->RxXferCount == 0)
+ {
+ /* Disable RXNE/PE and OVR interrupts */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Receive data */
+ (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
+ hspdif->CsXferCount--;
+
+ if(hspdif->CsXferCount == 0)
+ {
+ /* Disable CSRNE interrupt */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+ }
+}
+
+/**
+ * @brief This function handles SPDIFRX Communication Timeout.
+ * @param hspdif: SPDIFRX handle
+ * @param Flag: Flag checked
+ * @param Status: Value of the flag expected
+ * @param Timeout: Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h Thu Apr 30 13:45:11 2015 +0100
@@ -0,0 +1,559 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spdifrx.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 09-March-2015
+ * @brief Header file of SPDIFRX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SPDIFRX_H
+#define __STM32F4xx_HAL_SPDIFRX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPDIFRX
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPDIFRX Init structure definition
+ */
+typedef struct
+{
+ uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
+ This parameter can be a value of @ref SPDIFRX_Input_Selection */
+
+ uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
+ This parameter can be a value of @ref SPDIFRX_Max_Retries */
+
+ uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
+ This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
+
+ uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
+ This parameter can be a value of @ref SPDIFRX_Channel_Selection */
+
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
+ This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+
+}SPDIFRX_InitTypeDef;
+
+/**
+ * @brief SPDIFRX SetDataFormat structure definition
+ */
+typedef struct
+{
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
+ This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+
+}SPDIFRX_SetDataFormatTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SPDIFRX_STATE_RESET = 0x00, /*!< SPDIFRX not yet initialized or disabled */
+ HAL_SPDIFRX_STATE_READY = 0x01, /*!< SPDIFRX initialized and ready for use */
+ HAL_SPDIFRX_STATE_BUSY = 0x02, /*!< SPDIFRX internal process is ongoing */
+ HAL_SPDIFRX_STATE_BUSY_RX = 0x03, /*!< SPDIFRX internal Data Flow RX process is ongoing */
+ HAL_SPDIFRX_STATE_BUSY_CX = 0x04, /*!< SPDIFRX internal Control Flow RX process is ongoing */
+ HAL_SPDIFRX_STATE_ERROR = 0x07 /*!< SPDIFRX error state */
+}HAL_SPDIFRX_StateTypeDef;
+
+/**
+ * @brief SPDIFRX handle Structure definition
+ */
+typedef struct
+{
+ SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
+
+ SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
+
+ uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
+
+ uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
+
+ __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
+
+ __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
+
+ __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
+
+ __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
+
+ __IO uint32_t ErrorCode; /* SPDIFRX Error code */
+
+}SPDIFRX_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
+ * @{
+ */
+/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
+ * @{
+ */
+#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
+#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
+#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004) /*!< Parity error */
+#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
+#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010) /*!< Unknown Error error */
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
+ * @{
+ */
+#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000)
+#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000)
+#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000)
+#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
+ * @{
+ */
+#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000)
+#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000)
+#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000)
+#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
+ * @{
+ */
+#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
+* @{
+*/
+#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
+* @{
+*/
+#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
+* @{
+*/
+#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
+* @{
+*/
+#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
+ * @{
+ */
+#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000)
+#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
+ * @{
+ */
+#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000)
+#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010)
+#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
+ * @{
+ */
+#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000)
+#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_State SPDIFRX State
+ * @{
+ */
+
+#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC)
+#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)
+#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
+ * @{
+ */
+#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
+#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
+#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
+#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
+#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
+#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
+#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
+ * @{
+ */
+#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
+#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
+#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
+#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
+#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
+#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
+#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
+#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
+#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPDIFRX handle state
+ * @param __HANDLE__: SPDIFRX handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
+
+/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
+
+/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
+
+
+/** @brief Enable the specified SPDIFRX peripheral (RCV State).
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
+
+
+/** @brief Enable or disable the specified SPDIFRX interrupts.
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_IT_RXNE
+ * @arg SPDIFRX_IT_CSRNE
+ * @arg SPDIFRX_IT_PERRIE
+ * @arg SPDIFRX_IT_OVRIE
+ * @arg SPDIFRX_IT_SBLKIE
+ * @arg SPDIFRX_IT_SYNCDIE
+ * @arg SPDIFRX_IT_IFEIE
+ * @retval None
+ */
+#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
+
+/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_IT_RXNE
+ * @arg SPDIFRX_IT_CSRNE
+ * @arg SPDIFRX_IT_PERRIE
+ * @arg SPDIFRX_IT_OVRIE
+ * @arg SPDIFRX_IT_SBLKIE
+ * @arg SPDIFRX_IT_SYNCDIE
+ * @arg SPDIFRX_IT_IFEIE
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified SPDIFRX flag is set or not.
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_FLAG_RXNE
+ * @arg SPDIFRX_FLAG_CSRNE
+ * @arg SPDIFRX_FLAG_PERR
+ * @arg SPDIFRX_FLAG_OVR
+ * @arg SPDIFRX_FLAG_SBD
+ * @arg SPDIFRX_FLAG_SYNCD
+ * @arg SPDIFRX_FLAG_FERR
+ * @arg SPDIFRX_FLAG_SERR
+ * @arg SPDIFRX_FLAG_TERR
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_FLAG_PERR
+ * @arg SPDIFRX_FLAG_OVR
+ * @arg SPDIFRX_SR_SBD
+ * @arg SPDIFRX_SR_SYNCD
+ * @retval None
+ */
+#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPDIFRX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
+/**
+ * @}
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+/**
+ * @}
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
+ * @{
+ */
+#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
+ ((INPUT) == SPDIFRX_INPUT_IN2) || \
+ ((INPUT) == SPDIFRX_INPUT_IN3) || \
+ ((INPUT) == SPDIFRX_INPUT_IN0))
+#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
+ ((RET) == SPDIFRX_MAXRETRIES_3) || \
+ ((RET) == SPDIFRX_MAXRETRIES_15) || \
+ ((RET) == SPDIFRX_MAXRETRIES_63))
+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
+ ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
+ ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
+ ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
+ ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
+ ((CHANNEL) == SPDIFRX_CHANNEL_B))
+#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
+ ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+
+#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
+ ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SPDIFRX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_spi.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -35,7 +35,7 @@
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream
- (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
@@ -43,7 +43,7 @@
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SPI_MspInit() API.
+ by calling the customized HAL_SPI_MspInit() API.
[..]
Circular mode restriction:
(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
@@ -59,7 +59,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -93,7 +93,7 @@
* @{
*/
-/** @defgroup SPI
+/** @defgroup SPI SPI
* @brief SPI HAL module driver
* @{
*/
@@ -106,11 +106,15 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_TxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxISR(SPI_HandleTypeDef *hspi);
+static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi);
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -119,14 +123,16 @@
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
-/** @defgroup SPI_Group1 Initialization and de-initialization functions
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -134,7 +140,7 @@
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the SPIx peripheral:
+ de-initialize the SPIx peripheral:
(+) User must implement HAL_SPI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
@@ -153,7 +159,7 @@
(++) CRC Polynomial if CRC enabled
(+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx periperal.
+ of the selected SPIx peripheral.
@endverbatim
* @{
@@ -189,13 +195,15 @@
if(hspi->State == HAL_SPI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
}
hspi->State = HAL_SPI_STATE_BUSY;
- /* Disble the selected SPI peripheral */
+ /* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
@@ -259,7 +267,7 @@
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspInit could be implenetd in the user file
+ the HAL_SPI_MspInit could be implemented in the user file
*/
}
@@ -272,7 +280,7 @@
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit could be implenetd in the user file
+ the HAL_SPI_MspDeInit could be implemented in the user file
*/
}
@@ -280,7 +288,7 @@
* @}
*/
-/** @defgroup SPI_Group2 IO operation functions
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -302,30 +310,11 @@
dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
+ will be executed respectively at the end of the transmit or Receive process
The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
- (#) Blocking mode APIs are :
- (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive() in full duplex mode
-
- (#) Non Blocking mode API's with Interrupt are :
- (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
- (++) HAL_SPI_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SPI_TxCpltCallback()
- (++) HAL_SPI_RxCpltCallback()
- (++) HAL_SPI_ErrorCallback()
- (++) HAL_SPI_TxRxCpltCallback()
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
@endverbatim
* @{
@@ -371,15 +360,15 @@
hspi->RxXferCount = 0;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Configure communication direction : 1Line */
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
/* Check if the SPI is already enabled */
@@ -408,7 +397,7 @@
hspi->TxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -434,7 +423,7 @@
hspi->TxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -454,7 +443,7 @@
return HAL_TIMEOUT;
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -514,13 +503,13 @@
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@@ -554,7 +543,7 @@
hspi->RxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -575,7 +564,7 @@
hspi->RxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -601,7 +590,7 @@
hspi->RxXferCount--;
/* Wait until RXNE flag is set: CRC Received */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
@@ -611,6 +600,7 @@
/* Read CRC to Flush RXNE flag */
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
}
if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
@@ -623,12 +613,12 @@
tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
/* Check if CRC error occurred */
- if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
+ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -698,9 +688,9 @@
hspi->TxISR = 0;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Check if the SPI is already enabled */
@@ -722,7 +712,7 @@
if(hspi->TxXferCount == 0)
{
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -752,7 +742,7 @@
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -793,7 +783,7 @@
if(hspi->TxXferCount == 0)
{
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -821,7 +811,7 @@
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -850,7 +840,7 @@
}
/* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag is set */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@@ -860,6 +850,7 @@
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
}
/* Wait until Busy flag is reset before disabling SPI */
@@ -873,14 +864,14 @@
tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
/* Check if CRC error occurred */
- if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
+ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Process Unlocked */
@@ -940,13 +931,13 @@
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
@@ -1012,7 +1003,7 @@
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
@@ -1024,9 +1015,9 @@
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Enable TXE and ERR interrupt */
@@ -1102,9 +1093,9 @@
hspi->RxXferCount = Size;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Enable TXE, RXNE and ERR interrupt */
@@ -1168,13 +1159,13 @@
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Set the SPI TxDMA Half transfer complete callback */
@@ -1189,9 +1180,6 @@
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
- /* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1202,6 +1190,9 @@
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable Tx DMA Request */
+ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
return HAL_OK;
}
else
@@ -1213,7 +1204,7 @@
/**
* @brief Receive an amount of data in no-blocking mode with DMA
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size: amount of data to be sent
@@ -1248,7 +1239,7 @@
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
{
@@ -1260,9 +1251,9 @@
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Set the SPI RxDMA Half transfer complete callback */
@@ -1277,9 +1268,6 @@
/* Enable the Rx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
- /* Enable Rx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1290,6 +1278,9 @@
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable Rx DMA Request */
+ hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
return HAL_OK;
}
else
@@ -1348,9 +1339,9 @@
hspi->TxISR = 0;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
@@ -1378,16 +1369,26 @@
/* Enable Rx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
- /* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
hspi->hdmatx->XferCpltCallback = HAL_NULL;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
+
+ if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+ }
+ else
+ {
+ hspi->hdmatx->XferErrorCallback = HAL_NULL;
+ }
+
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
@@ -1398,8 +1399,6 @@
/* Enable Tx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
return HAL_OK;
}
else
@@ -1408,7 +1407,6 @@
}
}
-
/**
* @brief Pauses the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -1453,8 +1451,8 @@
/**
* @brief Stops the DMA Transfer.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
@@ -1507,7 +1505,7 @@
tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
- /* SPI in mode Tramitter ---------------------------------------------------*/
+ /* SPI in mode Transmitter ---------------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
hspi->TxISR(hspi);
@@ -1564,7 +1562,7 @@
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback could be implenetd in the user file
+ the HAL_SPI_TxCpltCallback could be implemented in the user file
*/
}
@@ -1577,7 +1575,7 @@
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback() could be implenetd in the user file
+ the HAL_SPI_RxCpltCallback() could be implemented in the user file
*/
}
@@ -1590,7 +1588,7 @@
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
+ the HAL_SPI_TxRxCpltCallback() could be implemented in the user file
*/
}
@@ -1603,7 +1601,7 @@
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
+ the HAL_SPI_TxHalfCpltCallback could be implemented in the user file
*/
}
@@ -1616,7 +1614,7 @@
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
+ the HAL_SPI_RxHalfCpltCallback() could be implemented in the user file
*/
}
@@ -1629,7 +1627,7 @@
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
+ the HAL_SPI_TxRxHalfCpltCallback() could be implemented in the user file
*/
}
@@ -1642,7 +1640,7 @@
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : - This function Should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback() could be implenetd in the user file.
+ the HAL_SPI_ErrorCallback() could be implemented in the user file.
- The ErrorCode parameter in the hspi handle is updated by the SPI processes
and user can use HAL_SPI_GetError() API to check the latest error occurred.
*/
@@ -1652,7 +1650,7 @@
* @}
*/
-/** @defgroup SPI_Group3 Peripheral State and Errors functions
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SPI control functions
*
@verbatim
@@ -1684,7 +1682,7 @@
* the configuration information for SPI module.
* @retval SPI Error Code
*/
-HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
return hspi->ErrorCode;
}
@@ -1721,7 +1719,7 @@
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -1777,7 +1775,7 @@
if(hspi->TxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* calculate and transfer CRC on Tx line */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@@ -1796,7 +1794,7 @@
{
__IO uint16_t tmpreg;
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
@@ -1806,6 +1804,7 @@
/* Read CRC to reset RXNE flag */
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
@@ -1819,7 +1818,7 @@
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
}
@@ -1914,7 +1913,7 @@
hspi->RxXferCount--;
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set CRC Next to calculate CRC on Rx side */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@@ -1958,7 +1957,7 @@
hspi->State = HAL_SPI_STATE_READY;
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -1989,47 +1988,54 @@
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ SPI_DMAEndTransmitReceive(hspi);
+ }
+ /* SPI_DIRECTION_1LINE or SPI_DIRECTION_2LINES_RXONLY */
+ else
{
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Disable Rx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ hspi->RxXferCount = 0;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
}
- /* Disable Rx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- hspi->RxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- /* Wait until RXNE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
-
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
-
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-
/* Check if Errors has been detected during transfer */
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
@@ -2047,6 +2053,61 @@
}
/**
+ * @brief End DMA SPI transmit receive process
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi)
+{
+ __IO uint16_t tmpreg;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Check if CRC is done on going (RXNE flag set) */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /* Wait until RXNE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+ }
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+ /* Disable Tx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Disable Rx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0;
+ hspi->RxXferCount = 0;
+}
+
+/**
* @brief DMA SPI transmit receive process complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
@@ -2058,52 +2119,10 @@
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
- {
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
- {
- /* Check if CRC is done on going (RXNE flag set) */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
- {
- /* Wait until RXNE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
- }
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
- /* Disable Tx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ { /**/
+ SPI_DMAEndTransmitReceive(hspi);
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
-
- /* Disable Rx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
-
- hspi->State = HAL_SPI_STATE_READY;
-
+ hspi->State = HAL_SPI_STATE_READY;
/* Check if Errors has been detected during transfer */
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
@@ -2180,6 +2199,9 @@
* @brief This function handles SPI Communication Timeout.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param Status: Flag status to check: RESET or set
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
@@ -2209,9 +2231,9 @@
__HAL_SPI_DISABLE(hspi);
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
hspi->State= HAL_SPI_STATE_READY;
@@ -2243,9 +2265,9 @@
__HAL_SPI_DISABLE(hspi);
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
hspi->State= HAL_SPI_STATE_READY;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_spi.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
/**
* @brief SPI Configuration Structure definition
*/
@@ -116,21 +119,6 @@
}HAL_SPI_StateTypeDef;
/**
- * @brief HAL SPI Error Code structure definition
- */
-typedef enum
-{
- HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
- HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
- HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
- HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
- HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
- HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
-
-}HAL_SPI_ErrorTypeDef;
-
-/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
@@ -163,99 +151,90 @@
__IO HAL_SPI_StateTypeDef State; /* SPI communication state */
- __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
+ __IO uint32_t ErrorCode; /* SPI Error code */
}SPI_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
-/** @defgroup SPI_mode
+/** @defgroup SPI_Error_Code SPI Error Code
+ * @brief SPI Error Code
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000010) /*!< Flag: RXNE,TXE, BSY */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
/**
* @}
*/
-/** @defgroup SPI_Direction_mode
+/** @defgroup SPI_Direction_mode SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
/**
* @}
*/
-/** @defgroup SPI_data_size
+/** @defgroup SPI_data_size SPI Data Size
* @{
*/
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT))
/**
* @}
*/
-/** @defgroup SPI_Clock_Polarity
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup SPI_Clock_Phase
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
/**
* @}
*/
-/** @defgroup SPI_Slave_Select_management
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
/**
* @}
*/
-/** @defgroup SPI_BaudRate_Prescaler
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
@@ -266,56 +245,38 @@
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
/**
* @}
*/
-/** @defgroup SPI_MSB_LSB_transmission
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transsmission
* @{
*/
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
/**
* @}
*/
-/** @defgroup SPI_TI_mode
+/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
-#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
-#define SPI_TIMODE_ENABLED SPI_CR2_FRF
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
- ((MODE) == SPI_TIMODE_ENABLED))
+#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
*/
-/** @defgroup SPI_CRC_Calculation
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
-#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
+#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
-/** @defgroup SPI_Interrupt_configuration_definition
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
@@ -325,7 +286,7 @@
* @}
*/
-/** @defgroup SPI_Flag_definition
+/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
#define SPI_FLAG_RXNE SPI_SR_RXNE
@@ -335,7 +296,6 @@
#define SPI_FLAG_OVR SPI_SR_OVR
#define SPI_FLAG_BSY SPI_SR_BSY
#define SPI_FLAG_FRE SPI_SR_FRE
-
/**
* @}
*/
@@ -345,7 +305,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
/** @brief Reset SPI handle state
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
@@ -406,44 +368,74 @@
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+ UNUSED(tmpreg); \
+ } while(0)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
- (__HANDLE__)->Instance->SR;}while(0)
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ }while(0)
+
+/** @brief Enable SPI
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
*/
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
-
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
-#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
+/** @brief Disable SPI
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
-#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
- (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
-
-/* Exported functions --------------------------------------------------------*/
-
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -466,10 +458,16 @@
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State and Control functions **************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
@@ -479,6 +477,95 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
+
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sram.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -64,7 +64,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -98,27 +98,27 @@
* @{
*/
-/** @defgroup SRAM
+/** @defgroup SRAM SRAM
* @brief SRAM driver modules
* @{
*/
#ifdef HAL_SRAM_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
/* Private functions ---------------------------------------------------------*/
-/** @defgroup SRAM_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
-
-/** @defgroup SRAM_Group1 Initialization and de-initialization functions
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -150,6 +150,8 @@
if(hsram->State == HAL_SRAM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
}
@@ -219,7 +221,7 @@
/**
* @brief DMA transfer complete callback.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -232,7 +234,7 @@
/**
* @brief DMA transfer complete error callback.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -247,7 +249,7 @@
* @}
*/
-/** @defgroup SRAM_Group2 Input and Output functions
+/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -567,7 +569,7 @@
* @}
*/
-/** @defgroup SRAM_Group3 Control functions
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
@@ -635,7 +637,7 @@
* @}
*/
-/** @defgroup SRAM_Group4 State functions
+/** @defgroup SRAM_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
@@ -660,7 +662,6 @@
{
return hsram->State;
}
-
/**
* @}
*/
@@ -668,7 +669,7 @@
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
#endif /* HAL_SRAM_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sram.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -48,23 +48,27 @@
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
#include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx)
/** @addtogroup SRAM
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+ * @{
+ */
/**
* @brief HAL SRAM State structures definition
*/
@@ -97,23 +101,49 @@
}SRAM_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
/** @brief Reset SRAM handle state
* @param __HANDLE__: SRAM handle
* @retval None
*/
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
@@ -123,26 +153,46 @@
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+/**
+ * @}
+ */
-void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
+/** @addtogroup SRAM_Exported_Functions_Group3
+ * @{
+ */
/* SRAM Control functions ******************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/* SRAM State functions *********************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
+/** @addtogroup SRAM_Exported_Functions_Group4
+ * @{
+ */
+/* SRAM State functions *********************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+/**
+ * @}
+ */
+
/**
* @}
*/
-
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -132,7 +132,7 @@
* @{
*/
-/** @defgroup TIM
+/** @defgroup TIM TIM
* @brief TIM HAL module driver
* @{
*/
@@ -143,6 +143,9 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@@ -163,13 +166,18 @@
static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @defgroup TIM_Group1 Time Base functions
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
* @brief Time Base functions
*
@verbatim
@@ -212,6 +220,8 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
}
@@ -403,7 +413,7 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
@@ -441,12 +451,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group2 Time Output Compare functions
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
* @brief Time Output Compare functions
*
@verbatim
@@ -488,7 +497,9 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
}
@@ -614,7 +625,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -748,7 +759,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -798,10 +809,10 @@
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -814,10 +825,10 @@
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -830,10 +841,10 @@
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -846,10 +857,10 @@
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -935,7 +946,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -948,12 +959,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group3 Time PWM functions
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
* @brief Time PWM functions
*
@verbatim
@@ -996,6 +1006,8 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
}
@@ -1121,7 +1133,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1258,7 +1270,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1308,10 +1320,10 @@
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -1324,10 +1336,10 @@
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -1340,10 +1352,10 @@
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -1356,10 +1368,10 @@
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -1445,7 +1457,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1458,12 +1470,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group4 Time Input Capture functions
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
* @brief Time Input Capture functions
*
@verbatim
@@ -1505,7 +1516,9 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
}
@@ -1792,10 +1805,10 @@
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
@@ -1808,10 +1821,10 @@
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
@@ -1824,10 +1837,10 @@
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
@@ -1840,10 +1853,10 @@
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
@@ -1935,7 +1948,7 @@
* @}
*/
-/** @defgroup TIM_Group5 Time One Pulse functions
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
* @brief Time One Pulse functions
*
@verbatim
@@ -1964,7 +1977,7 @@
* @param OnePulseMode: Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
@@ -1982,7 +1995,9 @@
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
}
@@ -2116,7 +2131,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -2195,7 +2210,7 @@
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -2205,12 +2220,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group6 Time Encoder functions
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
* @brief Time Encoder functions
*
@verbatim
@@ -2264,6 +2278,8 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
}
@@ -2293,7 +2309,7 @@
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
- /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
@@ -2381,6 +2397,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2423,6 +2440,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2466,6 +2484,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2514,6 +2533,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2565,6 +2585,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @param pData1: The destination Buffer address for IC1.
* @param pData2: The destination Buffer address for IC2.
* @param Length: The length of data to be transferred from TIM peripheral to memory.
@@ -2596,10 +2617,10 @@
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
@@ -2618,10 +2639,10 @@
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
@@ -2639,19 +2660,19 @@
case TIM_CHANNEL_ALL:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
@@ -2685,6 +2706,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2727,11 +2749,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group7 TIM IRQ handler management
+
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief IRQ handler management
*
@verbatim
@@ -2755,7 +2777,7 @@
/* Capture compare 1 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
@@ -2779,7 +2801,7 @@
/* Capture compare 2 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
@@ -2800,7 +2822,7 @@
/* Capture compare 3 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
@@ -2821,7 +2843,7 @@
/* Capture compare 4 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
@@ -2842,7 +2864,7 @@
/* TIM Update event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
HAL_TIM_PeriodElapsedCallback(htim);
@@ -2851,7 +2873,7 @@
/* TIM Break input event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
HAL_TIMEx_BreakCallback(htim);
@@ -2860,7 +2882,7 @@
/* TIM Trigger detection event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
HAL_TIM_TriggerCallback(htim);
@@ -2869,19 +2891,18 @@
/* TIM commutation event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
HAL_TIMEx_CommutationCallback(htim);
}
}
}
-
/**
* @}
*/
-/** @defgroup TIM_Group8 Peripheral Control functions
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -2921,7 +2942,6 @@
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
@@ -3096,7 +3116,8 @@
assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
-
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
htim->State = HAL_TIM_STATE_BUSY;
switch (Channel)
@@ -3202,7 +3223,7 @@
htim->State = HAL_TIM_STATE_BUSY;
- /* Extract the Ouput compare configuration from sConfig structure */
+ /* Extract the Output compare configuration from sConfig structure */
temp1.OCMode = sConfig->OCMode;
temp1.Pulse = sConfig->Pulse;
temp1.OCPolarity = sConfig->OCPolarity;
@@ -3292,25 +3313,25 @@
* the configuration information for TIM module.
* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
* This parameters can be on of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc: TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3322,7 +3343,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer: The Buffer address.
* @param BurstLength: DMA Burst length. This parameter can be one value
- * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3357,7 +3378,7 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3366,10 +3387,10 @@
case TIM_DMA_CC1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3378,10 +3399,10 @@
case TIM_DMA_CC2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3390,10 +3411,10 @@
case TIM_DMA_CC3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3402,10 +3423,10 @@
case TIM_DMA_CC4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3414,10 +3435,10 @@
case TIM_DMA_COM:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3429,7 +3450,7 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3462,6 +3483,48 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
@@ -3475,25 +3538,25 @@
* the configuration information for TIM module.
* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
* This parameters can be on of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc: TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3505,7 +3568,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer: The Buffer address.
* @param BurstLength: DMA Burst length. This parameter can be one value
- * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3540,7 +3603,7 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3549,10 +3612,10 @@
case TIM_DMA_CC1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3561,10 +3624,10 @@
case TIM_DMA_CC2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3573,10 +3636,10 @@
case TIM_DMA_CC3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3585,10 +3648,10 @@
case TIM_DMA_CC4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3597,10 +3660,10 @@
case TIM_DMA_COM:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3612,7 +3675,7 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3646,6 +3709,48 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
@@ -3659,16 +3764,16 @@
* the configuration information for TIM module.
* @param EventSource: specifies the event source.
* This parameter can be one of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
* @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+ * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
* @retval HAL status
*/
@@ -3942,7 +4047,7 @@
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module..
+ * the configuration information for TIM module.
* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
* This parameter can be one of the following values:
@@ -3965,7 +4070,7 @@
/* Reset the TI1 selection */
tmpcr2 &= ~TIM_CR2_TI1S;
- /* Set the the TI1 selection */
+ /* Set the TI1 selection */
tmpcr2 |= TI1_Selection;
/* Write to TIMxCR2 */
@@ -3977,7 +4082,7 @@
/**
* @brief Configures the TIM in Slave mode
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module..
+ * the configuration information for TIM module.
* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
@@ -3986,10 +4091,6 @@
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
@@ -3999,7 +4100,832 @@
htim->State = HAL_TIM_STATE_BUSY;
- /* Get the TIMx SMCR register value */
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim: TIM handle.
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0;
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+ return tmpreg;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) Timer Period elapsed callback
+ (+) Timer Output Compare callback
+ (+) Timer Input capture callback
+ (+) Timer Trigger callback
+ (+) Timer Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+
+}
+/**
+ * @brief Output Compare callback in non blocking mode
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Input Capture callback in non blocking mode
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non blocking mode
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non blocking mode
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non blocking mode
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base state
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC state
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM state
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture state
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode state
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode state
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx: TIM peripheral
+ * @param Structure: pointer on TIM Time Base required parameters
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1 = 0;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Auto-reload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1 and TIM8) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The output configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4);
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param ChannelState: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+ * @brief Time Output Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The output configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The output configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8);
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The output configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12);
+
+ /*if((TIMx == TIM1) || (TIMx == TIM8))*/
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 4 configuration
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sSlaveConfig: The slave configuration structure
+ * @retval None
+ */
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
/* Reset the Trigger Selection Bits */
@@ -4114,704 +5040,8 @@
default:
break;
}
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read the captured value from Capture Compare unit
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module..
- * @param Channel: TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval Captured value
- */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpreg = 0;
-
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
-
- break;
- }
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
-
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
-
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
-
- break;
- }
-
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
- return tmpreg;
}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Callbacks functions #####
- ==============================================================================
- [..]
- This section provides TIM callback functions:
- (+) Timer Period elapsed callback
- (+) Timer Output Compare callback
- (+) Timer Input capture callback
- (+) Timer Trigger callback
- (+) Timer Error callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Period elapsed callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
- */
-
-}
-/**
- * @brief Output Compare callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
-/**
- * @brief Input Capture callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timer error callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group10 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Base state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM OC state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM PWM state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Input Capture state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief TIM DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_ErrorCallback(htim);
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-}
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_IC_CaptureCallback(htim);
-
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_TriggerCallback(htim);
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx: TIM periheral
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- uint32_t tmpcr1 = 0;
- tmpcr1 = TIMx->CR1;
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
- }
-
- if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = (uint32_t)Structure->Prescaler;
-
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
- * @brief Time Ouput Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
-
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4);
-
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 3 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8);
-
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- tmpcr2 &= ~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 4 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- tmpccmrx &= ~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12);
-
- /*if((TIMx == TIM1) || (TIMx == TIM8))*/
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- }
- else
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
/**
* @brief Configure the Polarity and Filter for TI1.
@@ -4863,6 +5093,9 @@
* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
* @param TIM_ICFilter: Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
* @retval None
*/
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
@@ -4882,11 +5115,11 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12);
+ tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4);
+ tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -4943,6 +5176,9 @@
* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
* @param TIM_ICFilter: Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
* @retval None
*/
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
@@ -4962,11 +5198,11 @@
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= (TIM_ICFilter << 4);
+ tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
/* Select the Polarity and set the CC3E Bit */
tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= (TIM_ICPolarity << 8);
+ tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -4988,6 +5224,9 @@
* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
* @param TIM_ICFilter: Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
* @retval None
*/
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
@@ -5007,11 +5246,11 @@
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= (TIM_ICFilter << 12);
+ tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
/* Select the Polarity and set the CC4E Bit */
tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= (TIM_ICPolarity << 12);
+ tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -5021,7 +5260,7 @@
/**
* @brief Selects the Input Trigger source
* @param TIMx to select the TIM peripheral
- * @param InputTriggerSource: The Input Trigger source.
+ * @param TIM_ITRx: The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal Trigger 0
* @arg TIM_TS_ITR1: Internal Trigger 1
@@ -5046,6 +5285,7 @@
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
}
+
/**
* @brief Configures the TIMx External Trigger (ETR).
* @param TIMx to select the TIM peripheral
@@ -5081,37 +5321,6 @@
}
/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param ChannelState: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
-
-
-/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_tim.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-/** @addtogroup STM32F4xx_HAL
+/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+
/**
* @brief TIM Time base Configuration Structure definition
*/
@@ -293,13 +296,16 @@
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
}TIM_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
* @{
*/
-/** @defgroup TIM_Input_Channel_Polarity
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
* @{
*/
#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
@@ -309,7 +315,7 @@
* @}
*/
-/** @defgroup TIM_ETR_Polarity
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
@@ -318,7 +324,7 @@
* @}
*/
-/** @defgroup TIM_ETR_Prescaler
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
@@ -329,7 +335,7 @@
* @}
*/
-/** @defgroup TIM_Counter_Mode
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
@@ -337,31 +343,21 @@
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
- ((MODE) == TIM_COUNTERMODE_DOWN) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
/**
* @}
*/
-/** @defgroup TIM_ClockDivision
+/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV4))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_and_PWM_modes
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
* @{
*/
#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
@@ -373,102 +369,56 @@
#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_State
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
/**
* @}
*/
-/** @defgroup TIM_Output_Fast_State
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
- ((STATE) == TIM_OCFAST_ENABLE))
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_State
- * @{
- */
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
-
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCPOLARITY_LOW))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
* @{
*/
#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCNPOLARITY_LOW))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_Idle_State
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
* @{
*/
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
- ((STATE) == TIM_OCIDLESTATE_RESET))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_Idle_State
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
* @{
*/
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
- ((STATE) == TIM_OCNIDLESTATE_RESET))
/**
* @}
*/
-/** @defgroup TIM_Channel
+/** @defgroup TIM_Channel TIM Channel
* @{
*/
#define TIM_CHANNEL_1 ((uint32_t)0x0000)
@@ -477,40 +427,21 @@
#define TIM_CHANNEL_4 ((uint32_t)0x000C)
#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Polarity
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
- ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Selection
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
@@ -519,54 +450,42 @@
connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_TRC))
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Prescaler
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
/**
* @}
*/
-/** @defgroup TIM_One_Pulse_Mode
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
- ((MODE) == TIM_OPMODE_REPETITIVE))
/**
* @}
*/
-/** @defgroup TIM_Encoder_Mode
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
*/
#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
- ((MODE) == TIM_ENCODERMODE_TI2) || \
- ((MODE) == TIM_ENCODERMODE_TI12))
+
/**
* @}
*/
-/** @defgroup TIM_Interrupt_definition
+/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
* @{
*/
#define TIM_IT_UPDATE (TIM_DIER_UIE)
@@ -577,24 +496,20 @@
#define TIM_IT_COM (TIM_DIER_COMIE)
#define TIM_IT_TRIGGER (TIM_DIER_TIE)
#define TIM_IT_BREAK (TIM_DIER_BIE)
-
-#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_TRIGGER) || \
- ((IT) == TIM_IT_BREAK))
/**
* @}
*/
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+/**
+ * @}
+ */
-/** @defgroup TIM_DMA_sources
+/** @defgroup TIM_DMA_sources TIM DMA sources
* @{
*/
#define TIM_DMA_UPDATE (TIM_DIER_UDE)
@@ -604,28 +519,27 @@
#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define TIM_DMA_COM (TIM_DIER_COMDE)
#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
/**
* @}
*/
-/** @defgroup TIM_Event_Source
+/** @defgroup TIM_Event_Source TIM Event Source
* @{
*/
-#define TIM_EventSource_Update TIM_EGR_UG
-#define TIM_EventSource_CC1 TIM_EGR_CC1G
-#define TIM_EventSource_CC2 TIM_EGR_CC2G
-#define TIM_EventSource_CC3 TIM_EGR_CC3G
-#define TIM_EventSource_CC4 TIM_EGR_CC4G
-#define TIM_EventSource_COM TIM_EGR_COMG
-#define TIM_EventSource_Trigger TIM_EGR_TG
-#define TIM_EventSource_Break TIM_EGR_BG
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
+
/**
* @}
*/
-/** @defgroup TIM_Flag_definition
+/** @defgroup TIM_Flag_definition TIM Flag definition
* @{
*/
#define TIM_FLAG_UPDATE (TIM_SR_UIF)
@@ -640,24 +554,11 @@
#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
-
-#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_TRIGGER) || \
- ((FLAG) == TIM_FLAG_BREAK) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
/**
* @}
*/
-/** @defgroup TIM_Clock_Source
+/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
@@ -670,22 +571,11 @@
#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
/**
* @}
*/
-/** @defgroup TIM_Clock_Polarity
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
@@ -693,159 +583,106 @@
#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
/**
* @}
*/
-/** @defgroup TIM_Clock_Prescaler
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
*/
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
* @}
*/
-/** @defgroup TIM_Clock_Filter
- * @{
- */
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Source
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
/**
* @}
*/
-/** @defgroup TIM_ClearInput_Polarity
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
/**
* @}
*/
-/** @defgroup TIM_ClearInput_Prescaler
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
*/
#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Filter
- * @{
- */
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
*/
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
/**
* @}
*/
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Lock_level
+
+/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
/**
* @}
*/
-/** @defgroup TIM_Break_Input_enable_disable
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
* @{
*/
#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Break_Polarity
+
+/** @defgroup TIM_Break_Polarity TIM Break Polarity
* @{
*/
#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
/**
* @}
*/
-/** @defgroup TIM_AOE_Bit_Set_Reset
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
* @{
*/
#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Master_Mode_Selection
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
#define TIM_TRGO_RESET ((uint32_t)0x0000)
@@ -855,22 +692,12 @@
#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
/**
* @}
*/
-/** @defgroup TIM_Slave_Mode
+
+/** @defgroup TIM_Slave_Mode TIM Slave Mode
* @{
*/
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
@@ -878,28 +705,20 @@
#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
/**
* @}
*/
-/** @defgroup TIM_Master_Slave_Mode
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
* @{
*/
-
#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Selection
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
#define TIM_TS_ITR0 ((uint32_t)0x0000)
@@ -911,28 +730,11 @@
#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
#define TIM_TS_ETRF ((uint32_t)0x0070)
#define TIM_TS_NONE ((uint32_t)0xFFFF)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_NONE))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Polarity
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
@@ -940,151 +742,84 @@
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Prescaler
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
* @{
*/
#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Filter
- * @{
- */
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
- /** @defgroup TIM_TI1_Selection
+/** @defgroup TIM_TI1_Selection TIM TI1 Selection
* @{
*/
#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
/**
* @}
*/
-/** @defgroup TIM_DMA_Base_address
+/** @defgroup TIM_DMA_Base_address TIM DMA Base address
* @{
*/
-#define TIM_DMABase_CR1 (0x00000000)
-#define TIM_DMABase_CR2 (0x00000001)
-#define TIM_DMABase_SMCR (0x00000002)
-#define TIM_DMABase_DIER (0x00000003)
-#define TIM_DMABase_SR (0x00000004)
-#define TIM_DMABase_EGR (0x00000005)
-#define TIM_DMABase_CCMR1 (0x00000006)
-#define TIM_DMABase_CCMR2 (0x00000007)
-#define TIM_DMABase_CCER (0x00000008)
-#define TIM_DMABase_CNT (0x00000009)
-#define TIM_DMABase_PSC (0x0000000A)
-#define TIM_DMABase_ARR (0x0000000B)
-#define TIM_DMABase_RCR (0x0000000C)
-#define TIM_DMABase_CCR1 (0x0000000D)
-#define TIM_DMABase_CCR2 (0x0000000E)
-#define TIM_DMABase_CCR3 (0x0000000F)
-#define TIM_DMABase_CCR4 (0x00000010)
-#define TIM_DMABase_BDTR (0x00000011)
-#define TIM_DMABase_DCR (0x00000012)
-#define TIM_DMABase_OR (0x00000013)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
+#define TIM_DMABASE_CR1 (0x00000000)
+#define TIM_DMABASE_CR2 (0x00000001)
+#define TIM_DMABASE_SMCR (0x00000002)
+#define TIM_DMABASE_DIER (0x00000003)
+#define TIM_DMABASE_SR (0x00000004)
+#define TIM_DMABASE_EGR (0x00000005)
+#define TIM_DMABASE_CCMR1 (0x00000006)
+#define TIM_DMABASE_CCMR2 (0x00000007)
+#define TIM_DMABASE_CCER (0x00000008)
+#define TIM_DMABASE_CNT (0x00000009)
+#define TIM_DMABASE_PSC (0x0000000A)
+#define TIM_DMABASE_ARR (0x0000000B)
+#define TIM_DMABASE_RCR (0x0000000C)
+#define TIM_DMABASE_CCR1 (0x0000000D)
+#define TIM_DMABASE_CCR2 (0x0000000E)
+#define TIM_DMABASE_CCR3 (0x0000000F)
+#define TIM_DMABASE_CCR4 (0x00000010)
+#define TIM_DMABASE_BDTR (0x00000011)
+#define TIM_DMABASE_DCR (0x00000012)
+#define TIM_DMABASE_OR (0x00000013)
/**
* @}
*/
-/** @defgroup TIM_DMA_Burst_Length
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABurstLength_1Transfer (0x00000000)
-#define TIM_DMABurstLength_2Transfers (0x00000100)
-#define TIM_DMABurstLength_3Transfers (0x00000200)
-#define TIM_DMABurstLength_4Transfers (0x00000300)
-#define TIM_DMABurstLength_5Transfers (0x00000400)
-#define TIM_DMABurstLength_6Transfers (0x00000500)
-#define TIM_DMABurstLength_7Transfers (0x00000600)
-#define TIM_DMABurstLength_8Transfers (0x00000700)
-#define TIM_DMABurstLength_9Transfers (0x00000800)
-#define TIM_DMABurstLength_10Transfers (0x00000900)
-#define TIM_DMABurstLength_11Transfers (0x00000A00)
-#define TIM_DMABurstLength_12Transfers (0x00000B00)
-#define TIM_DMABurstLength_13Transfers (0x00000C00)
-#define TIM_DMABurstLength_14Transfers (0x00000D00)
-#define TIM_DMABurstLength_15Transfers (0x00000E00)
-#define TIM_DMABurstLength_16Transfers (0x00000F00)
-#define TIM_DMABurstLength_17Transfers (0x00001000)
-#define TIM_DMABurstLength_18Transfers (0x00001100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup DMA_Handle_index
+/** @defgroup DMA_Handle_index DMA Handle index
* @{
*/
#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
@@ -1098,7 +833,7 @@
* @}
*/
-/** @defgroup Channel_CC_State
+/** @defgroup Channel_CC_State Channel CC State
* @{
*/
#define TIM_CCx_ENABLE ((uint32_t)0x0001)
@@ -1114,7 +849,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
/** @brief Reset TIM handle state
* @param __HANDLE__: TIM handle
* @retval None
@@ -1136,11 +873,6 @@
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
/**
* @brief Disable the TIM peripheral.
* @param __HANDLE__: TIM handle
@@ -1148,9 +880,9 @@
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
{ \
- if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
@@ -1166,9 +898,9 @@
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
{ \
- if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
@@ -1182,24 +914,36 @@
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+
/**
* @brief Sets the TIM Capture Compare Register value on runtime without
* calling another time ConfigChannel function.
@@ -1213,7 +957,7 @@
* @param __COMPARE__: specifies the Capture Compare register new value.
* @retval None
*/
-#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
/**
@@ -1227,7 +971,7 @@
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval None
*/
-#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
/**
@@ -1236,14 +980,14 @@
* @param __COUNTER__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
* @brief Gets the TIM Counter Register value on runtime.
* @param __HANDLE__: TIM handle.
* @retval None
*/
-#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Sets the TIM Autoreload Register value on runtime without calling
@@ -1252,7 +996,7 @@
* @param __AUTORELOAD__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
@@ -1262,7 +1006,7 @@
* @param __HANDLE__: TIM handle.
* @retval None
*/
-#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Sets the TIM Clock Division value on runtime without calling
@@ -1275,7 +1019,7 @@
* @arg TIM_CLOCKDIVISION_DIV4
* @retval None
*/
-#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \
(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
@@ -1286,7 +1030,7 @@
* @param __HANDLE__: TIM handle.
* @retval None
*/
-#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Sets the TIM Input Capture prescaler on runtime without calling
@@ -1306,10 +1050,10 @@
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
* @retval None
*/
-#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \
- __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
- __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0)
/**
@@ -1323,11 +1067,58 @@
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
* @retval None
*/
-#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * Counter overflow/underflow
+ * Setting the UG bit
+ * Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+
+/**
+ * @brief Sets the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__: Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
/**
* @}
*/
@@ -1336,6 +1127,13 @@
#include "stm32f4xx_hal_tim_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1
+ * @{
+ */
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
@@ -1351,7 +1149,13 @@
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+/** @addtogroup TIM_Exported_Functions_Group2
+ * @{
+ */
/* Timer Output Compare functions **********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
@@ -1367,6 +1171,13 @@
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3
+ * @{
+ */
/* Timer PWM functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
@@ -1382,6 +1193,13 @@
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4
+ * @{
+ */
/* Timer Input Capture functions ***********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
@@ -1397,6 +1215,13 @@
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5
+ * @{
+ */
/* Timer One Pulse functions ***************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
@@ -1410,6 +1235,13 @@
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6
+ * @{
+ */
/* Timer Encoder functions *****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
@@ -1425,9 +1257,23 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7
+ * @{
+ */
/* Interrupt Handler functions **********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8
+ * @{
+ */
/* Control functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
@@ -1437,6 +1283,7 @@
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
@@ -1446,6 +1293,13 @@
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group9
+ * @{
+ */
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
@@ -1454,6 +1308,13 @@
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group10
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
@@ -1462,14 +1323,274 @@
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
+ * @{
+ */
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_DCR) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Mask_Definitions TIM Mask Definition
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -103,7 +103,7 @@
* @{
*/
-/** @defgroup TIMEx
+/** @defgroup TIMEx TIMEx
* @brief TIM HAL module driver
* @{
*/
@@ -114,15 +114,21 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIMEx_Private_Functions
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Exported Functions
* @{
*/
-/** @defgroup TIMEx_Group1 Timer Hall Sensor functions
+/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
*
@verbatim
@@ -398,9 +404,9 @@
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Set the DMA Input Capture 1 Callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream for Capture 1*/
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
@@ -440,12 +446,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group2 Timer Complementary Output Compare functions
+/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
*
@verbatim
@@ -472,10 +477,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -486,7 +491,7 @@
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -503,10 +508,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -517,7 +522,7 @@
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -534,10 +539,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -579,12 +584,15 @@
break;
}
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
@@ -599,10 +607,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -643,13 +651,19 @@
default:
break;
}
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -664,10 +678,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@@ -697,10 +711,10 @@
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -713,10 +727,10 @@
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -729,10 +743,10 @@
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -745,10 +759,10 @@
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -765,7 +779,7 @@
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -782,10 +796,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -830,7 +844,7 @@
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -842,12 +856,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group3 Timer Complementary PWM functions
+/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
*
@verbatim
@@ -883,10 +896,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -897,7 +910,7 @@
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -913,10 +926,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -927,7 +940,7 @@
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -944,10 +957,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -995,7 +1008,7 @@
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -1012,10 +1025,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1057,13 +1070,16 @@
break;
}
- /* Disable the TIM Break interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1080,10 +1096,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@@ -1113,10 +1129,10 @@
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -1129,10 +1145,10 @@
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -1145,10 +1161,10 @@
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -1161,10 +1177,10 @@
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -1181,7 +1197,7 @@
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -1198,10 +1214,10 @@
* the configuration information for TIM module.
* @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1/
- * TIM_CHANNEL_2/
- * TIM_CHANNEL_3/
- * TIM_CHANNEL_4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1246,7 +1262,7 @@
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1263,7 +1279,7 @@
* @}
*/
-/** @defgroup TIMEx_Group4 Timer Complementary One Pulse functions
+/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
*
@verbatim
@@ -1282,14 +1298,14 @@
*/
/**
- * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * @brief Starts the TIM One Pulse signal generation on the complementary
* output.
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1 /
- * IM_CHANNEL_2
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1300,7 +1316,7 @@
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
@@ -1314,7 +1330,8 @@
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1 / TIM_CHANNEL_2
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1326,7 +1343,7 @@
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1343,7 +1360,8 @@
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1 / IM_CHANNEL_2
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1360,7 +1378,7 @@
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
@@ -1374,7 +1392,8 @@
* the configuration information for TIM module.
* @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * TIM_CHANNEL_1 / IM_CHANNEL_2
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1391,7 +1410,7 @@
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1400,11 +1419,11 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group5 Peripheral Control functions
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -1435,11 +1454,11 @@
* the configuration information for TIM module.
* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
- * TIM_TS_ITR0 /
- * TIM_TS_ITR1 /
- * TIM_TS_ITR2 /
- * TIM_TS_ITR3 /
- * TIM_TS_NONE
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@@ -1485,11 +1504,11 @@
* the configuration information for TIM module.
* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
- * TIM_TS_ITR0 /
- * TIM_TS_ITR1 /
- * TIM_TS_ITR2 /
- * TIM_TS_ITR3 /
- * TIM_TS_NONE
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@@ -1539,11 +1558,11 @@
* the configuration information for TIM module.
* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
- * TIM_TS_ITR0 /
- * TIM_TS_ITR1 /
- * TIM_TS_ITR2 /
- * TIM_TS_ITR3 /
- * TIM_TS_NONE
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@@ -1574,9 +1593,9 @@
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
@@ -1643,6 +1662,7 @@
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
/* Process Locked */
__HAL_LOCK(htim);
@@ -1670,11 +1690,11 @@
/**
* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module..
- * @param TIM_Remap: specifies the TIM input remapping source.
+ * the configuration information for TIM module.
+ * @param Remap: specifies the TIM input remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
+ * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
* @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
* @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
* @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
@@ -1703,12 +1723,11 @@
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group6 Extension Callbacks functions
+/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
* @brief Extension Callbacks functions
*
@verbatim
@@ -1749,12 +1768,11 @@
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group7 Extension Peripheral State functions
+/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
* @brief Extension Peripheral State functions
*
@verbatim
@@ -1790,7 +1808,7 @@
* the configuration information for the specified DMA module.
* @retval None
*/
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
@@ -1798,7 +1816,10 @@
HAL_TIMEx_CommutationCallback(htim);
}
-
+/**
+ * @}
+ */
+
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-/** @addtogroup STM32F4xx_HAL
+/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup TIMEx_Exported_Types TIM Exported Types
+ * @{
+ */
+
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
@@ -90,31 +93,33 @@
*/
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode.
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode.
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level.
+ uint32_t LockLevel; /*!< TIM Lock level.
This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time.
+ uint32_t DeadTime; /*!< TIM dead Time.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State.
+ uint32_t BreakState; /*!< TIM Break State.
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity.
+ uint32_t BreakPolarity; /*!< TIM Break input polarity.
This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
}TIM_BreakDeadTimeConfigTypeDef;
-
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants
+/** @defgroup TIMEx_Exported_Constants TIM Exported Constants
* @{
*/
-/** @defgroup TIMEx_Remap
+/** @defgroup TIMEx_Remap TIM Remap
* @{
*/
-
#define TIM_TIM2_TIM8_TRGO (0x00000000)
#define TIM_TIM2_ETH_PTP (0x00000400)
#define TIM_TIM2_USBFS_SOF (0x00000800)
@@ -126,29 +131,26 @@
#define TIM_TIM11_GPIO (0x00000000)
#define TIM_TIM11_HSE (0x00000002)
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
- ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
- ((TIM_REMAP) == TIM_TIM5_GPIO)||\
- ((TIM_REMAP) == TIM_TIM5_LSI)||\
- ((TIM_REMAP) == TIM_TIM5_LSE)||\
- ((TIM_REMAP) == TIM_TIM5_RTC)||\
- ((TIM_REMAP) == TIM_TIM11_GPIO)||\
- ((TIM_REMAP) == TIM_TIM11_HSE))
-
+#if defined (STM32F446xx)
+#define TIM_TIM11_SPDIFRX (0x00000001)
+#endif /* STM32F446xx */
+/**
+ * @}
+ */
+
/**
* @}
*/
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions
+ * @{
+ */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-
+/** @addtogroup TIMEx_Exported_Functions_Group1
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
@@ -165,7 +167,13 @@
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group2
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
@@ -178,7 +186,13 @@
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group3
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
@@ -190,7 +204,13 @@
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group4
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
@@ -199,22 +219,94 @@
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
-/* Extnsion Control functions ************************************************/
+/** @addtogroup TIMEx_Exported_Functions_Group5
+ * @{
+ */
+/* Extension Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group6
+ * @{
+ */
/* Extension Callback *********************************************************/
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group7
+ * @{
+ */
/* Extension Peripheral State functions **************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Private Macros
+ * @{
+ */
+#if defined (STM32F446xx)
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+#else
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+#endif /* STM32F446xx */
+
+
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -222,8 +314,8 @@
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_uart.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -63,7 +63,7 @@
[..]
(@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
- low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
HAL_UART_MspInit() API.
[..]
@@ -79,13 +79,9 @@
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
(+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_RxCpltCallback
(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
@@ -121,6 +117,7 @@
(+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
(+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
(+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+ (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
[..]
(@) You can refer to the UART HAL driver header file for more useful macros
@@ -129,7 +126,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -163,7 +160,7 @@
* @{
*/
-/** @defgroup UART
+/** @defgroup UART UART
* @brief HAL UART module driver
* @{
*/
@@ -171,12 +168,22 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup UART_Private_Constants
+ * @{
+ */
#define UART_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
static void UART_SetConfig (UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -184,14 +191,16 @@
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup UART_Private_Functions
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
*/
-/** @defgroup UART_Group1 Initialization and de-initialization functions
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -211,7 +220,7 @@
please refer to Reference manual for possible UART frame formats.
(++) Hardware flow control
(++) Receiver/transmitter modes
- (++) Over Sampling Methode
+ (++) Over Sampling Method
[..]
The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
@@ -235,20 +244,25 @@
{
return HAL_ERROR;
}
-
+
+ /* Check the parameters */
if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
- {
- /* Check the parameters */
+ {
+ /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
}
else
{
- /* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -291,9 +305,16 @@
{
return HAL_ERROR;
}
-
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -343,11 +364,17 @@
{
return HAL_ERROR;
}
- /* Check the Break detection length parameter */
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
+ assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -389,13 +416,13 @@
* @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param Address: USART address
- * @param WakeUpMethode: specifies the USART wakeup method.
+ * @param WakeUpMethod: specifies the USART wake-up method.
* This parameter can be one of the following values:
- * @arg UART_WAKEUPMETHODE_IDLELINE: Wakeup by an idle line detection
- * @arg UART_WAKEUPMETHODE_ADDRESSMARK: Wakeup by an address mark
+ * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode)
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
{
/* Check the UART handle allocation */
if(huart == HAL_NULL)
@@ -403,12 +430,17 @@
return HAL_ERROR;
}
- /* Check the Address & wake up method parameters */
- assert_param(IS_UART_WAKEUPMETHODE(WakeUpMethode));
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
assert_param(IS_UART_ADDRESS(Address));
-
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -432,9 +464,9 @@
/* Set the USART address node */
huart->Instance->CR2 |= Address;
- /* Set the wake up methode by setting the WAKE bit in the CR1 register */
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
huart->Instance->CR1 &= ~(USART_CR1_WAKE);
- huart->Instance->CR1 |= WakeUpMethode;
+ huart->Instance->CR1 |= WakeUpMethod;
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
@@ -507,7 +539,7 @@
* @}
*/
-/** @defgroup UART_Group2 IO operation functions
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
* @brief UART Transmit and Receive functions
*
@verbatim
@@ -528,7 +560,7 @@
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or receive process.
+ will be executed respectively at the end of the transmit or receive process.
The HAL_UART_ErrorCallback() user callback will be executed when
a communication error is detected.
@@ -921,6 +953,9 @@
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
huart->Instance->CR3 |= USART_CR3_DMAT;
@@ -1055,14 +1090,14 @@
}
else if(huart->State == HAL_UART_STATE_BUSY_RX)
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_UART_CLEAR_OREFLAG(huart);
/* Enable the UART DMA Rx request */
huart->Instance->CR3 |= USART_CR3_DMAR;
}
else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_UART_CLEAR_OREFLAG(huart);
/* Enable the UART DMA Tx & Rx request */
huart->Instance->CR3 |= USART_CR3_DMAT;
@@ -1175,6 +1210,14 @@
UART_Transmit_IT(huart);
}
+ tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
+ tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
+ /* UART in mode Transmitter end --------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ }
+
if(huart->ErrorCode != HAL_UART_ERROR_NONE)
{
/* Set the UART state ready to be able to start again the process */
@@ -1253,7 +1296,7 @@
* @}
*/
-/** @defgroup UART_Group3 Peripheral Control functions
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
* @brief UART control functions
*
@verbatim
@@ -1425,7 +1468,7 @@
* @}
*/
-/** @defgroup UART_Group4 Peripheral State and Errors functions
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief UART State and Errors functions
*
@verbatim
@@ -1486,27 +1529,8 @@
in the UART CR3 register */
huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
- /* Wait for UART TC Flag */
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- huart->State = HAL_UART_STATE_TIMEOUT;
- HAL_UART_ErrorCallback(huart);
- }
- else
- {
- /* No Timeout */
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
- HAL_UART_TxCpltCallback(huart);
- }
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
/* DMA Circular mode */
else
@@ -1658,7 +1682,7 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1693,31 +1717,8 @@
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the UART Parity Error Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State = HAL_UART_STATE_READY;
- }
-
- /* Wait on TC flag to be able to start a second transfer */
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- HAL_UART_TxCpltCallback(huart);
-
- return HAL_OK;
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
return HAL_OK;
}
@@ -1727,6 +1728,39 @@
}
}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_TxCpltCallback(huart);
+
+ return HAL_OK;
+}
+
/**
* @brief Receives an amount of data in non blocking mode
* @param huart: pointer to a UART_HandleTypeDef structure that contains
@@ -1809,19 +1843,10 @@
uint32_t tmpreg = 0x00;
/* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
assert_param(IS_UART_PARITY(huart->Init.Parity));
assert_param(IS_UART_MODE(huart->Init.Mode));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-
- /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
- {
- assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
- }
/*-------------------------- USART CR2 Configuration -----------------------*/
tmpreg = huart->Instance->CR2;
@@ -1870,11 +1895,11 @@
/*-------------------------- USART BRR Configuration ---------------------*/
if((huart->Instance == USART1) || (huart->Instance == USART6))
{
- huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
else
{
- huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
}
}
else
@@ -1882,11 +1907,11 @@
/*-------------------------- USART BRR Configuration ---------------------*/
if((huart->Instance == USART1) || (huart->Instance == USART6))
{
- huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
else
{
- huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
}
}
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_uart.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,9 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
/**
* @brief UART Init Structure definition
@@ -80,14 +83,14 @@
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
- uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
- uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
This parameter can be a value of @ref UART_Over_Sampling */
}UART_InitTypeDef;
@@ -107,202 +110,185 @@
}HAL_UART_StateTypeDef;
/**
- * @brief HAL UART Error Code structure definition
- */
-typedef enum
-{
- HAL_UART_ERROR_NONE = 0x00, /*!< No error */
- HAL_UART_ERROR_PE = 0x01, /*!< Parity error */
- HAL_UART_ERROR_NE = 0x02, /*!< Noise error */
- HAL_UART_ERROR_FE = 0x04, /*!< frame error */
- HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_UART_ErrorTypeDef;
-
-/**
* @brief UART handle Structure definition
*/
typedef struct
{
- USART_TypeDef *Instance; /* UART registers base address */
+ USART_TypeDef *Instance; /*!< UART registers base address */
- UART_InitTypeDef Init; /* UART communication parameters */
+ UART_InitTypeDef Init; /*!< UART communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
- uint16_t TxXferSize; /* UART Tx Transfer size */
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
- uint16_t TxXferCount; /* UART Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
- uint16_t RxXferSize; /* UART Rx Transfer size */
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
- uint16_t RxXferCount; /* UART Rx Transfer Counter */
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
- DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_UART_StateTypeDef State; /* UART communication state */
+ __IO HAL_UART_StateTypeDef State; /*!< UART communication state */
- __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */
-
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
}UART_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants
+/** @defgroup UART_Exported_Constants UART Exported constants
* @{
*/
-
-/** @defgroup UART_Word_Length
+
+/** @defgroup UART_Error_Code UART Error Code
+ * @brief UART Error Code
+ * @{
+ */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
- ((LENGTH) == UART_WORDLENGTH_9B))
/**
* @}
*/
-/** @defgroup UART_Stop_Bits
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 ((uint32_t)0x00000000)
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2))
/**
* @}
*/
-/** @defgroup UART_Parity
+/** @defgroup UART_Parity UART Parity
* @{
*/
#define UART_PARITY_NONE ((uint32_t)0x00000000)
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
- ((PARITY) == UART_PARITY_EVEN) || \
- ((PARITY) == UART_PARITY_ODD))
/**
* @}
*/
-/** @defgroup UART_Hardware_Flow_Control
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == UART_HWCONTROL_NONE) || \
- ((CONTROL) == UART_HWCONTROL_RTS) || \
- ((CONTROL) == UART_HWCONTROL_CTS) || \
- ((CONTROL) == UART_HWCONTROL_RTS_CTS))
/**
* @}
*/
-/** @defgroup UART_Mode
+/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
- /** @defgroup UART_State
+ /** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE ((uint32_t)0x00000000)
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
- ((STATE) == UART_STATE_ENABLE))
/**
* @}
*/
-/** @defgroup UART_Over_Sampling
+/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
- ((SAMPLING) == UART_OVERSAMPLING_8))
/**
* @}
*/
-/** @defgroup UART_LIN_Break_Detection_Length
+/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020)
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
/**
* @}
*/
-/** @defgroup UART_WakeUp_functions
+/** @defgroup UART_WakeUp_functions UART Wakeup Functions
* @{
*/
-#define UART_WAKEUPMETHODE_IDLELINE ((uint32_t)0x00000000)
-#define UART_WAKEUPMETHODE_ADDRESSMARK ((uint32_t)0x00000800)
-#define IS_UART_WAKEUPMETHODE(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHODE_IDLELINE) || \
- ((WAKEUP) == UART_WAKEUPMETHODE_ADDRESSMARK))
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800)
/**
* @}
*/
-/** @defgroup UART_Flags
+/** @defgroup UART_Flags UART FLags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-#define UART_FLAG_CTS ((uint32_t)0x00000200)
-#define UART_FLAG_LBD ((uint32_t)0x00000100)
-#define UART_FLAG_TXE ((uint32_t)0x00000080)
-#define UART_FLAG_TC ((uint32_t)0x00000040)
-#define UART_FLAG_RXNE ((uint32_t)0x00000020)
-#define UART_FLAG_IDLE ((uint32_t)0x00000010)
-#define UART_FLAG_ORE ((uint32_t)0x00000008)
-#define UART_FLAG_NE ((uint32_t)0x00000004)
-#define UART_FLAG_FE ((uint32_t)0x00000002)
-#define UART_FLAG_PE ((uint32_t)0x00000001)
+#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
+#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
+#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
+#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
+#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
+#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
-/** @defgroup UART_Interrupt_definition
+/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
* Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
+ * - XXXX : Interrupt mask (16 bits) in the Y register
* - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
+ * - 0001: CR1 register
+ * - 0010: CR2 register
+ * - 0011: CR3 register
*
* @{
- */
-#define UART_IT_PE ((uint32_t)0x10000100)
-#define UART_IT_TXE ((uint32_t)0x10000080)
-#define UART_IT_TC ((uint32_t)0x10000040)
-#define UART_IT_RXNE ((uint32_t)0x10000020)
-#define UART_IT_IDLE ((uint32_t)0x10000010)
+ */
-#define UART_IT_LBD ((uint32_t)0x20000040)
-#define UART_IT_CTS ((uint32_t)0x30000400)
+#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define UART_IT_ERR ((uint32_t)0x30000001)
+#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@@ -312,6 +298,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
/** @brief Reset UART handle state
* @param __HANDLE__: specifies the UART Handle.
@@ -321,7 +310,7 @@
*/
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
-/** @brief Flushs the UART DR register
+/** @brief Flushes the UART DR register
* @param __HANDLE__: specifies the UART Handle.
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
@@ -338,7 +327,7 @@
* @arg UART_FLAG_TC: Transmission Complete flag
* @arg UART_FLAG_RXNE: Receive data register not empty flag
* @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: OverRun Error flag
+ * @arg UART_FLAG_ORE: Overrun Error flag
* @arg UART_FLAG_NE: Noise Error flag
* @arg UART_FLAG_FE: Framing Error flag
* @arg UART_FLAG_PE: Parity Error flag
@@ -358,7 +347,7 @@
* @arg UART_FLAG_TC: Transmission Complete flag.
* @arg UART_FLAG_RXNE: Receive data register not empty flag.
*
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
@@ -377,8 +366,14 @@
* UART peripheral.
* @retval None
*/
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
- (__HANDLE__)->Instance->DR;}while(0)
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
/** @brief Clear the UART FE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
@@ -411,11 +406,11 @@
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Enables or disables the specified UART interrupt.
+/** @brief Enable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __INTERRUPT__: specifies the UART interrupt source to check.
+ * @param __INTERRUPT__: specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
@@ -425,14 +420,28 @@
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified UART interrupt.
- * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
#define UART_IT_MASK ((uint32_t)0x0000FFFF)
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
@@ -531,39 +540,56 @@
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0)
-/** @brief macros to enables or disables the UART's one bit sampling method
+/** @brief macros to enables the UART's one bit sample method
* @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief macros to disables the UART's one bit sample method
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+/** @brief Enable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+/**
+ * @}
+ */
-#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (__DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((__DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
-#define __DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (__DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((__DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+/** @addtogroup UART_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -580,17 +606,104 @@
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+/** @addtogroup UART_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+/** @addtogroup UART_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+/** @brief UART interruptions flag mask
+ *
+ */
+#define UART_CR1_REG_INDEX 1
+#define UART_CR2_REG_INDEX 2
+#define UART_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+ ((PARITY) == UART_PARITY_EVEN) || \
+ ((PARITY) == UART_PARITY_ODD))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+ ((SAMPLING) == UART_OVERSAMPLING_8))
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -598,8 +711,8 @@
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_usart.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@@ -33,7 +33,7 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
@@ -41,11 +41,11 @@
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
(++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_USART_MspInit(&husart) API.
+ by calling the customized HAL_USART_MspInit(&husart) API.
-@@- The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
- __USART_ENABLE_IT() and __USART_DISABLE_IT() inside the transmit and receive process.
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
(#) Three operation modes are available within this driver :
@@ -59,15 +59,11 @@
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
@@ -109,7 +105,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -143,19 +139,30 @@
* @{
*/
-/** @defgroup USART
+/** @defgroup USART USART
* @brief HAL USART Synchronous module driver
* @{
*/
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define DUMMY_DATA 0xFFFF
+/** @addtogroup USART_Private_Constants
+ * @{
+ */
+#define DUMMY_DATA 0xFFFF
#define USART_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
static void USART_SetConfig (USART_HandleTypeDef *husart);
@@ -165,14 +172,16 @@
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-
-/** @defgroup USART_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USART_Exported_Functions USART Exported Functions
* @{
*/
-/** @defgroup USART_Group1 USART Initialization and de-initialization functions
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -223,6 +232,8 @@
if(husart->State == HAL_USART_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_USART_MspInit(husart);
}
@@ -239,7 +250,7 @@
husart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL);
/* Enable the Peripheral */
- __USART_ENABLE(husart);
+ __HAL_USART_ENABLE(husart);
/* Initialize the USART state */
husart->ErrorCode = HAL_USART_ERROR_NONE;
@@ -267,6 +278,9 @@
husart->State = HAL_USART_STATE_BUSY;
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
@@ -288,7 +302,7 @@
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_MspInit could be implenetd in the user file
+ the HAL_USART_MspInit could be implemented in the user file
*/
}
@@ -301,7 +315,7 @@
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_MspDeInit could be implenetd in the user file
+ the HAL_USART_MspDeInit could be implemented in the user file
*/
}
@@ -309,7 +323,7 @@
* @}
*/
-/** @defgroup USART_Group2 IO operation functions
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
* @brief USART Transmit and Receive functions
*
@verbatim
@@ -335,7 +349,7 @@
using DMA mode.
The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
+ will be executed respectively at the end of the transmit or Receive process
The HAL_USART_ErrorCallback() user callback will be executed when a communication
error is detected
@@ -354,13 +368,18 @@
(++) HAL_USART_Transmit_DMA()in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceie_DMA() in full duplex mode
-
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_USART_TxHalfCpltCallback()
(++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
-
+
@endverbatim
* @{
*/
@@ -687,14 +706,14 @@
when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
to benefit for the frame error and noise interrupts the USART mode should be
configured only for transmit "USART_MODE_TX"
- The __USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
+ The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
Noise error interrupt */
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Transmit Data Register Empty Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
@@ -730,17 +749,17 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
/* Enable the USART Data Register not empty Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_ENABLE_IT(husart, USART_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
/* Send dummy byte in order to generate the clock for the slave to send data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
@@ -783,20 +802,20 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
/* Enable the USART Data Register not empty Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_ENABLE_IT(husart, USART_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
/* Enable the USART Transmit Data Register Empty Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
@@ -847,6 +866,9 @@
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAT;
@@ -992,6 +1014,9 @@
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
/* Clear the Overrun flag: mandatory for the second transfer in circular mode */
__HAL_USART_CLEAR_OREFLAG(husart);
@@ -1171,6 +1196,14 @@
USART_TransmitReceive_IT(husart);
}
}
+
+ tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
+ tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
+ /* USART in mode Transmitter (transmission end) ----------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ USART_EndTransmit_IT(husart);
+ }
}
/**
@@ -1255,7 +1288,7 @@
* @}
*/
-/** @defgroup USART_Group3 Peripheral State and Errors functions
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief USART State and Errors functions
*
@verbatim
@@ -1315,22 +1348,12 @@
husart->TxXferCount = 0;
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
- /* Wait for USART TC Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- husart->State = HAL_USART_STATE_TIMEOUT;
- HAL_USART_ErrorCallback(husart);
- }
- else
- {
- /* No Timeout */
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the USART CR3 register */
- husart->Instance->CR3 &= ~(USART_CR3_DMAT);
- husart->State= HAL_USART_STATE_READY;
- HAL_USART_TxCpltCallback(husart);
- }
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
}
/* DMA Circular mode */
@@ -1368,23 +1391,24 @@
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
husart->RxXferCount = 0;
- husart->State= HAL_USART_STATE_READY;
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
/* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
in the USART CR3 register */
husart->Instance->CR3 &= ~(USART_CR3_DMAR);
+ husart->State= HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
}
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
/* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
in the USART CR3 register */
husart->Instance->CR3 &= ~(USART_CR3_DMAR);
husart->Instance->CR3 &= ~(USART_CR3_DMAT);
-
+
+ husart->State= HAL_USART_STATE_READY;
HAL_USART_TxRxCpltCallback(husart);
}
}
@@ -1395,7 +1419,7 @@
{
HAL_USART_RxCpltCallback(husart);
}
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
HAL_USART_TxRxCpltCallback(husart);
@@ -1460,10 +1484,10 @@
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __USART_DISABLE_IT(husart, USART_IT_TXE);
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
- __USART_DISABLE_IT(husart, USART_IT_PE);
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State= HAL_USART_STATE_READY;
@@ -1485,10 +1509,10 @@
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __USART_DISABLE_IT(husart, USART_IT_TXE);
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
- __USART_DISABLE_IT(husart, USART_IT_PE);
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State= HAL_USART_STATE_READY;
@@ -1538,21 +1562,10 @@
if(--husart->TxXferCount == 0)
{
/* Disable the USART Transmit data register empty Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_TXE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_DISABLE_IT(husart, USART_IT_ERR);
-
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxCpltCallback(husart);
-
- return HAL_OK;
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
return HAL_OK;
}
@@ -1563,6 +1576,27 @@
}
/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxCpltCallback(husart);
+
+ return HAL_OK;
+}
+
+/**
* @brief Simplex Receive an amount of data in non-blocking mode.
* @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
@@ -1613,13 +1647,13 @@
if(husart->RxXferCount == 0)
{
/* Disable the USART RXNE Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
/* Disable the USART Parity Error Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State = HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
@@ -1672,7 +1706,7 @@
/* Check the latest data transmitted */
if(husart->TxXferCount == 0)
{
- __USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
}
}
}
@@ -1713,13 +1747,13 @@
/* Check the latest data received */
if(husart->RxXferCount == 0)
{
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
/* Disable the USART Parity Error Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State = HAL_USART_STATE_READY;
@@ -1770,7 +1804,7 @@
/* Set CPHA bit according to husart->Init.CLKPhase value */
/* Set LBCL bit according to husart->Init.CLKLastBit value */
/* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
- tmpreg |= (uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity |
+ tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity |
husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
/* Write to USART CR2 */
husart->Instance->CR2 = (uint32_t)tmpreg;
@@ -1778,15 +1812,16 @@
/*-------------------------- USART CR1 Configuration -----------------------*/
tmpreg = husart->Instance->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits */
tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE));
+ USART_CR1_RE | USART_CR1_OVER8));
/* Configure the USART Word Length, Parity and mode:
Set the M bits according to husart->Init.WordLength value
Set PCE and PS bits according to husart->Init.Parity value
- Set TE and RE bits according to husart->Init.Mode value */
- tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode;
+ Set TE and RE bits according to husart->Init.Mode value
+ Force OVER8 bit to 1 in order to reach the max USART frequencies */
+ tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
/* Write to USART CR1 */
husart->Instance->CR1 = (uint32_t)tmpreg;
@@ -1798,11 +1833,11 @@
/*-------------------------- USART BRR Configuration -----------------------*/
if((husart->Instance == USART1) || (husart->Instance == USART6))
{
- husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
}
else
{
- husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
}
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_usart.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
/**
* @brief USART Init Structure definition
*/
@@ -78,7 +82,7 @@
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
@@ -108,19 +112,6 @@
}HAL_USART_StateTypeDef;
/**
- * @brief HAL USART Error Code structure definition
- */
-typedef enum
-{
- HAL_USART_ERROR_NONE = 0x00, /*!< No error */
- HAL_USART_ERROR_PE = 0x01, /*!< Parity error */
- HAL_USART_ERROR_NE = 0x02, /*!< Noise error */
- HAL_USART_ERROR_FE = 0x04, /*!< frame error */
- HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_USART_ErrorTypeDef;
-
-/**
* @brief USART handle Structure definition
*/
typedef struct
@@ -149,125 +140,122 @@
__IO HAL_USART_StateTypeDef State; /* Usart communication state */
- __IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */
-
+ __IO uint32_t ErrorCode; /* USART Error code */
+
}USART_HandleTypeDef;
-
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants
+/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
-/** @defgroup USART_Word_Length
+/** @defgroup USART_Error_Code USART Error Code
+ * @brief USART Error Code
+ * @{
+ */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Word_Length USART Word Length
* @{
*/
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
/**
* @}
*/
-/** @defgroup USART_Stop_Bits
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_1 ((uint32_t)0x00000000)
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
- ((STOPBITS) == USART_STOPBITS_1_5) || \
- ((STOPBITS) == USART_STOPBITS_2))
/**
* @}
*/
-/** @defgroup USART_Parity
+/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE ((uint32_t)0x00000000)
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
- ((PARITY) == USART_PARITY_EVEN) || \
- ((PARITY) == USART_PARITY_ODD))
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
-/** @defgroup USART_Mode
+/** @defgroup USART_Mode USART Mode
* @{
*/
#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
/**
* @}
*/
-/** @defgroup USART_Clock
+/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLED ((uint32_t)0x00000000)
-#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
- ((CLOCK) == USART_CLOCK_ENABLED))
+#define USART_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
*/
-/** @defgroup USART_Clock_Polarity
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW ((uint32_t)0x00000000)
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup USART_Clock_Phase
+/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
/**
* @}
*/
-/** @defgroup USART_Last_Bit
+/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
- ((LASTBIT) == USART_LASTBIT_ENABLE))
/**
* @}
*/
-/** @defgroup USART_NACK_State
+/** @defgroup USART_NACK_State USART NACK State
* @{
*/
-#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK)
-#define USARTNACK_DISABLED ((uint32_t)0x00000000)
-#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \
- ((NACK) == USARTNACK_DISABLED))
+#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
-/** @defgroup USART_Flags
+/** @defgroup USART_Flags USART Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-
#define USART_FLAG_TXE ((uint32_t)0x00000080)
#define USART_FLAG_TC ((uint32_t)0x00000040)
#define USART_FLAG_RXNE ((uint32_t)0x00000020)
@@ -280,7 +268,7 @@
* @}
*/
-/** @defgroup USART_Interrupt_definition
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
@@ -290,18 +278,16 @@
*
* @{
*/
-#define USART_IT_PE ((uint32_t)0x10000100)
-#define USART_IT_TXE ((uint32_t)0x10000080)
-#define USART_IT_TC ((uint32_t)0x10000040)
-#define USART_IT_RXNE ((uint32_t)0x10000020)
-#define USART_IT_IDLE ((uint32_t)0x10000010)
+#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define USART_IT_LBD ((uint32_t)0x20000040)
-#define USART_IT_CTS ((uint32_t)0x30000400)
+#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
-#define USART_IT_ERR ((uint32_t)0x30000001)
-
-
+#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@@ -309,8 +295,12 @@
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
/** @brief Reset USART handle state
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
@@ -327,13 +317,12 @@
* @arg USART_FLAG_TC: Transmission Complete flag
* @arg USART_FLAG_RXNE: Receive data register not empty flag
* @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_ORE: Overrun Error flag
* @arg USART_FLAG_NE: Noise Error flag
* @arg USART_FLAG_FE: Framing Error flag
* @arg USART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified Smartcard pending flags.
@@ -344,7 +333,7 @@
* @arg USART_FLAG_TC: Transmission Complete flag.
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
*
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
@@ -362,8 +351,14 @@
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
- (__HANDLE__)->Instance->DR;}while(0)
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
@@ -392,7 +387,7 @@
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Enables or disables the specified Usart interrupts.
+/** @brief Enables or disables the specified USART interrupts.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __INTERRUPT__: specifies the USART interrupt source to check.
@@ -403,20 +398,17 @@
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified Usart interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
-#define USART_IT_MASK ((uint32_t)0x0000FFFF)
-#define __USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-/** @brief Checks whether the specified Usart interrupt has occurred or not.
+/** @brief Checks whether the specified USART interrupt has occurred or not.
* @param __HANDLE__: specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __IT__: specifies the USART interrupt source to check.
@@ -432,22 +424,55 @@
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
-#define __USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define __USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __USART_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+/** @brief Macro to enable the USART's one bit sample method
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Macro to disable the USART's one bit sample method
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
-
+/** @brief Disable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
@@ -468,10 +493,83 @@
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
-/* Peripheral State functions **************************************************/
+/** @addtogroup USART_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+/** @brief USART interruptions flag mask
+ *
+ */
+#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+
+#define USART_CR1_REG_INDEX 1
+#define USART_CR2_REG_INDEX 2
+#define USART_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
+ ((NACK) == USART_NACK_DISABLE))
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
+ ((CLOCK) == USART_CLOCK_ENABLE))
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+
+#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
+#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100)
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@@ -40,7 +40,7 @@
##### How to use this driver #####
==============================================================================
[..]
- (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
(+) Start the WWDG using HAL_WWDG_Start() function.
@@ -64,13 +64,13 @@
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
- (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt
+ (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wake-up interrupt
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -104,7 +104,7 @@
* @{
*/
-/** @defgroup WWDG
+/** @defgroup WWDG WWDG
* @brief WWDG HAL module driver.
* @{
*/
@@ -116,13 +116,12 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
* @{
*/
-/** @defgroup WWDG_Group1 Initialization and de-initialization functions
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@@ -164,6 +163,8 @@
if(hwwdg->State == HAL_WWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hwwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
}
@@ -255,7 +256,7 @@
* @}
*/
-/** @defgroup WWDG_Group2 IO operation functions
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -314,7 +315,7 @@
hwwdg->State = HAL_WWDG_STATE_BUSY;
/* Enable the Early Wakeup Interrupt */
- __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
+ __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
/* Enable the peripheral */
__HAL_WWDG_ENABLE(hwwdg);
@@ -369,20 +370,24 @@
*/
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
- /* WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ /* Check if Early Wakeup Interrupt is enable */
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
- /* Early Wakeup callback */
- HAL_WWDG_WakeupCallback(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_READY;
-
- /* Clear the WWDG Data Ready flag */
- __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hwwdg);
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Early Wakeup callback */
+ HAL_WWDG_WakeupCallback(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+ }
}
}
@@ -403,7 +408,7 @@
* @}
*/
-/** @defgroup WWDG_Group3 Peripheral State functions
+/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+ * @{
+ */
+
/**
* @brief WWDG HAL State Structure definition
*/
@@ -98,89 +101,51 @@
__IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
}WWDG_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_BitAddress_AliasRegion
- * @brief WWDG registers bit address in the alias region
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
-/* --- CFR Register ---*/
-/* Alias word address of EWI bit */
-#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Interrupt_definition
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
-#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI)
-
-#define IS_WWDG_IT(__IT__) ((__IT__) == WWDG_IT_EWI)
-
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
-/** @defgroup WWDG_Flag_definition
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
*/
-#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */
-#define IS_WWDG_FLAG(__FLAG__) ((__FLAG__) == WWDG_FLAG_EWIF))
-
-
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
-/** @defgroup WWDG_Prescaler
+/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8))
-
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
-/** @defgroup WWDG_Window
- * @{
- */
-#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Counter
- * @{
- */
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
-
-/**
- * @}
- */
-
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+ * @{
+ */
/** @brief Reset WWDG handle state
* @param __HANDLE__: WWDG handle
@@ -196,6 +161,57 @@
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
+ * @brief Disables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enable, WWDG Peripheral cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
+
+/**
+ * @brief Gets the selected WWDG's it status.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief Clear the WWDG's interrupt pending bits
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+ * @brief Enables the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+ * @brief Disables the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
+
+/**
* @brief Gets the selected WWDG's flag status.
* @param __HANDLE__: WWDG handle
* @param __FLAG__: specifies the flag to check.
@@ -215,41 +231,107 @@
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-/**
- * @brief Enables the WWDG early wakeup interrupt.
- * @param __INTERRUPT__: specifies the interrupt to enable.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early wakeup interrupt
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
+/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
+ * @param __HANDLE__: WWDG Handle.
+ * @param __INTERRUPT__: specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
-/** @brief Clear the WWDG's interrupt pending bits
- * bits to clear the selected interrupt pending bits.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+/**
+ * @}
*/
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+/** @addtogroup WWDG_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+ * @}
+ */
+/** @addtogroup WWDG_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+/** @addtogroup WWDG_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup WWDG_Private_Constants WWDG Private Constants
+ * @{
+ */
+/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress
+ * @brief WWDG registers bit address in the alias region
+ * @{
+ */
+
+/* --- CFR Register ---*/
+/* Alias word address of EWI bit */
+#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+ * @{
+ */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup WWDG_Private_Functions WWDG Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -257,8 +339,7 @@
/**
* @}
- */
-
+ */
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -46,7 +46,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -80,14 +80,14 @@
* @{
*/
-/** @defgroup FMC
+/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
* @{
*/
#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -95,13 +95,12 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FMC_Private_Functions
+/** @addtogroup FMC_LL_Private_Functions
* @{
*/
-/** @defgroup FMC_NORSRAM Controller functions
- * @brief NORSRAM Controller functions
+/** @addtogroup FMC_LL_NORSRAM
+ * @brief NORSRAM Controller functions
*
@verbatim
==============================================================================
@@ -125,7 +124,7 @@
* @{
*/
-/** @defgroup HAL_FMC_NORSRAM_Group1 Initialization/de-initialization functions
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -161,17 +160,35 @@
assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+#if !defined (STM32F446xx)
assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
+#endif /* !defined (STM32F446xx) */
assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
- assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+#if defined (STM32F446xx)
+ assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
+ assert_param(IS_FMC_PAGESIZE(Init->PageSize));
+#endif /* defined (STM32F446xx) */
+
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Init->NSBank];
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
+ FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN));
/* Set NORSRAM device control parameters */
- tmpr = (uint32_t)(Init->DataAddressMux |\
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
Init->MemoryType |\
Init->MemoryDataWidth |\
Init->BurstAccessMode |\
@@ -183,8 +200,33 @@
Init->ExtendedMode |\
Init->AsynchronousWait |\
Init->WriteBurst |\
- Init->ContinuousClock
- );
+ Init->ContinuousClock);
+#else /* defined(STM32F446xx) */
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
+ FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \
+ FMC_BCR1_WFDIS));
+
+ /* Set NORSRAM device control parameters */
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst |\
+ Init->ContinuousClock |\
+ Init->PageSize |\
+ Init->WriteFifo);
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
{
@@ -198,13 +240,19 @@
{
Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
- Init->ContinuousClock);
- }
+ Init->ContinuousClock);
+ }
+
+#if defined(STM32F446xx)
+ if(Init->NSBank != FMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
+ }
+#endif /* defined(STM32F446xx) */
return HAL_OK;
}
-
/**
* @brief DeInitialize the FMC_NORSRAM peripheral
* @param Device: Pointer to NORSRAM device instance
@@ -226,12 +274,12 @@
/* FMC_NORSRAM_BANK1 */
if(Bank == FMC_NORSRAM_BANK1)
{
- Device->BTCR[Bank] = 0x000030DB;
+ Device->BTCR[Bank] = 0x000030DB;
}
/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
else
{
- Device->BTCR[Bank] = 0x000030D2;
+ Device->BTCR[Bank] = 0x000030D2;
}
Device->BTCR[Bank + 1] = 0x0FFFFFFF;
@@ -240,7 +288,6 @@
return HAL_OK;
}
-
/**
* @brief Initialize the FMC_NORSRAM Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
@@ -264,15 +311,22 @@
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Bank + 1];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
+ FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
+ FMC_BTR1_ACCMOD));
+
/* Set FMC_NORSRAM device timing parameters */
- tmpr = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode)
- );
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (((Timing->CLKDivision)-1) << 20) |\
+ (((Timing->DataLatency)-2) << 24) |\
+ (Timing->AccessMode));
Device->BTCR[Bank + 1] = tmpr;
@@ -297,46 +351,69 @@
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+#if !defined(STM32F446xx)
assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+#endif /* !defined(STM32F446xx) */
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
- Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode));
+ /* Get the BWTR register value */
+ tmpr = Device->BWTR[Bank];
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_CLKDIV | FMC_BWTR1_DATLAT | \
+ FMC_BWTR1_ACCMOD));
+
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (((Timing->CLKDivision)-1) << 20) |\
+ (((Timing->DataLatency)-2) << 24) |\
+ (Timing->AccessMode));
+#else /* defined(STM32F446xx) */
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
+
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (Timing->AccessMode));
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
+ Device->BWTR[Bank] = tmpr;
}
- else
+ else
{
Device->BWTR[Bank] = 0x0FFFFFFF;
}
return HAL_OK;
}
-
-
/**
* @}
*/
-
-/** @defgroup HAL_FMC_NORSRAM_Group3 Control functions
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
* @brief management functions
*
@verbatim
@@ -350,7 +427,6 @@
@endverbatim
* @{
*/
-
/**
* @brief Enables dynamically FMC_NORSRAM write operation.
* @param Device: Pointer to NORSRAM device instance
@@ -394,9 +470,9 @@
/**
* @}
*/
-
-/** @defgroup FMC_PCCARD Controller functions
- * @brief PCCARD Controller functions
+
+/** @addtogroup FMC_LL_NAND
+ * @brief NAND Controller functions
*
@verbatim
==============================================================================
@@ -419,7 +495,8 @@
@endverbatim
* @{
*/
-
+
+#if defined(STM32F446xx)
/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@@ -436,7 +513,7 @@
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the FMC_NAND device according to the specified
* control parameters in the FMC_NAND_HandleTypeDef
@@ -446,7 +523,274 @@
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
{
- uint32_t tmppcr = 0;
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Get the NAND bank register value */
+ tmpr = Device->PCR;
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
+ FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
+ FMC_PCR_TAR | FMC_PCR_ECCPS));
+
+ /* Set NAND device control parameters */
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9) |\
+ ((Init->TARSetupTime) << 13));
+
+ /* NAND bank registers configuration */
+ Device->PCR = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Timing: Pointer to NAND timing structure
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM;
+
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \
+ FMC_PMEM_MEMHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24)
+ );
+
+ /* NAND bank registers configuration */
+ Device->PMEM = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Timing: Pointer to NAND timing structure
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get the NAND bank register value */
+ tmpr = Device->PATT;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \
+ FMC_PATT_ATTHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+
+ /* NAND bank registers configuration */
+ Device->PATT = tmpr;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the FMC_NAND device
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable the NAND Bank */
+ __FMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ /* Set the FMC_NAND_BANK registers to their reset values */
+ Device->PCR = 0x00000018;
+ Device->SR = 0x00000040;
+ Device->PMEM = 0xFCFCFCFC;
+ Device->PATT = 0xFCFCFCFC;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_FMC_NAND_Group2 Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Enable ECC feature */
+ Device->PCR |= FMC_PCR_ECCEN;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable ECC feature */
+ Device->PCR &= ~FMC_PCR_ECCEN;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param ECCval: Pointer to ECC value
+ * @param Bank: NAND bank number
+ * @param Timeout: Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Get the ECCR register value */
+ *ECCval = (uint32_t)Device->ECCR;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the FMC_NAND device according to the specified
+ * control parameters in the FMC_NAND_HandleTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Init: Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -458,25 +802,40 @@
assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+ if(Init->NandBank == FMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PCR2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PCR3;
+ }
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \
+ FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
+ FMC_PCR2_TAR | FMC_PCR2_ECCPS));
+
/* Set NAND device control parameters */
- tmppcr = (uint32_t)(Init->Waitfeature |\
- FMC_PCR_MEMORY_TYPE_NAND |\
- Init->MemoryDataWidth |\
- Init->EccComputation |\
- Init->ECCPageSize |\
- ((Init->TCLRSetupTime) << 9) |\
- ((Init->TARSetupTime) << 13)
- );
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9) |\
+ ((Init->TARSetupTime) << 13));
if(Init->NandBank == FMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PCR2 = tmppcr;
+ Device->PCR2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PCR3 = tmppcr;
+ Device->PCR3 = tmpr;
}
return HAL_OK;
@@ -493,7 +852,7 @@
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
- uint32_t tmppmem = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -503,8 +862,23 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PMEM3;
+ }
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \
+ FMC_PMEM2_MEMHIZ2));
+
/* Set FMC_NAND device timing parameters */
- tmppmem = (uint32_t)(Timing->SetupTime |\
+ tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
@@ -513,12 +887,12 @@
if(Bank == FMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PMEM2 = tmppmem;
+ Device->PMEM2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PMEM3 = tmppmem;
+ Device->PMEM3 = tmpr;
}
return HAL_OK;
@@ -534,7 +908,7 @@
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
- uint32_t tmppatt = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -544,28 +918,41 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PATT2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PATT3;
+ }
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \
+ FMC_PATT2_ATTHIZ2));
+
/* Set FMC_NAND device timing parameters */
- tmppatt = (uint32_t)(Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- ((Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
if(Bank == FMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PATT2 = tmppatt;
+ Device->PATT2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PATT3 = tmppatt;
+ Device->PATT3 = tmpr;
}
return HAL_OK;
}
-
/**
* @brief DeInitializes the FMC_NAND device
* @param Device: Pointer to NAND device instance
@@ -606,11 +993,10 @@
/**
* @}
*/
-
-
-/** @defgroup HAL_FMC_NAND_Group3 Control functions
- * @brief management functions
- *
+
+/** @addtogroup FMC_LL_NAND_Private_Functions_Group2
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FMC_NAND Control functions #####
@@ -622,8 +1008,6 @@
@endverbatim
* @{
*/
-
-
/**
* @brief Enables dynamically FMC_NAND ECC feature.
* @param Device: Pointer to NAND device instance
@@ -649,7 +1033,6 @@
return HAL_OK;
}
-
/**
* @brief Disables dynamically FMC_NAND ECC feature.
* @param Device: Pointer to NAND device instance
@@ -694,8 +1077,8 @@
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait untill FIFO is empty */
- while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
+ /* Wait until FIFO is empty */
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -724,12 +1107,14 @@
/**
* @}
*/
-
+
+#endif /* defined(STM32F446xx) */
/**
* @}
*/
-
-/** @defgroup FMC_PCCARD Controller functions
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @addtogroup FMC_LL_PCCARD
* @brief PCCARD Controller functions
*
@verbatim
@@ -748,15 +1133,13 @@
FMC_PCCARD_AttributeSpace_Timing_Init()
(+) FMC PCCARD bank IO space timing configuration using the function
FMC_PCCARD_IOSpace_Timing_Init()
-
-
@endverbatim
* @{
*/
-/** @defgroup HAL_FMC_PCCARD_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
+/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -780,20 +1163,30 @@
*/
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+ /* Get PCCARD control register value */
+ tmpr = Device->PCR4;
+
+ /* Clear TAR, TCLR, PWAITEN and PWID bits */
+ tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
+ FMC_PCR4_PWID));
+
/* Set FMC_PCCARD device control parameters */
- Device->PCR4 = (uint32_t)(Init->Waitfeature |\
- FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
- (Init->TCLRSetupTime << 9) |\
- (Init->TARSetupTime << 13));
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
+ (Init->TCLRSetupTime << 9) |\
+ (Init->TARSetupTime << 13));
+
+ Device->PCR4 = tmpr;
return HAL_OK;
-
}
/**
@@ -805,6 +1198,8 @@
*/
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
@@ -812,13 +1207,20 @@
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get PCCARD common space timing register value */
+ tmpr = Device->PMEM4;
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \
+ FMC_PMEM4_MEMHIZ4));
/* Set PCCARD timing parameters */
- Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+ Device->PMEM4 = tmpr;
+
return HAL_OK;
}
@@ -831,6 +1233,8 @@
*/
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
@@ -838,13 +1242,20 @@
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get PCCARD timing parameters */
+ tmpr = Device->PATT4;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \
+ FMC_PATT4_ATTHIZ4));
+
/* Set PCCARD timing parameters */
- Device->PATT4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+ Device->PATT4 = tmpr;
+
return HAL_OK;
}
@@ -857,6 +1268,8 @@
*/
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
@@ -864,13 +1277,21 @@
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get FMC_PCCARD device timing parameters */
+ tmpr = Device->PIO4;
+
+ /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
+ tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \
+ FMC_PIO4_IOHIZ4));
+
/* Set FMC_PCCARD device timing parameters */
- Device->PIO4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+ Device->PIO4 = tmpr;
+
return HAL_OK;
}
@@ -900,9 +1321,10 @@
/**
* @}
*/
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-/** @defgroup FMC_SDRAM Controller functions
+/** @addtogroup FMC_LL_SDRAM
* @brief SDRAM Controller functions
*
@verbatim
@@ -924,9 +1346,9 @@
* @{
*/
-/** @defgroup HAL_FMC_SDRAM_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
+/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -968,8 +1390,16 @@
/* Set SDRAM bank configuration parameters */
if (Init->SDBank != FMC_SDRAM_BANK2)
- {
- Device->SDCR[FMC_SDRAM_BANK1] = (uint32_t)(Init->ColumnBitsNumber |\
+ {
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+
+ tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
Init->RowBitsNumber |\
Init->MemoryDataWidth |\
Init->InternalBankNumber |\
@@ -978,23 +1408,36 @@
Init->SDClockPeriod |\
Init->ReadBurst |\
Init->ReadPipeDelay
- );
+ );
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
}
else /* FMC_Bank2_SDRAM */
{
- tmpr1 = (uint32_t)(Init->SDClockPeriod |\
- Init->ReadBurst |\
- Init->ReadPipeDelay
- );
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+ tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
+ Init->ReadBurst |\
+ Init->ReadPipeDelay);
+
+ tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
- tmpr2 = (uint32_t)(Init->ColumnBitsNumber |\
+ tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
Init->RowBitsNumber |\
Init->MemoryDataWidth |\
Init->InternalBankNumber |\
Init->CASLatency |\
- Init->WriteProtection
- );
-
+ Init->WriteProtection);
+
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
}
@@ -1028,29 +1471,46 @@
/* Set SDRAM device timing parameters */
if (Bank != FMC_SDRAM_BANK2)
- {
- Device->SDTR[FMC_SDRAM_BANK1] = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
- (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
- (((Timing->SelfRefreshTime)-1) << 8) |\
- (((Timing->RowCycleDelay)-1) << 12) |\
- (((Timing->WriteRecoveryTime)-1) <<16) |\
- (((Timing->RPDelay)-1) << 20) |\
- (((Timing->RCDDelay)-1) << 24)
- );
+ {
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
+ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
+ (((Timing->SelfRefreshTime)-1) << 8) |\
+ (((Timing->RowCycleDelay)-1) << 12) |\
+ (((Timing->WriteRecoveryTime)-1) <<16) |\
+ (((Timing->RPDelay)-1) << 20) |\
+ (((Timing->RCDDelay)-1) << 24));
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
}
else /* FMC_Bank2_SDRAM */
{
-
- tmpr1 = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
(((Timing->SelfRefreshTime)-1) << 8) |\
(((Timing->WriteRecoveryTime)-1) <<16) |\
- (((Timing->RCDDelay)-1) << 24)
- );
-
- tmpr2 = (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
- (((Timing->RPDelay)-1) << 20)
- );
+ (((Timing->RCDDelay)-1) << 24));
+
+ tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+ tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
+ (((Timing->RPDelay)-1) << 20));
Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
@@ -1083,11 +1543,10 @@
/**
* @}
*/
-
-/** @defgroup HAL_FMC_SDRAM_Group3 Control functions
- * @brief management functions
- *
+/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FMC_SDRAM Control functions #####
@@ -1099,7 +1558,6 @@
@endverbatim
* @{
*/
-
/**
* @brief Enables dynamically FMC_SDRAM write protection.
* @param Device: Pointer to SDRAM device instance
@@ -1260,9 +1718,11 @@
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#endif /* HAL_FMC_MODULE_ENABLED */
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,34 +43,24 @@
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-
-/** @addtogroup FMC
+
+/** @addtogroup FMC_LL
* @{
*/
-
-/* Exported typedef ----------------------------------------------------------*/
-#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
-#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
-#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
-#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
-#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
-
-#define FMC_NORSRAM_DEVICE FMC_Bank1
-#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
-#define FMC_NAND_DEVICE FMC_Bank2_3
-#define FMC_PCCARD_DEVICE FMC_Bank4
-#define FMC_SDRAM_DEVICE FMC_Bank5_6
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Types FMC Private Types
+ * @{
+ */
/**
- * @brief FMC_NORSRAM Configuration Structure definition
+ * @brief FMC NORSRAM Configuration Structure definition
*/
typedef struct
{
@@ -98,7 +88,8 @@
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FMC_Wrap_Mode */
+ This parameter can be a value of @ref FMC_Wrap_Mode
+ This mode is not available for the STM32F446xx devices */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
@@ -127,10 +118,20 @@
through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
+ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO
+ This mode is available only for the STM32F446xx devices */
+
+ uint32_t PageSize; /*!< Specifies the memory page size.
+ This parameter can be a value of @ref FMC_Page_Size
+ This mode is available only for the STM32F446xx devices */
+
}FMC_NORSRAM_InitTypeDef;
/**
- * @brief FMC_NORSRAM Timing parameters structure definition
+ * @brief FMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
@@ -173,7 +174,7 @@
}FMC_NORSRAM_TimingTypeDef;
/**
- * @brief FMC_NAND Configuration Structure definition
+ * @brief FMC NAND Configuration Structure definition
*/
typedef struct
{
@@ -202,7 +203,7 @@
}FMC_NAND_InitTypeDef;
/**
- * @brief FMC_NAND_PCCARD Timing parameters structure definition
+ * @brief FMC NAND/PCCARD Timing parameters structure definition
*/
typedef struct
{
@@ -233,7 +234,7 @@
}FMC_NAND_PCC_TimingTypeDef;
/**
- * @brief FMC_NAND Configuration Structure definition
+ * @brief FMC NAND Configuration Structure definition
*/
typedef struct
{
@@ -250,7 +251,7 @@
}FMC_PCCARD_InitTypeDef;
/**
- * @brief FMC_SDRAM Configuration Structure definition
+ * @brief FMC SDRAM Configuration Structure definition
*/
typedef struct
{
@@ -288,7 +289,7 @@
}FMC_SDRAM_InitTypeDef;
/**
- * @brief FMC_SDRAM Timing parameters structure definition
+ * @brief FMC SDRAM Timing parameters structure definition
*/
typedef struct
{
@@ -322,7 +323,7 @@
}FMC_SDRAM_TimingTypeDef;
/**
- * @brief SDRAM command parameters structure definition
+ * @brief SDRAM command parameters structure definition
*/
typedef struct
{
@@ -337,70 +338,59 @@
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
}FMC_SDRAM_CommandTypeDef;
+/**
+ * @}
+ */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FMC_NOR_SRAM_Controller
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Constants FMC Private Constants
* @{
*/
-/** @defgroup FMC_NORSRAM_Bank
+/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
+ * @{
+ */
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
-
-#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
- ((BANK) == FMC_NORSRAM_BANK2) || \
- ((BANK) == FMC_NORSRAM_BANK3) || \
- ((BANK) == FMC_NORSRAM_BANK4))
/**
* @}
*/
-/** @defgroup FMC_Data_Address_Bus_Multiplexing
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
-
-#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_Memory_Type
+/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
-
-#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
- ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
- ((MEMORY) == FMC_MEMORY_TYPE_NOR))
/**
* @}
*/
-/** @defgroup FMC_NORSRAM_Data_Width
+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
-
-#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
/**
* @}
*/
-/** @defgroup FMC_NORSRAM_Flash_Access
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
@@ -409,224 +399,157 @@
* @}
*/
-/** @defgroup FMC_Burst_Access_Mode
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
-
-#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
- ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
/**
* @}
*/
-
-/** @defgroup FMC_Wait_Signal_Polarity
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
-
-#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wrap_Mode
- * @{
- */
-#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
-
-#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
- ((MODE) == FMC_WRAP_MODE_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_Wait_Timing
+/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
* @{
*/
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
-
-#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
- ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
+/** @note This mode is not available for the STM32F446xx devices
+ */
+#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
/**
* @}
*/
-/** @defgroup FMC_Write_Operation
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+ * @{
+ */
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
-
-#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
- ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_Wait_Signal
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
-
-#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
- ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FMC_Extended_Mode
- * @{
- */
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
-
-#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
- ((MODE) == FMC_EXTENDED_MODE_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_AsynchronousWait
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+ * @{
+ */
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
-
-#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_Write_Burst
+/** @defgroup FMC_Page_Size FMC Page Size
+ * @note These values are available only for the STM32F446xx devices.
+ * @{
+ */
+#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
+#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
+#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_FIFO FMC Write FIFO
+ * @note These values are available only for the STM32F446xx devices.
+ * @{
+ */
+#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
-
-#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
- ((BURST) == FMC_WRITE_BURST_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FMC_Continous_Clock
- * @{
- */
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
-
-#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
/**
* @}
*/
-/** @defgroup FMC_Address_Setup_Time
+/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
-#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Hold_Time
- * @{
- */
-#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Setup_Time
- * @{
- */
-#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
/**
* @}
*/
-
-/** @defgroup FMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_CLK_Division
- * @{
- */
-#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Latency
- * @{
- */
-#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
-/**
- * @}
- */
-
-/** @defgroup FMC_Access_Mode
+
+/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
-
-#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
- ((MODE) == FMC_ACCESS_MODE_B) || \
- ((MODE) == FMC_ACCESS_MODE_C) || \
- ((MODE) == FMC_ACCESS_MODE_D))
/**
* @}
*/
/**
* @}
- */
+ */
-/** @defgroup FMC_NAND_Controller
+/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
* @{
*/
-
-/** @defgroup FMC_NAND_Bank
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
- */
+ */
#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
-
-#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
- ((BANK) == FMC_NAND_BANK3))
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
/**
* @}
*/
-/** @defgroup FMC_Wait_feature
+/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
-
-#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_PCR_Memory_Type
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
@@ -635,31 +558,25 @@
* @}
*/
-/** @defgroup FMC_NAND_Data_Width
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-
-#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
/**
* @}
*/
-/** @defgroup FMC_ECC
+/** @defgroup FMC_ECC FMC ECC
* @{
*/
#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
-
-#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
- ((STATE) == FMC_NAND_ECC_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_ECC_Page_Size
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
@@ -668,265 +585,116 @@
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
-
-#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
/**
* @}
*/
-
-/** @defgroup FMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
+
/**
* @}
- */
+ */
-/** @defgroup FMC_TAR_Setup_Time
+/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
* @{
*/
-#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Setup_Time
+/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
* @{
*/
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
/**
* @}
*/
-/** @defgroup FMC_Wait_Setup_Time
- * @{
- */
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Hold_Setup_Time
- * @{
- */
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Controller
- * @{
- */
-
-/** @defgroup FMC_SDRAM_Bank
- * @{
- */
-#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
-#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
-
-#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
- ((BANK) == FMC_SDRAM_BANK2))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Column_Bits_number
+/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
* @{
*/
#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
-
-#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
- ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
- ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
- ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Row_Bits_number
+/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
* @{
*/
#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
-
-#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
- ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
- ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Memory_Bus_Width
+/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
* @{
*/
#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
-
-#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
- ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Internal_Banks_Number
+/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
* @{
*/
#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
-
-#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
- ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_CAS_Latency
+/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
* @{
*/
#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
-
-#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
- ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
- ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Write_Protection
+/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
* @{
*/
#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
-#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
- ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Clock_Period
+/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
* @{
*/
#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
-
-#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
- ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
- ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Read_Burst
+/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
* @{
*/
#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
-
-#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
- ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Read_Pipe_Delay
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
* @{
*/
#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
-
-#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
- ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
- ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_LoadToActive_Delay
- * @{
- */
-#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
- * @{
- */
-#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_SelfRefresh_Time
- * @{
- */
-#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
/**
* @}
*/
-
-/** @defgroup FMC_SDRAM_RowCycle_Delay
- * @{
- */
-#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Write_Recovery_Time
- * @{
- */
-#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_RP_Delay
- * @{
- */
-#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_RCD_Delay
- * @{
- */
-#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Command_Mode
+/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
* @{
*/
#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
@@ -936,57 +704,21 @@
#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
-
-#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
- ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
- ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
- ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
- ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
- ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
- ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Command_Target
+/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
* @{
*/
#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
-
-#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
- ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
- ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
/**
* @}
*/
-/** @defgroup FMC_SDRAM_AutoRefresh_Number
- * @{
- */
-#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_ModeRegister_Definition
- * @{
- */
-#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Refresh_rate
- * @{
- */
-#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Mode_Status
+/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
* @{
*/
#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
@@ -995,72 +727,23 @@
/**
* @}
*/
-
-/** @defgroup FMC_NORSRAM_Device_Instance
- * @{
- */
-#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
- * @{
- */
-#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Device_Instance
- * @{
- */
-#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_PCCARD_Device_Instance
- * @{
- */
-#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
+
/**
* @}
*/
-/** @defgroup FMC_SDRAM_Device_Instance
- * @{
- */
-#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Interrupt_definition
- * @brief FMC Interrupt definition
+/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
* @{
*/
#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
#define FMC_IT_LEVEL ((uint32_t)0x00000010)
#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
-
-#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
-
-#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
- ((IT) == FMC_IT_LEVEL) || \
- ((IT) == FMC_IT_FALLING_EDGE) || \
- ((IT) == FMC_IT_REFRESH_ERROR))
/**
* @}
*/
-/** @defgroup FMC_Flag_definition
- * @brief FMC Flag definition
+/** @defgroup FMC_LL_Flag_definition FMC Flag definition
* @{
*/
#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
@@ -1070,26 +753,50 @@
#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
-
-#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
- ((FLAG) == FMC_FLAG_LEVEL) || \
- ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
- ((FLAG) == FMC_FLAG_FEMPT) || \
- ((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) || \
- ((FLAG) == FMC_SDRAM_FLAG_BUSY))
-
-#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMC_LL_Alias_definition FMC Alias definition
+ * @{
+ */
+#if defined(STM32F446xx)
+ #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
+#else
+ #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
+ #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
+#endif /* defined(STM32F446xx) */
+ #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+ #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+ #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
+
-/** @defgroup FMC_NOR_Macros
+#if defined(STM32F446xx)
+ #define FMC_NAND_DEVICE FMC_Bank3
+#else
+ #define FMC_NAND_DEVICE FMC_Bank2_3
+ #define FMC_PCCARD_DEVICE FMC_Bank4
+#endif /* defined(STM32F446xx) */
+ #define FMC_NORSRAM_DEVICE FMC_Bank1
+ #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+ #define FMC_SDRAM_DEVICE FMC_Bank5_6
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC Private Macros
+ * @{
+ */
+
+/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
-
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__: FMC_NORSRAM Instance
@@ -1105,16 +812,31 @@
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
-
/**
* @}
*/
-/** @defgroup FMC_NAND_Macros
+/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
-
+#if defined(STM32F446xx)
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__: FMC_NAND Instance
@@ -1132,15 +854,16 @@
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+
+#endif /* defined(STM32F446xx)*/
/**
* @}
*/
-
-/** @defgroup FMC_PCCARD_Macros
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
* @brief macros to handle SRAM read/write operations
* @{
*/
-
/**
* @brief Enable the PCCARD device access.
* @param __INSTANCE__: FMC_PCCARD Instance
@@ -1157,13 +880,67 @@
/**
* @}
*/
-
-/** @defgroup FMC_Interrupt
- * @brief macros to handle FMC interrupts
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
+/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
+ * @brief macros to handle FMC flags and interrupts
* @{
*/
+#if defined(STM32F446xx)
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__: FMC_NAND instance
* @param __BANK__: FMC_NAND Bank
@@ -1179,7 +956,7 @@
/**
* @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND handle
+ * @param __INSTANCE__: FMC_NAND Instance
* @param __BANK__: FMC_NAND Bank
* @param __INTERRUPT__: FMC_NAND interrupt
* This parameter can be any combination of the following values:
@@ -1193,7 +970,7 @@
/**
* @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND handle
+ * @param __INSTANCE__: FMC_NAND Instance
* @param __BANK__: FMC_NAND Bank
* @param __FLAG__: FMC_NAND flag
* This parameter can be any combination of the following values:
@@ -1207,7 +984,7 @@
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND handle
+ * @param __INSTANCE__: FMC_NAND Instance
* @param __BANK__: FMC_NAND Bank
* @param __FLAG__: FMC_NAND flag
* This parameter can be any combination of the following values:
@@ -1218,7 +995,10 @@
* @retval None
*/
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+#endif /* defined(STM32F446xx) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/**
* @brief Enable the PCCARD device interrupt.
* @param __INSTANCE__: FMC_PCCARD instance
@@ -1268,7 +1048,8 @@
* @retval None
*/
#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
-
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
/**
* @brief Enable the SDRAM device interrupt.
* @param __INSTANCE__: FMC_SDRAM instance
@@ -1312,64 +1093,325 @@
#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
/**
* @}
+ */
+
+/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
+ * @{
+ */
+#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
+ ((BANK) == FMC_NORSRAM_BANK2) || \
+ ((BANK) == FMC_NORSRAM_BANK3) || \
+ ((BANK) == FMC_NORSRAM_BANK4))
+
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
+
+#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
+ ((BANK) == FMC_NAND_BANK3))
+
+#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+
+#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
+
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#if !defined (STM32F446xx)
+#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FMC_WRAP_MODE_ENABLE))
+#endif /* !defined (STM32F446xx) */
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+
+#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+
+#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
+ ((BANK) == FMC_SDRAM_BANK2))
+
+#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+
+#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
+
+#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
+ ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+
+
+#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
+
+#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
+
+#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
+ ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
+
+
+#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
+
+#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+
+#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+
+#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
+ ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
+
+#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
+
+#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
+
+#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
+
+#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
+
+#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
+
+#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
+ ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+
+#if defined (STM32F446xx)
+#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
+ ((SIZE) == FMC_PAGE_SIZE_128) || \
+ ((SIZE) == FMC_PAGE_SIZE_256) || \
+ ((SIZE) == FMC_PAGE_SIZE_1024))
+
+#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
+ ((FIFO) == FMC_WRITE_FIFO_ENABLE))
+#endif /* defined (STM32F446xx) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
*/
-/* Exported functions --------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
+ * @{
+ */
-/* FMC_NORSRAM Controller functions *******************************************/
-/* Initialization/de-initialization functions */
+/** @defgroup FMC_LL_NORSRAM NOR SRAM
+ * @{
+ */
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
-/* FMC_NORSRAM Control functions */
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+ * @{
+ */
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
-/* FMC_NAND Controller functions **********************************************/
-/* Initialization/de-initialization functions */
+/** @defgroup FMC_LL_NAND NAND
+ * @{
+ */
+/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
-/* FMC_NAND Control functions */
+/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+ * @{
+ */
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-/* FMC_PCCARD Controller functions ********************************************/
-/* Initialization/de-initialization functions */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup FMC_LL_PCCARD PCCARD
+ * @{
+ */
+/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-/* FMC_SDRAM Controller functions *********************************************/
-/* Initialization/de-initialization functions */
+/** @defgroup FMC_LL_SDRAM SDRAM
+ * @{
+ */
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
-/* FMC_SDRAM Control functions */
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
+ * @{
+ */
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
- */
+ */
+/**
+ * @}
+ */
/**
* @}
*/
-
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief FSMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -78,27 +78,24 @@
* @{
*/
-/** @defgroup FSMC
+/** @defgroup FSMC_LL FSMC Low Layer
* @brief FSMC driver modules
* @{
*/
#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
-
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FSMC_Private_Functions
+/** @addtogroup FSMC_LL_Private_Functions
* @{
*/
-/** @defgroup FSMC_NORSRAM Controller functions
+/** @addtogroup FSMC_LL_NORSRAM
* @brief NORSRAM Controller functions
*
@verbatim
@@ -122,7 +119,7 @@
* @{
*/
-/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -165,20 +162,30 @@
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Init->NSBank];
+
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
+ tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
+ FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
+ FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
+ FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
+ FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
/* Set NORSRAM device control parameters */
- tmpr = (uint32_t)(Init->DataAddressMux |\
- Init->MemoryType |\
- Init->MemoryDataWidth |\
- Init->BurstAccessMode |\
- Init->WaitSignalPolarity |\
- Init->WrapMode |\
- Init->WaitSignalActive |\
- Init->WriteOperation |\
- Init->WaitSignal |\
- Init->ExtendedMode |\
- Init->AsynchronousWait |\
- Init->WriteBurst
- );
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WrapMode |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst
+ );
if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
{
@@ -190,7 +197,6 @@
return HAL_OK;
}
-
/**
* @brief DeInitialize the FSMC_NORSRAM peripheral
* @param Device: Pointer to NORSRAM device instance
@@ -247,15 +253,22 @@
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Bank + 1];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
+ FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
+ FSMC_BTR1_ACCMOD));
+
/* Set FSMC_NORSRAM device timing parameters */
- tmpr = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode)
- );
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (((Timing->CLKDivision)-1) << 20) |\
+ (((Timing->DataLatency)-2) << 24) |\
+ (Timing->AccessMode));
Device->BTCR[Bank + 1] = tmpr;
@@ -272,6 +285,8 @@
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
+ uint32_t tmpr = 0;
+
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
{
@@ -284,13 +299,23 @@
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
- Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode));
+ /* Get the BWTR register value */
+ tmpr = Device->BWTR[Bank];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
+ FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
+ FSMC_BWTR1_ACCMOD));
+
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (((Timing->CLKDivision)-1) << 20) |\
+ (((Timing->DataLatency)-2) << 24) |\
+ (Timing->AccessMode));
+
+ Device->BWTR[Bank] = tmpr;
}
else
{
@@ -299,16 +324,13 @@
return HAL_OK;
}
-
-
/**
* @}
*/
-
-/** @defgroup HAL_FSMC_NORSRAM_Group3 Control functions
- * @brief management functions
- *
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FSMC_NORSRAM Control functions #####
@@ -348,7 +370,6 @@
return HAL_OK;
}
-
/**
* @}
*/
@@ -357,8 +378,8 @@
* @}
*/
-/** @defgroup FSMC_PCCARD Controller functions
- * @brief PCCARD Controller functions
+/** @addtogroup FSMC_LL_NAND
+ * @brief NAND Controller functions
*
@verbatim
==============================================================================
@@ -382,9 +403,9 @@
* @{
*/
-/** @defgroup HAL_FSMC_NAND_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
+/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -408,7 +429,7 @@
*/
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
{
- uint32_t tmppcr = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
@@ -419,29 +440,43 @@
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+ if(Init->NandBank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PCR2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PCR3;
+ }
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
+ FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
+ FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
+
/* Set NAND device control parameters */
- tmppcr = (uint32_t)(Init->Waitfeature |\
- FSMC_PCR_MEMORY_TYPE_NAND |\
- Init->MemoryDataWidth |\
- Init->EccComputation |\
- Init->ECCPageSize |\
- ((Init->TCLRSetupTime) << 9) |\
- ((Init->TARSetupTime) << 13)
- );
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FSMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9) |\
+ ((Init->TARSetupTime) << 13));
if(Init->NandBank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PCR2 = tmppcr;
+ Device->PCR2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PCR3 = tmppcr;
+ Device->PCR3 = tmpr;
}
return HAL_OK;
-
}
/**
@@ -454,7 +489,7 @@
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
- uint32_t tmppmem = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
@@ -462,8 +497,23 @@
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PMEM3;
+ }
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
+ FSMC_PMEM2_MEMHIZ2));
+
/* Set FSMC_NAND device timing parameters */
- tmppmem = (uint32_t)(Timing->SetupTime |\
+ tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
@@ -472,12 +522,12 @@
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PMEM2 = tmppmem;
+ Device->PMEM2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PMEM3 = tmppmem;
+ Device->PMEM3 = tmpr;
}
return HAL_OK;
@@ -493,7 +543,7 @@
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
- uint32_t tmppatt = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
@@ -501,8 +551,23 @@
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PATT2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PATT3;
+ }
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
+ FSMC_PATT2_ATTHIZ2));
+
/* Set FSMC_NAND device timing parameters */
- tmppatt = (uint32_t)(Timing->SetupTime |\
+ tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
@@ -511,18 +576,17 @@
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PATT2 = tmppatt;
+ Device->PATT2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PATT3 = tmppatt;
+ Device->PATT3 = tmpr;
}
return HAL_OK;
}
-
/**
* @brief DeInitializes the FSMC_NAND device
* @param Device: Pointer to NAND device instance
@@ -555,15 +619,13 @@
return HAL_OK;
}
-
/**
* @}
*/
-
-/** @defgroup HAL_FSMC_NAND_Group3 Control functions
- * @brief management functions
- *
+/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FSMC_NAND Control functions #####
@@ -575,7 +637,6 @@
@endverbatim
* @{
*/
-
/**
* @brief Enables dynamically FSMC_NAND ECC feature.
@@ -598,7 +659,6 @@
return HAL_OK;
}
-
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
* @param Device: Pointer to NAND device instance
@@ -639,8 +699,8 @@
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait untill FIFO is empty */
- while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT))
+ /* Wait until FIFO is empty */
+ while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -674,7 +734,7 @@
* @}
*/
-/** @defgroup FSMC_PCCARD Controller functions
+/** @addtogroup FSMC_LL_PCCARD
* @brief PCCARD Controller functions
*
@verbatim
@@ -698,9 +758,9 @@
* @{
*/
-/** @defgroup HAL_FSMC_PCCARD_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
+/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -724,19 +784,29 @@
*/
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+ /* Get PCCARD control register value */
+ tmpr = Device->PCR4;
+
+ /* Clear TAR, TCLR, PWAITEN and PWID bits */
+ tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
+ FSMC_PCR4_PWID));
+
/* Set FSMC_PCCARD device control parameters */
- Device->PCR4 = (uint32_t)(Init->Waitfeature |\
- FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
- (Init->TCLRSetupTime << 9) |\
- (Init->TARSetupTime << 13));
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
+ (Init->TCLRSetupTime << 9) |\
+ (Init->TARSetupTime << 13));
+
+ Device->PCR4 = tmpr;
return HAL_OK;
-
}
/**
@@ -748,19 +818,28 @@
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get PCCARD common space timing register value */
+ tmpr = Device->PMEM4;
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
+ FSMC_PMEM4_MEMHIZ4));
/* Set PCCARD timing parameters */
- Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
+ tmpr |= (uint32_t)((Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ (Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+
+ Device->PMEM4 = tmpr;
+
return HAL_OK;
}
@@ -773,18 +852,27 @@
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get PCCARD timing parameters */
+ tmpr = Device->PATT4;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
+ FSMC_PATT4_ATTHIZ4));
+
/* Set PCCARD timing parameters */
- Device->PATT4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+ Device->PATT4 = tmpr;
return HAL_OK;
}
@@ -798,18 +886,28 @@
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get FSMC_PCCARD device timing parameters */
+ tmpr = Device->PIO4;
+
+ /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
+ tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
+ FSMC_PIO4_IOHIZ4));
+
/* Set FSMC_PCCARD device timing parameters */
- Device->PIO4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+
+ Device->PIO4 = tmpr;
return HAL_OK;
}
@@ -833,7 +931,6 @@
return HAL_OK;
}
-
/**
* @}
*/
@@ -842,9 +939,11 @@
* @}
*/
+/**
+ * @}
+ */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#endif /* HAL_FSMC_MODULE_ENABLED */
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
/**
* @}
@@ -853,5 +952,4 @@
/**
* @}
*/
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,32 +43,25 @@
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-
-/** @addtogroup FSMC
+
+/** @addtogroup FSMC_LL
* @{
- */
+ */
-/* Exported typedef ----------------------------------------------------------*/
-#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
-#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
-#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-
-#define FSMC_NORSRAM_DEVICE FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
-#define FSMC_NAND_DEVICE FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE FSMC_Bank4
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Types FSMC Private Types
+ * @{
+ */
/**
- * @brief FSMC_NORSRAM Configuration Structure definition
+ * @brief FSMC NORSRAM Configuration Structure definition
*/
typedef struct
{
@@ -123,7 +116,7 @@
}FSMC_NORSRAM_InitTypeDef;
/**
- * @brief FSMC_NORSRAM Timing parameters structure definition
+ * @brief FSMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
@@ -167,7 +160,7 @@
}FSMC_NORSRAM_TimingTypeDef;
/**
- * @brief FSMC_NAND Configuration Structure definition
+ * @brief FSMC NAND Configuration Structure definition
*/
typedef struct
{
@@ -197,7 +190,7 @@
}FSMC_NAND_InitTypeDef;
/**
- * @brief FSMC_NAND_PCCARD Timing parameters structure definition
+ * @brief FSMC NAND/PCCARD Timing parameters structure definition
*/
typedef struct
{
@@ -229,7 +222,7 @@
}FSMC_NAND_PCC_TimingTypeDef;
/**
- * @brief FSMC_NAND Configuration Structure definition
+ * @brief FSMC NAND Configuration Structure definition
*/
typedef struct
{
@@ -245,74 +238,59 @@
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FSMC_PCCARD_InitTypeDef;
+/**
+ * @}
+ */
-/* Exported constants --------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
+ * @{
+ */
-/** @defgroup FSMC_NOR_SRAM_Controller
+/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
* @{
*/
-
-/** @defgroup FSMC_NORSRAM_Bank
+/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
* @{
*/
#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
- ((BANK) == FSMC_NORSRAM_BANK2) || \
- ((BANK) == FSMC_NORSRAM_BANK3) || \
- ((BANK) == FSMC_NORSRAM_BANK4))
/**
* @}
*/
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
* @{
*/
-
#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
-
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_Memory_Type
+/** @defgroup FSMC_Memory_Type FSMC Memory Type
* @{
*/
-
#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
-
-
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
- ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
- ((MEMORY) == FSMC_MEMORY_TYPE_NOR))
/**
* @}
*/
-/** @defgroup FSMC_NORSRAM_Data_Width
+/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
* @{
*/
-
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
-
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
/**
* @}
*/
-/** @defgroup FSMC_NORSRAM_Flash_Access
+/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
* @{
*/
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
@@ -321,232 +299,132 @@
* @}
*/
-/** @defgroup FSMC_Burst_Access_Mode
+/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
* @{
*/
-
#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
-
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
- ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
/**
* @}
*/
-
-/** @defgroup FSMC_Wait_Signal_Polarity
+/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
* @{
*/
#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
-
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode
- * @{
- */
-#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
-#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
-
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
- ((MODE) == FSMC_WRAP_MODE_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_Wait_Timing
+/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
+ * @{
+ */
+#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
* @{
*/
#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
-
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
/**
* @}
*/
-/** @defgroup FSMC_Write_Operation
+/** @defgroup FSMC_Write_Operation FSMC Write Operation
* @{
*/
#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
-
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal
- * @{
- */
-#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
-#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
-
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode
- * @{
- */
-#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
- ((MODE) == FSMC_EXTENDED_MODE_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_AsynchronousWait
+/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
+ * @{
+ */
+#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
+ * @{
+ */
+#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
* @{
*/
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
-
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
/**
* @}
*/
-/** @defgroup FSMC_Write_Burst
+/** @defgroup FSMC_Write_Burst FSMC Write Burst
* @{
*/
-
#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
-
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
- ((BURST) == FSMC_WRITE_BURST_ENABLE))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Continous_Clock
- * @{
- */
-
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
-
-#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-
/**
* @}
*/
-/** @defgroup FSMC_Address_Setup_Time
+/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
* @{
*/
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
/**
* @}
*/
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
+/** @defgroup FSMC_Access_Mode FSMC Access Mode
* @{
*/
#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
-
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
- ((MODE) == FSMC_ACCESS_MODE_B) || \
- ((MODE) == FSMC_ACCESS_MODE_C) || \
- ((MODE) == FSMC_ACCESS_MODE_D))
/**
* @}
*/
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Controller
- * @{
- */
-
-/** @defgroup FSMC_NAND_Bank
- * @{
- */
-#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
-#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
- ((BANK) == FSMC_NAND_BANK3))
-
/**
* @}
*/
-/** @defgroup FSMC_Wait_feature
+/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
+ * @{
+ */
+/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
+ * @{
+ */
+#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_feature FSMC Wait feature
* @{
*/
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
-
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_PCR_Memory_Type
+/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
* @{
*/
#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
@@ -555,31 +433,25 @@
* @}
*/
-/** @defgroup FSMC_NAND_Data_Width
+/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
* @{
*/
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-
-#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
/**
* @}
*/
-/** @defgroup FSMC_ECC
+/** @defgroup FSMC_ECC FSMC ECC
* @{
*/
#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
-
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
- ((STATE) == FSMC_NAND_ECC_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_ECC_Page_Size
+/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
* @{
*/
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
@@ -588,376 +460,48 @@
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
-
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
/**
* @}
*/
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
/**
* @}
*/
-
-
-/** @defgroup FSMC_NORSRAM_Device_Instance
- * @{
- */
-#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
- * @{
- */
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-/**
- * @}
- */
-
- /** @defgroup FSMC_NAND_Device_Instance
- * @{
- */
-#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Device_Instance
- * @{
- */
-#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
-
-/**
- * @}
- */
-/** @defgroup FSMC_Interrupt_definition
- * @brief FSMC Interrupt definition
+/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
* @{
*/
#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
-
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \
- ((IT) == FSMC_IT_LEVEL) || \
- ((IT) == FSMC_IT_FALLING_EDGE) || \
- ((IT) == FSMC_IT_REFRESH_ERROR))
/**
* @}
*/
-/** @defgroup FSMC_Flag_definition
- * @brief FSMC Flag definition
+/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
* @{
*/
#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
-
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \
- ((FLAG) == FSMC_FLAG_LEVEL) || \
- ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-
-
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
-
-
-/** @defgroup FSMC_NOR_Macros
- * @brief macros to handle NOR device enable/disable and read/write operations
- * @{
- */
-
-/**
- * @brief Enable the NORSRAM device access.
- * @param __INSTANCE__: FSMC_NORSRAM Instance
- * @param __BANK__: FSMC_NORSRAM Bank
- * @retval none
- */
-#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
-
-/**
- * @brief Disable the NORSRAM device access.
- * @param __INSTANCE__: FSMC_NORSRAM Instance
- * @param __BANK__: FSMC_NORSRAM Bank
- * @retval none
- */
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
-
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_NAND_Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
-
-/**
- * @brief Enable the NAND device access.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @retval none
- */
-#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
-
-
-/**
- * @brief Disable the NAND device access.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @retval none
- */
-#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
-
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Macros
- * @brief macros to handle SRAM read/write operations
- * @{
- */
-
-/**
- * @brief Enable the PCCARD device access.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @retval none
- */
-#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
-
-/**
- * @brief Disable the PCCARD device access.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @retval none
- */
-#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt
- * @brief macros to handle FSMC interrupts
- * @{
- */
-
-/**
- * @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __INTERRUPT__: FSMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
-
-/**
- * @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __INTERRUPT__: FSMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
+/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
+ * @{
*/
-#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
-
-/**
- * @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __FLAG__: FSMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
-/**
- * @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __FLAG__: FSMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval None
- */
-#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
-/**
- * @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __INTERRUPT__: FSMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
-
-/**
- * @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __INTERRUPT__: FSMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
+#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-/**
- * @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __FLAG__: FSMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __FLAG__: FSMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval None
- */
-#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
-/* FSMC_NORSRAM Controller functions ******************************************/
-/* Initialization/de-initialization functions */
-HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-
-/* FSMC_NORSRAM Control functions */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-
-/* FSMC_NAND Controller functions *********************************************/
-/* Initialization/de-initialization functions */
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-
-/* FSMC_NAND Control functions */
-HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-
-/* FSMC_PCCARD Controller functions *******************************************/
-/* Initialization/de-initialization functions */
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
-
-/* FSMC APIs, macros and typedefs redefinition */
#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
@@ -1028,7 +572,393 @@
#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
+ * @brief macros to handle FSMC flags and interrupts
+ * @{
+ */
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__ : FSMC_NAND Bank
+ * @param __FLAG__ : FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __FLAG__: FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
+ * @{
+ */
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK4))
+
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_D))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
+ ((BANK) == FSMC_NAND_BANK3))
+
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FSMC_NAND_ECC_ENABLE))
+
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
+
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
+
+#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
+
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+
+#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NORSRAM NOR SRAM
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_NAND NAND
+ * @{
+ */
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_PCCARD PCCARD
+ * @{
+ */
+/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -21,13 +21,6 @@
peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
devices.
- [..] The MultiMedia Card system specifications are available through the MultiMedia Card
- Association website at www.mmca.org, published by the MMCA technical committee.
- SD memory card and SD I/O card system specifications are available through the SD card
- Association website at www.sdcard.org.
- CE-ATA system specifications are available through the CE-ATA work group web site at
- www.ce-ata.org.
-
[..] The SDIO features include the following:
(+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
@@ -67,7 +60,7 @@
peripheral.
(+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
- function and disable it using the function HAL_SDIO_PowerState_OFF(SDIOx).
+ function and disable it using the function SDIO_PowerState_OFF(SDIOx).
(+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
@@ -107,7 +100,7 @@
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
- (++) Data TimeOut
+ (++) Data Timeout
(++) Data Length
(++) Data Block size
(++) Data Transfer direction: should be from card (To SDIO)
@@ -127,7 +120,7 @@
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
- (++) Data TimeOut
+ (++) Data Timeout
(++) Data Length
(++) Data Block size
(++) Data Transfer direction: should be to card (To CARD)
@@ -145,7 +138,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -179,8 +172,8 @@
* @{
*/
-/** @defgroup SDMMC
- * @brief SDMMC HAL module driver
+/** @defgroup SDMMC_LL SDMMC Low Layer
+ * @brief Low layer module for SD and MMC driver
* @{
*/
@@ -193,11 +186,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup SDIO_Private_Functions
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
* @{
*/
-/** @defgroup HAL_SDIO_Group1 Initialization/de-initialization functions
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -245,13 +238,11 @@
return HAL_OK;
}
-
-
/**
* @}
*/
-/** @defgroup HAL_SDIO_Group2 I/O operation functions
+/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
* @brief Data transfers functions
*
@verbatim
@@ -295,7 +286,7 @@
* @}
*/
-/** @defgroup HAL_SDIO_Group3 Peripheral Control functions
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
@@ -436,7 +427,7 @@
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
- /* Set the SDIO Data TimeOut value */
+ /* Set the SDIO Data Timeout value */
SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
/* Set the SDIO DataLength value */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,13 +50,12 @@
* @{
*/
-/** @addtogroup SDMMC
+/** @addtogroup SDMMC_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup SDIO_Exported_Types SDIO Exported Types
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
* @{
*/
@@ -143,12 +142,11 @@
*/
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SDIO_Exported_Constants
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
-/** @defgroup SDIO_Clock_Edge
+/** @defgroup SDIO_Clock_Edge Clock Edge
* @{
*/
#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
@@ -160,7 +158,7 @@
* @}
*/
-/** @defgroup SDIO_Clock_Bypass
+/** @defgroup SDIO_Clock_Bypass Clock Bypass
* @{
*/
#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
@@ -172,7 +170,7 @@
* @}
*/
-/** @defgroup SDIO_Clock_Power_Save
+/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
* @{
*/
#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
@@ -184,7 +182,7 @@
* @}
*/
-/** @defgroup SDIO_Bus_Wide
+/** @defgroup SDIO_Bus_Wide Bus Width
* @{
*/
#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
@@ -198,7 +196,7 @@
* @}
*/
-/** @defgroup SDIO_Hardware_Flow_Control
+/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
* @{
*/
#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
@@ -210,7 +208,7 @@
* @}
*/
-/** @defgroup SDIO_Clock_Division
+/** @defgroup SDIO_Clock_Division Clock Division
* @{
*/
#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
@@ -218,7 +216,7 @@
* @}
*/
-/** @defgroup SDIO_Command_Index
+/** @defgroup SDIO_Command_Index Command Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
@@ -226,7 +224,7 @@
* @}
*/
-/** @defgroup SDIO_Response_Type
+/** @defgroup SDIO_Response_Type Response Type
* @{
*/
#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
@@ -240,7 +238,7 @@
* @}
*/
-/** @defgroup SDIO_Wait_Interrupt_State
+/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
* @{
*/
#define SDIO_WAIT_NO ((uint32_t)0x00000000)
@@ -254,7 +252,7 @@
* @}
*/
-/** @defgroup SDIO_CPSM_State
+/** @defgroup SDIO_CPSM_State CPSM State
* @{
*/
#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
@@ -266,7 +264,7 @@
* @}
*/
-/** @defgroup SDIO_Response_Registers
+/** @defgroup SDIO_Response_Registers Response Register
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
@@ -282,7 +280,7 @@
* @}
*/
-/** @defgroup SDIO_Data_Length
+/** @defgroup SDIO_Data_Length Data Lenght
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
@@ -290,7 +288,7 @@
* @}
*/
-/** @defgroup SDIO_Data_Block_Size
+/** @defgroup SDIO_Data_Block_Size Data Block Size
* @{
*/
#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
@@ -328,7 +326,7 @@
* @}
*/
-/** @defgroup SDIO_Transfer_Direction
+/** @defgroup SDIO_Transfer_Direction Transfer Direction
* @{
*/
#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
@@ -340,7 +338,7 @@
* @}
*/
-/** @defgroup SDIO_Transfer_Type
+/** @defgroup SDIO_Transfer_Type Transfer Type
* @{
*/
#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
@@ -352,7 +350,7 @@
* @}
*/
-/** @defgroup SDIO_DPSM_State
+/** @defgroup SDIO_DPSM_State DPSM State
* @{
*/
#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
@@ -364,11 +362,11 @@
* @}
*/
-/** @defgroup SDIO_Read_Wait_Mode
+/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
* @{
*/
-#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
-#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
+#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
+#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
((MODE) == SDIO_READ_WAIT_MODE_DATA2))
@@ -376,7 +374,7 @@
* @}
*/
-/** @defgroup SDIO_Interrupt_sources
+/** @defgroup SDIO_Interrupt_sources Interrupt Sources
* @{
*/
#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
@@ -403,13 +401,11 @@
#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
-
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
-/** @defgroup SDIO_Flags
+/** @defgroup SDIO_Flags Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
@@ -436,124 +432,77 @@
#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
-
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \
- ((FLAG) == SDIO_FLAG_RXOVERR) || \
- ((FLAG) == SDIO_FLAG_CMDREND) || \
- ((FLAG) == SDIO_FLAG_CMDSENT) || \
- ((FLAG) == SDIO_FLAG_DATAEND) || \
- ((FLAG) == SDIO_FLAG_STBITERR) || \
- ((FLAG) == SDIO_FLAG_DBCKEND) || \
- ((FLAG) == SDIO_FLAG_CMDACT) || \
- ((FLAG) == SDIO_FLAG_TXACT) || \
- ((FLAG) == SDIO_FLAG_RXACT) || \
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \
- ((FLAG) == SDIO_FLAG_TXDAVL) || \
- ((FLAG) == SDIO_FLAG_RXDAVL) || \
- ((FLAG) == SDIO_FLAG_SDIOIT) || \
- ((FLAG) == SDIO_FLAG_CEATAEND))
-
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
-
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
- ((IT) == SDIO_IT_DCRCFAIL) || \
- ((IT) == SDIO_IT_CTIMEOUT) || \
- ((IT) == SDIO_IT_DTIMEOUT) || \
- ((IT) == SDIO_IT_TXUNDERR) || \
- ((IT) == SDIO_IT_RXOVERR) || \
- ((IT) == SDIO_IT_CMDREND) || \
- ((IT) == SDIO_IT_CMDSENT) || \
- ((IT) == SDIO_IT_DATAEND) || \
- ((IT) == SDIO_IT_STBITERR) || \
- ((IT) == SDIO_IT_DBCKEND) || \
- ((IT) == SDIO_IT_CMDACT) || \
- ((IT) == SDIO_IT_TXACT) || \
- ((IT) == SDIO_IT_RXACT) || \
- ((IT) == SDIO_IT_TXFIFOHE) || \
- ((IT) == SDIO_IT_RXFIFOHF) || \
- ((IT) == SDIO_IT_TXFIFOF) || \
- ((IT) == SDIO_IT_RXFIFOF) || \
- ((IT) == SDIO_IT_TXFIFOE) || \
- ((IT) == SDIO_IT_RXFIFOE) || \
- ((IT) == SDIO_IT_TXDAVL) || \
- ((IT) == SDIO_IT_RXDAVL) || \
- ((IT) == SDIO_IT_SDIOIT) || \
- ((IT) == SDIO_IT_CEATAEND))
-
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
/**
* @}
*/
-
-
-/** @defgroup SDIO_Instance_definition
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
* @{
- */
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+ */
-/**
- * @}
+/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
+ * @{
*/
-
-/* Exported macro ------------------------------------------------------------*/
/* ------------ SDIO registers bit address in the alias region -------------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/* --- CLKCR Register ---*/
/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+#define CLKEN_BITNUMBER 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
/* --- CMD Register ---*/
/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+#define SDIOSUSPEND_BITNUMBER 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+#define ENCMDCOMPL_BITNUMBER 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+#define NIEN_BITNUMBER 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+#define ATACMD_BITNUMBER 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
/* --- DCTRL Register ---*/
/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+#define DMAEN_BITNUMBER 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+#define RWSTART_BITNUMBER 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+#define RWSTOP_BITNUMBER 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+#define RWMOD_BITNUMBER 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+#define SDIOEN_BITNUMBER 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+ * @brief SDMMC_LL registers bit address in the alias region
+ * @{
+ */
/* ---------------------- SDIO registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
@@ -577,41 +526,40 @@
/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-/* SDIO Intialization Frequency (400KHz max) */
+/* SDIO Initialization Frequency (400KHz max) */
#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
/* SDIO Data Transfer Frequency (25MHz max) */
#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+/**
+ * @}
+ */
-/** @defgroup SDIO_Interrupt_Clock
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
/**
* @brief Enable the SDIO device.
- * @param None
* @retval None
*/
#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
/**
* @brief Disable the SDIO device.
- * @param None
* @retval None
*/
#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
/**
* @brief Enable the SDIO DMA transfer.
- * @param None
* @retval None
*/
#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
/**
* @brief Disable the SDIO DMA transfer.
- * @param None
* @retval None
*/
#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
@@ -798,102 +746,89 @@
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param None
* @retval None
*/
#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
/**
* @brief Disable Start the SD I/O Read Wait operations.
- * @param None
* @retval None
*/
#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param None
* @retval None
*/
#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
- * @param None
* @retval None
*/
#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
/**
* @brief Enable the SD I/O Mode Operation.
- * @param None
* @retval None
*/
#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
/**
* @brief Disable the SD I/O Mode Operation.
- * @param None
* @retval None
*/
#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
/**
* @brief Enable the SD I/O Suspend command sending.
- * @param None
* @retval None
*/
#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
/**
* @brief Disable the SD I/O Suspend command sending.
- * @param None
* @retval None
*/
#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-
+
+#if !defined(STM32F446xx)
/**
* @brief Enable the command completion signal.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
/**
* @brief Disable the command completion signal.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
/**
* @brief Enable the CE-ATA interrupt.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
/**
* @brief Disable the CE-ATA interrupt.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
/**
* @brief Enable send CE-ATA command (CMD61).
- * @param None
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
/**
* @brief Disable send CE-ATA command (CMD61).
- * @param None
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-
+#endif /* !defined(STM32F446xx) */
/**
* @}
*/
@@ -903,12 +838,12 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDIO_Exported_Functions
+/** @addtogroup SDMMC_LL_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
-/** @addtogroup HAL_SDIO_Group1
+/** @addtogroup HAL_SDMMC_LL_Group1
* @{
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
@@ -917,7 +852,7 @@
*/
/* I/O operation functions *****************************************************/
-/** @addtogroup HAL_SDIO_Group2
+/** @addtogroup HAL_SDMMC_LL_Group2
* @{
*/
/* Blocking mode: Polling */
@@ -928,7 +863,7 @@
*/
/* Peripheral Control functions ************************************************/
-/** @addtogroup HAL_SDIO_Group3
+/** @addtogroup HAL_SDMMC_LL_Group3
* @{
*/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c Thu Apr 30 13:45:11 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_usb.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -22,13 +22,13 @@
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
- (#) The upper HAL HCD/PCD driver will call the righ routines for its internal processes.
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -167,7 +167,7 @@
* @param USBx : Selected device
* @param mode : current core mode
* This parameter can be one of the these values:
- * @arg USB_OTG_DEVICE_MODE: Peripheral mode mode
+ * @arg USB_OTG_DEVICE_MODE: Peripheral mode
* @arg USB_OTG_HOST_MODE: Host mode
* @arg USB_OTG_DRD_MODE: Dual Role Device mode
* @retval HAL status
@@ -202,13 +202,27 @@
uint32_t i = 0;
/*Activate VBUS Sensing B */
+#if defined(STM32F446xx)
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+
+ if (cfg.vbus_sensing_enable == 0)
+ {
+ /*Desactivate VBUS Sensing B */
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+ /* B-peripheral session valid override enable*/
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+ }
+#else
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
if (cfg.vbus_sensing_enable == 0)
{
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
}
-
+#endif /* STM32F446xx */
+
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
@@ -779,12 +793,12 @@
* @param USBx : Selected device
* @param src : source pointer
* @param ch_ep_num : endpoint or host channel number
- * @param len : Noumber of bytes to read
+ * @param len : Number of bytes to read
* @param dma: USB dma enabled or disabled
* This parameter can be one of the these values:
* 0 : DMA feature not used
* 1 : DMA feature used
- * @retval pointer to desctination buffer
+ * @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
@@ -1121,11 +1135,15 @@
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
- /* no VBUS sensing*/
+ /* Activate VBUS Sensing B */
+#if defined(STM32F446xx)
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#else
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-
+#endif /* STM32F446xx */
+
/* Disable the FS/LS support mode only */
if((cfg.speed == USB_OTG_SPEED_FULL)&&
(USBx != USB_OTG_FS))
@@ -1310,7 +1328,7 @@
* @param ep_type : Endpoint Type
* This parameter can be one of the these values:
* @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochrounous type
+ * @arg EP_TYPE_ISOC: Isochronous type
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
* @param mps : Max Packet Size
@@ -1668,7 +1686,7 @@
while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
- /* Clear any pending Host interrups */
+ /* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFF;
USBx->GINTSTS = 0xFFFFFFFF;
USB_EnableGlobalInt(USBx);
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h Thu Apr 30 13:45:11 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_usb.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 19-June-2014
+ * @version V1.3.0
+ * @date 09-March-2015
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -122,7 +122,9 @@
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
@@ -224,11 +226,11 @@
/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-/** @defgroup USB_Core_Mode_
+/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0
@@ -238,7 +240,7 @@
* @}
*/
-/** @defgroup USB_Core_Speed_
+/** @defgroup USB_Core_Speed_ USB Core Speed
* @{
*/
#define USB_OTG_SPEED_HIGH 0
@@ -249,7 +251,7 @@
* @}
*/
-/** @defgroup USB_Core_PHY_
+/** @defgroup USB_Core_PHY_ USB Core PHY
* @{
*/
#define USB_OTG_ULPI_PHY 1
@@ -258,7 +260,7 @@
* @}
*/
-/** @defgroup USB_Core_MPS_
+/** @defgroup USB_Core_MPS_ USB Core MPS
* @{
*/
#define USB_OTG_HS_MAX_PACKET_SIZE 512
@@ -268,7 +270,7 @@
* @}
*/
-/** @defgroup USB_Core_Phy_Frequency_
+/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
@@ -279,7 +281,7 @@
* @}
*/
-/** @defgroup USB_CORE_Frame_Interval_
+/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0
@@ -290,7 +292,7 @@
* @}
*/
-/** @defgroup USB_EP0_MPS_
+/** @defgroup USB_EP0_MPS_ USB EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0
@@ -301,7 +303,7 @@
* @}
*/
-/** @defgroup USB_EP_Speed_
+/** @defgroup USB_EP_Speed_ USB EP Speed
* @{
*/
#define EP_SPEED_LOW 0
@@ -311,7 +313,7 @@
* @}
*/
-/** @defgroup USB_EP_Type_
+/** @defgroup USB_EP_Type_ USB EP Type
* @{
*/
#define EP_TYPE_CTRL 0
@@ -323,7 +325,7 @@
* @}
*/
-/** @defgroup USB_STS_Defines_
+/** @defgroup USB_STS_Defines_ USB STS Defines
* @{
*/
#define STS_GOUT_NAK 1
@@ -335,7 +337,7 @@
* @}
*/
-/** @defgroup HCFG_SPEED_Defines_
+/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
* @{
*/
#define HCFG_30_60_MHZ 0
@@ -345,7 +347,7 @@
* @}
*/
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0
@@ -380,7 +382,9 @@
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-
+/**
+ * @}
+ */
/* Exported macro ------------------------------------------------------------*/
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
--- a/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_api.c Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_api.c Thu Apr 30 13:45:11 2015 +0100
@@ -55,10 +55,9 @@
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
// Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set = &gpio->BSRRL;
- obj->reg_clr = &gpio->BSRRH;
+ obj->mask = gpio_set(pin);
+ obj->reg_in = &gpio->IDR;
+ obj->reg_set_clr = &gpio->BSRR;
}
void gpio_mode(gpio_t *obj, PinMode mode)
--- a/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_object.h Thu Apr 30 13:00:08 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_object.h Thu Apr 30 13:45:11 2015 +0100
@@ -44,17 +44,16 @@
PinName pin;
uint32_t mask;
__IO uint32_t *reg_in;
- __IO uint16_t *reg_set;
- __IO uint16_t *reg_clr;
+ __IO uint32_t *reg_set_clr;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
{
MBED_ASSERT(obj->pin != (PinName)NC);
if (value) {
- *obj->reg_set = obj->mask;
+ *obj->reg_set_clr = obj->mask;
} else {
- *obj->reg_clr = obj->mask;
+ *obj->reg_set_clr = obj->mask << 16;
}
}