Steve Kim
mbed library sources(for async_print)
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mbed-src
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mbed official
Revision 80:66393a7b209d, committed 2014-01-30
- Comitter:
- mbed_official
- Date:
- Thu Jan 30 12:15:05 2014 +0000
- Parent:
- 79:6fdc4ea80ae0
- Child:
- 81:a9456fdf72fa
- Commit message:
- Synchronized with git revision dba523f83fe09b7fce11fc1299dd1216e9776359
Full URL: https://github.com/mbedmicro/mbed/commit/dba523f83fe09b7fce11fc1299dd1216e9776359/
Update of I2C, SPI, SLEEP for NUCLEO_F103RB and L152RE
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/misc.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/misc.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file misc.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides all the miscellaneous firmware functions (add-on * to CMSIS functions). ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/misc.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/misc.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file misc.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx.h Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx.h Thu Jan 30 12:15:05 2014 +0000
@@ -2,12 +2,12 @@
******************************************************************************
* @file stm32l1xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32L1xx High-density, Medium-density
- * and Medium-density Plus devices.
+ * definitions and memory mapping for STM32L1xx High-density, Medium-density,
+ * Medium-density and XL-density Plus devices.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
@@ -26,7 +26,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -66,23 +66,27 @@
application
*/
-#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
/* #define STM32L1XX_MD */ /*!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
- STM32L151xBxx, STM32L152x6xx, STM32L152x8xx and STM32L152xBxx.
+ STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx,
+ STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA,
+ STM32L152x8xxA and STM32L152xBxxA.
- Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
STM32L100x8xx and STM32L100xBxx. */
-//#define STM32L1XX_MDP /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx
-// - Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */
-
-#define STM32L1XX_HD /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
+/* #define STM32L1XX_MDP */ /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx
+ - Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */
+
+/* #define STM32L1XX_HD */ /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
+
+#define STM32L1XX_XL /*!< Ultra Low Power XL-density devices: STM32L151xExx, STM32L152xExx and STM32L162xExx */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
-#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
#error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
#endif
@@ -111,7 +115,7 @@
Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
#endif
/**
@@ -119,7 +123,7 @@
Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
-#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
#endif
#if !defined (HSI_VALUE)
@@ -139,10 +143,10 @@
#endif
/**
- * @brief STM32L1xx Standard Peripheral Library version number V1.2.0
+ * @brief STM32L1xx Standard Peripheral Library version number V1.3.0
*/
#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
@@ -225,6 +229,7 @@
RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
+
#ifdef STM32L1XX_MD
TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
#endif /* STM32L1XX_MD */
@@ -257,6 +262,21 @@
AES_IRQn = 55, /*!< AES global Interrupt */
COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
#endif /* STM32L1XX_HD */
+
+#ifdef STM32L1XX_XL
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 48, /*!< UART4 global Interrupt */
+ UART5_IRQn = 49, /*!< UART5 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif /* STM32L1XX_XL */
} IRQn_Type;
/**
@@ -557,8 +577,10 @@
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+#if defined (STM32L1XX_HD) || defined (STM32L1XX_XL)
__IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
uint16_t RESERVED3; /*!< Reserved, 0x2A */
+#endif
} GPIO_TypeDef;
/**
@@ -663,13 +685,28 @@
typedef struct
{
- __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
- __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
- __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
- __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
- __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
- __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
- __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x04 */
+ __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x08 */
+ __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x0C */
+ __IO uint32_t HYSCR1; /*!< RI hysteresis control register 1, Address offset: 0x10 */
+ __IO uint32_t HYSCR2; /*!< RI Hysteresis control register 2, Address offset: 0x14 */
+ __IO uint32_t HYSCR3; /*!< RI Hysteresis control register 3, Address offset: 0x18 */
+ __IO uint32_t HYSCR4; /*!< RI Hysteresis control register 4, Address offset: 0x1C */
+ __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x20 */
+ __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x24 */
+ __IO uint32_t CICR1; /*!< RI Channel identification for capture register 1, Address offset: 0x28 */
+ __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x2C */
+ __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x30 */
+ __IO uint32_t CICR2; /*!< RI Channel identification for capture register 2, Address offset: 0x34 */
+ __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x38 */
+ __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x3C */
+ __IO uint32_t CICR3; /*!< RI Channel identification for capture register3 , Address offset: 0x40 */
+ __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x44 */
+ __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x48 */
+ __IO uint32_t CICR4; /*!< RI Channel identification for capture register 4, Address offset: 0x4C */
+ __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x50 */
+ __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x54 */
+ __IO uint32_t CICR5; /*!< RI Channel identification for capture register 5, Address offset: 0x58 */
} RI_TypeDef;
/**
@@ -4885,6 +4922,291 @@
#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+/******************** Bit definition for RI_ASMR1 register ********************/
+#define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A analog switch mode selection */
+#define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR1 register ********************/
+#define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel masking */
+#define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR1 register ********************/
+#define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel identification for capture */
+#define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR2 register ********************/
+#define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B analog switch mode selection */
+#define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR2 register ********************/
+#define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel masking */
+#define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR2 register ********************/
+#define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel identification for capture */
+#define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR3 register ********************/
+#define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C analog switch mode selection */
+#define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR3 register ********************/
+#define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel masking */
+#define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR3 register ********************/
+#define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel identification for capture */
+#define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR4 register ********************/
+#define RI_ASMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F analog switch mode selection */
+#define RI_ASMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR4 register ********************/
+#define RI_CMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel masking */
+#define RI_CMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR4 register ********************/
+#define RI_CICR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel identification for capture */
+#define RI_CICR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR5 register ********************/
+#define RI_ASMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G analog switch mode selection */
+#define RI_ASMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR5 register ********************/
+#define RI_CMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel masking */
+#define RI_CMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR5 register ********************/
+#define RI_CICR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel identification for capture */
+#define RI_CICR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
/******************************************************************************/
/* */
/* Timers (TIM) */
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_adc.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_adc.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_adc.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and Configuration @@ -65,7 +65,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_adc.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_adc.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_adc.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_aes.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_aes.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_aes.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the AES peripheral: * + Configuration @@ -52,7 +52,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_aes.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_aes.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_aes.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the AES firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_aes_util.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_aes_util.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_aes_util.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides high level functions to encrypt and decrypt an * input message using AES in ECB/CBC/CTR modes. * @@ -30,7 +30,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_comp.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_comp.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_comp.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the comparators (COMP1 and COMP2) peripheral: * + Comparators configuration @@ -56,7 +56,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_comp.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_comp.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_comp.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the COMP firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_crc.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_crc.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_crc.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides all the CRC firmware functions. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_crc.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_crc.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_crc.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dac.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dac.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_dac.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Digital-to-Analog Converter (DAC) peripheral: * + DAC channels configuration: trigger, output buffer, data format @@ -83,7 +83,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dac.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dac.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_dac.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dbgmcu.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dbgmcu.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_dbgmcu.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides all the DBGMCU firmware functions. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dbgmcu.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dbgmcu.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_dbgmcu.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the DBGMCU * firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dma.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dma.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_dma.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Direct Memory Access controller (DMA): * + Initialization and Configuration @@ -52,7 +52,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dma.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dma.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_dma.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_exti.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_exti.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_exti.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the EXTI peripheral: * + Initialization and Configuration @@ -45,7 +45,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_exti.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_exti.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_exti.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_flash.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_flash.c Thu Jan 30 12:15:05 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_flash.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file provides all the Flash firmware functions. These functions
* can be executed from Internal FLASH or Internal SRAM memories.
* The functions that should be called from SRAM are defined inside
@@ -75,7 +75,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -497,11 +497,11 @@
/**
* @brief Erase a byte in data memory.
* @param Address: specifies the address to be erased.
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
- * density devices.
+ * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and
+ * STM32L1XX_XL devices.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @retval FLASH Status: The returned value can be:
@@ -530,11 +530,11 @@
/**
* @brief Erase a halfword in data memory.
* @param Address: specifies the address to be erased.
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
- * density devices.
+ * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and
+ * STM32L1XX_XL devices.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @retval FLASH Status: The returned value can be:
@@ -567,7 +567,7 @@
* if the address to load is the start address of a word (multiple of a word).
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @retval FLASH Status: The returned value can be:
@@ -597,7 +597,7 @@
* @brief Write a Byte at a specified address in data memory.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @param Address: specifies the address to be written.
@@ -609,7 +609,7 @@
FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
uint32_t tmp = 0, tmpaddr = 0;
#endif
@@ -624,7 +624,7 @@
/* Clear the FTDW bit */
FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
if(Data != (uint8_t)0x00)
{
/* If the previous operation is completed, proceed to write the new Data */
@@ -642,7 +642,7 @@
status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
}
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL)
/* If the previous operation is completed, proceed to write the new Data */
*(__IO uint8_t *)Address = Data;
@@ -658,7 +658,7 @@
* @brief Writes a half word at a specified address in data memory.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @param Address: specifies the address to be written.
@@ -670,7 +670,7 @@
FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
uint32_t tmp = 0, tmpaddr = 0;
#endif
@@ -685,7 +685,7 @@
/* Clear the FTDW bit */
FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
if(Data != (uint16_t)0x0000)
{
/* If the previous operation is completed, proceed to write the new data */
@@ -711,7 +711,7 @@
DATA_EEPROM_FastProgramByte(Address + 1, 0x00);
}
}
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL)
/* If the previous operation is completed, proceed to write the new data */
*(__IO uint16_t *)Address = Data;
@@ -727,7 +727,7 @@
* @brief Programs a word at a specified address in data memory.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to the data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @param Address: specifies the address to be written.
@@ -765,7 +765,7 @@
* @brief Write a Byte at a specified address in data memory without erase.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before
@@ -778,7 +778,7 @@
FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
uint32_t tmp = 0, tmpaddr = 0;
#endif
@@ -790,7 +790,7 @@
if(status == FLASH_COMPLETE)
{
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
if(Data != (uint8_t) 0x00)
{
*(__IO uint8_t *)Address = Data;
@@ -808,7 +808,7 @@
status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
}
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL)
*(__IO uint8_t *)Address = Data;
/* Wait for last operation to be completed */
@@ -823,7 +823,7 @@
* @brief Writes a half word at a specified address in data memory without erase.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before
@@ -836,7 +836,7 @@
FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
uint32_t tmp = 0, tmpaddr = 0;
#endif
@@ -848,7 +848,7 @@
if(status == FLASH_COMPLETE)
{
-#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_XL)
if(Data != (uint16_t)0x0000)
{
*(__IO uint16_t *)Address = Data;
@@ -873,7 +873,7 @@
DATA_EEPROM_FastProgramByte(Address + 1, 0x00);
}
}
-#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP) || defined (STM32L1XX_XL)
*(__IO uint16_t *)Address = Data;
/* Wait for last operation to be completed */
@@ -888,7 +888,7 @@
* @brief Programs a word at a specified address in data memory without erase.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
- * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * Call the DATA_EEPROM_Lock() to disable the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before
@@ -1087,8 +1087,8 @@
/**
* @brief Write protects the desired pages of the second 128KB of the Flash.
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
- * density devices.
+ * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and
+ * STM32L1XX_XL devices.
* @param OB_WRP1: specifies the address of the pages to be write protected.
* This parameter can be:
* @arg value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023
@@ -1146,7 +1146,7 @@
/**
* @brief Write protects the desired pages of the third 128KB of the Flash.
- * @note This function can be used only for STM32L1XX_HD density devices.
+ * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices.
* @param OB_WRP2: specifies the address of the pages to be write protected.
* This parameter can be:
* @arg value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535
@@ -1509,7 +1509,7 @@
/**
* @brief Configures to boot from Bank1 or Bank2.
- * @note This function can be used only for STM32L1XX_HD density devices.
+ * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices.
* @param OB_BOOT: select the FLASH Bank to boot from.
* This parameter can be one of the following values:
* @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash
@@ -1580,8 +1580,8 @@
/**
* @brief Returns the FLASH Write Protection Option Bytes value.
- * @note This function can be used only for STM32L1XX_HD and STM32L1XX_MDP
- * density devices.
+ * @note This function can be used only for STM32L1XX_HD, STM32L1XX_MDP and
+ * STM32L1XX_XL devices.
* @param None
* @retval The FLASH Write Protection Option Bytes value.
*/
@@ -1593,7 +1593,7 @@
/**
* @brief Returns the FLASH Write Protection Option Bytes value.
- * @note This function can be used only for STM32L1XX_HD density devices.
+ * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices.
* @param None
* @retval The FLASH Write Protection Option Bytes value.
*/
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_flash.h Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_flash.h Thu Jan 30 12:15:05 2014 +0000
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l1xx_flash.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -92,8 +92,8 @@
* @{
*/
-#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))
+#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08083FFF))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF))
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_flash_ramfunc.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_flash_ramfunc.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_flash_ramfunc.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides all the Flash firmware functions which should be * executed from the internal SRAM. This file should be placed in * internal SRAM. @@ -39,7 +39,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. @@ -140,17 +140,19 @@ /** * @brief Erases a specified 2 page in program memory in parallel. - * @note This function can be used only for STM32L1XX_HD density devices. + * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices. * To correctly run this function, the FLASH_Unlock() function * must be called before. * Call the FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation). * @param Page_Address1: The page address in program memory to be erased in - * the first Bank (BANK1). This parameter should be between 0x08000000 - * and 0x0802FF00. + * the first Bank (BANK1). This parameter should be: + * - between 0x08000000 and 0x0802FF00 for STM32L1XX_HD devices + * - between 0x08000000 and 0x0803FF00 for STM32L1XX_XL devices * @param Page_Address2: The page address in program memory to be erased in - * the second Bank (BANK2). This parameter should be between 0x08030000 - * and 0x0805FF00. + * the second Bank (BANK2). This parameter should be: + * - between 0x08030000 and 0x0805FF00 for STM32L1XX_HD devices + * - between 0x08040000 and 0x0807FF00 for STM32L1XX_XL devices * @note A Page is erased in the Program memory only if the address to load * is the start address of a page (multiple of 256 bytes). * @retval FLASH Status: The returned value can be: @@ -262,14 +264,18 @@ /** * @brief Programs 2 half page in program memory in parallel. * @param Address1: specifies the first address to be written in the first bank - * (BANK1). This parameter should be between 0x08000000 and 0x0802FF80. + * (BANK1).This parameter should be: + * - between 0x08000000 and 0x0802FF80 for STM32L1XX_HD devices + * - between 0x08000000 and 0x0803FF80 for STM32L1XX_XL devices * @param pBuffer1: pointer to the buffer containing the data to be written * to the first half page in the first bank. * @param Address2: specifies the second address to be written in the second bank - * (BANK2). This parameter should be between 0x08030000 and 0x0805FF80. + * (BANK2). This parameter should be: + * - between 0x08030000 and 0x0805FF80 for STM32L1XX_HD devices + * - between 0x08040000 and 0x0807FF80 for STM32L1XX_XL devices * @param pBuffer2: pointer to the buffer containing the data to be written * to the second half page in the second bank. - * @note This function can be used only for STM32L1XX_HD density devices. + * @note This function can be used only for STM32L1XX_HD and STM32L1XX_XL devices. * @note To correctly run this function, the FLASH_Unlock() function * must be called before. * Call the FLASH_Lock() to disable the flash memory access
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_fsmc.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the FSMC peripheral: * + Initialization @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_fsmc.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_gpio.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_gpio.c Thu Jan 30 12:15:05 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_gpio.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration
@@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -179,6 +179,7 @@
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+ uint32_t tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
@@ -197,30 +198,42 @@
if (currentpin == pos)
{
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+ /* Use temporary variable to update MODER register configuration, to avoid
+ unexpected transition in the GPIO pin configuration. */
+ tmpreg = GPIOx->MODER;
+ tmpreg &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+ tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+ GPIOx->MODER = tmpreg;
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
{
/* Check Speed mode parameters */
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+ /* Use temporary variable to update OSPEEDR register configuration, to avoid
+ unexpected transition in the GPIO pin configuration. */
+ tmpreg = GPIOx->OSPEEDR;
+ tmpreg &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+ tmpreg |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+ GPIOx->OSPEEDR = tmpreg;
/*Check Output mode parameters */
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
- /* Output mode configuration */
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+ /* Use temporary variable to update OTYPER register configuration, to avoid
+ unexpected transition in the GPIO pin configuration. */
+ tmpreg = GPIOx->OTYPER;
+ tmpreg &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+ tmpreg |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+ GPIOx->OTYPER = tmpreg;
}
- /* Pull-up Pull down resistor configuration */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+ /* Use temporary variable to update PUPDR register configuration, to avoid
+ unexpected transition in the GPIO pin configuration. */
+ tmpreg = GPIOx->PUPDR;
+ tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+ tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+ GPIOx->PUPDR = tmpreg;
}
}
}
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_gpio.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_gpio.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_gpio.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the GPIO * firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_i2c.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_i2c.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_i2c.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Inter-integrated circuit (I2C) * + Initialization and Configuration @@ -57,7 +57,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_i2c.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_i2c.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_i2c.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_iwdg.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_iwdg.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_iwdg.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Independent watchdog (IWDG) peripheral: * + Prescaler and Counter configuration @@ -64,7 +64,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_iwdg.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_iwdg.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_iwdg.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_lcd.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_lcd.c Thu Jan 30 12:15:05 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_lcd.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the LCD controller (LCD) peripheral:
* + Initialization and configuration
@@ -61,7 +61,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -129,6 +129,8 @@
#define BLINK_MASK ((uint32_t)0xFFFC1FFF) /* LCD BLINK Mask */
#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF) /* LCD CONTRAST Mask */
+#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -236,10 +238,15 @@
*/
void LCD_WaitForSynchro(void)
{
+ uint32_t synchrocounter = 0;
+ uint32_t synchrostatus = 0x00;
+
/* Loop until FCRSF flag is set */
- while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)
+ do
{
- }
+ synchrostatus = LCD->SR & LCD_FLAG_FCRSF;
+ synchrocounter++;
+ } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
}
/**
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_lcd.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_lcd.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_lcd.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the LCD firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_opamp.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_opamp.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_opamp.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the operational amplifiers (opamp) peripheral: * + Initialization and configuration @@ -44,7 +44,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. @@ -276,10 +276,10 @@ assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming)); /* Reset the OPAMP_OTR range bit */ - OPAMP->CSR &= (~(uint32_t) (OPAMP_OTR_OT_USER)); + OPAMP->OTR &= (~(uint32_t) (OPAMP_OTR_OT_USER)); /* Select the OPAMP offset trimming */ - OPAMP->CSR |= OPAMP_Trimming; + OPAMP->OTR |= OPAMP_Trimming; }
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_opamp.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_opamp.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_opamp.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the operational * amplifiers (opamp) firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_pwr.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_pwr.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_pwr.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + RTC Domain Access @@ -17,7 +17,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_pwr.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_pwr.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_pwr.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_rcc.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: * + Internal/external clocks, PLL, CSS and MCO configuration @@ -38,7 +38,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.h Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.h Thu Jan 30 12:15:05 2014 +0000
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l1xx_rcc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file contains all the functions prototypes for the RCC
* firmware library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -404,7 +404,7 @@
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LSECSS))
+ ((FLAG) == RCC_FLAG_OBLRST)|| ((FLAG) == RCC_FLAG_LSECSS))
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rtc.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rtc.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_rtc.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: * + Initialization @@ -204,7 +204,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. @@ -851,8 +851,6 @@ /** * @brief Gets the RTC current Calendar Subseconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. * @param None * @retval RTC current Calendar Subseconds value. */
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rtc.h Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_rtc.h Thu Jan 30 12:15:05 2014 +0000
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l1xx_rtc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -744,8 +744,8 @@
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
- ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
- ((FLAG) == RTC_FLAG_SHPF))
+ ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+ ((FLAG) == RTC_FLAG_SHPF)|| ((FLAG) == RTC_FLAG_INITS))
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
/**
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_sdio.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_sdio.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_sdio.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the SDIO peripheral: * + Initialization @@ -109,7 +109,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_sdio.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_sdio.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_sdio.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_spi.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_spi.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_spi.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Serial peripheral interface (SPI): * + Initialization and Configuration @@ -75,7 +75,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_spi.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_spi.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_spi.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the SPI * firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_syscfg.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_syscfg.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_syscfg.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the SYSCFG and RI peripherals: * + SYSCFG Initialization and Configuration @@ -49,7 +49,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_syscfg.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_syscfg.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_syscfg.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the SYSCFG * firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_tim.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_tim.c Thu Jan 30 12:15:05 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_tim.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the TIM peripheral:
* + TimeBase management
@@ -89,7 +89,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -2540,7 +2540,9 @@
/**
* @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 2, 3, 4 or 5 to select the TIM peripheral.
+ * @param TIMx: where x can be 2, 3, 4, 5 or 9 to select the TIM peripheral.
+ * @note TIM9 is supporting Encoder Interface only in STM32L1XX_MDP, STM32L1XX_HD
+ * and STM32L1XX_XL devices.
* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
* This parameter can be one of the following values:
* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
@@ -2565,7 +2567,7 @@
uint16_t tmpccer = 0;
/* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_LIST7_PERIPH(TIMx));
assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_tim.h Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_tim.h Thu Jan 30 12:15:05 2014 +0000
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l1xx_tim.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 22-February-2013
+ * @version V1.3.0
+ * @date 31-January-2014
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -175,7 +175,12 @@
((PERIPH) == TIM10) || \
((PERIPH) == TIM11))
-
+/* LIST3: TIM2, TIM3, TIM4, TIM5 and TIM9 */
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM9))
/** @defgroup TIM_Output_Compare_and_PWM_modes
* @{
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_usart.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_usart.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_usart.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Universal synchronous asynchronous receiver * transmitter (USART): @@ -58,7 +58,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_usart.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_usart.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_usart.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the USART * firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_wwdg.c Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_wwdg.c Thu Jan 30 12:15:05 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_wwdg.c * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file provides firmware functions to manage the following * functionalities of the Window watchdog (WWDG) peripheral: * + Prescaler, Refresh window and Counter configuration @@ -65,7 +65,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_wwdg.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_wwdg.h Thu Jan 30 12:15:05 2014 +0000 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_wwdg.h * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 + * @version V1.3.0 + * @date 31-January-2014 * @brief This file contains all the functions prototypes for the WWDG * firmware library. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralNames.h Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralNames.h Thu Jan 30 12:15:05 2014 +0000
@@ -65,8 +65,9 @@
} I2CName;
typedef enum {
- PWM_2 = (int)TIM2_BASE,
- PWM_3 = (int)TIM3_BASE
+ TIM_1 = (int)TIM1_BASE,
+ TIM_14 = (int)TIM14_BASE,
+ TIM_16 = (int)TIM16_BASE
} PWMName;
#ifdef __cplusplus
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/device.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/device.h Thu Jan 30 12:15:05 2014 +0000 @@ -41,7 +41,7 @@ #define DEVICE_SERIAL 1 -#define DEVICE_I2C 0 +#define DEVICE_I2C 1 #define DEVICE_I2CSLAVE 0 #define DEVICE_SPI 0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/i2c_api.c Thu Jan 30 12:15:05 2014 +0000
@@ -0,0 +1,327 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/* Timeout values for flags and events waiting loops. These timeouts are
+ not based on accurate values, they just guarantee that the application will
+ not remain stuck if the I2C communication is corrupted. */
+#define FLAG_TIMEOUT ((int)0x1000)
+#define LONG_TIMEOUT ((int)0x8000)
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_NOPULL, GPIO_AF_1)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_NOPULL, GPIO_AF_1)},
+ {NC, NC, 0}
+};
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ // Determine the I2C to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+
+ obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+
+ if (obj->i2c == (I2CName)NC) {
+ error("I2C pin mapping failed");
+ }
+
+ // Enable I2C clock
+ if (obj->i2c == I2C_1) {
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
+ }
+ //if (obj->i2c == I2C_2) {
+ // RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
+ //}
+
+ // Configure I2C pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrain);
+ pin_mode(scl, OpenDrain);
+
+ // Reset to clear pending flags if any
+ i2c_reset(obj);
+
+ // I2C configuration
+ i2c_frequency(obj, 100000); // 100 kHz per default
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2C_InitTypeDef I2C_InitStructure;
+ uint32_t tim;
+
+ // Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235)
+ // with Rise time = 100ns and Fall time = 10ns
+ switch (hz) {
+ case 100000:
+ tim = 0x00201D2B; // Standard mode
+ break;
+ case 200000:
+ tim = 0x0010021E; // Fast mode
+ break;
+ case 400000:
+ tim = 0x0010020A; // Fast mode
+ break;
+ default:
+ error("Only 100kHz, 200kHz and 400kHz I2C frequencies are supported.");
+ break;
+ }
+
+ // I2C configuration
+ I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+ I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+ I2C_InitStructure.I2C_DigitalFilter = 0x00;
+ I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+ I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+ I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+ I2C_InitStructure.I2C_Timing = tim;
+ I2C_Init(i2c, &I2C_InitStructure);
+
+ I2C_Cmd(i2c, ENABLE);
+}
+
+inline int i2c_start(i2c_t *obj) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout = LONG_TIMEOUT;
+
+ // Test BUSY Flag
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) != RESET)
+ {
+ if ((timeout--) == 0) return 0;
+ }
+
+ I2C_GenerateSTART(i2c, ENABLE);
+
+ return 0;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+
+ I2C_GenerateSTOP(i2c, ENABLE);
+
+ return 0;
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+ int value;
+
+ if (length == 0) return 0;
+
+ // Configure slave address, nbytes, reload, end mode and start or stop generation
+ if (stop) {
+ I2C_TransferHandling(i2c, address, length, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+ }
+ else {
+ I2C_TransferHandling(i2c, address, length, I2C_Reload_Mode, I2C_Generate_Start_Read);
+ }
+
+ // Read all bytes
+ for (count = 0; count < length; count++) {
+ value = i2c_byte_read(obj, 0);
+ data[count] = (char)value;
+ }
+
+ if (stop) {
+ // Wait until STOPF flag is set
+ timeout = LONG_TIMEOUT;
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_STOPF) == RESET)
+ {
+ if ((timeout--) == 0) return 0;
+ }
+
+ // Clear STOPF flag
+ I2C_ClearFlag(i2c, I2C_ICR_STOPCF);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+
+ // Test BUSY Flag
+ //timeout = LONG_TIMEOUT;
+ //while (I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) != RESET)
+ //{
+ // if((timeout--) == 0) return 0;
+ //}
+
+ // Configure slave address, nbytes, reload, end mode and start or stop generation
+ if (stop) {
+ I2C_TransferHandling(i2c, address, length, I2C_AutoEnd_Mode, I2C_Generate_Start_Write);
+ }
+ else {
+ I2C_TransferHandling(i2c, address, length, I2C_Reload_Mode, I2C_Generate_Start_Write);
+ }
+
+ // Write all bytes
+ for (count = 0; count < length; count++) {
+ if (i2c_byte_write(obj, data[count]) != 1) {
+ i2c_stop(obj);
+ return 0;
+ }
+ }
+
+ if (stop) {
+ // Wait until STOPF flag is set
+ timeout = LONG_TIMEOUT;
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_STOPF) == RESET)
+ {
+ if ((timeout--) == 0) return 0;
+ }
+
+ // Clear STOPF flag
+ I2C_ClearFlag(i2c, I2C_ICR_STOPCF);
+ }
+
+ return count;
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint8_t data;
+ int timeout = FLAG_TIMEOUT;
+
+ // Wait until the byte is received
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_RXNE) == RESET) {
+ if ((timeout--) == 0) return 0;
+ }
+
+ data = I2C_ReceiveData(i2c);
+
+ return (int)data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ int timeout = FLAG_TIMEOUT;
+
+ // Wait until TXIS flag is set
+ timeout = LONG_TIMEOUT;
+ while (I2C_GetFlagStatus(i2c, I2C_ISR_TXIS) == RESET)
+ {
+ if ((timeout--) == 0) return 0;
+ }
+
+ I2C_SendData(i2c, (uint8_t)data);
+
+ // Wait until the byte is transmitted
+ //while (I2C_GetFlagStatus(i2c, I2C_ISR_TCR) == RESET) {
+ // if ((timeout--) == 0) return 0;
+ //}
+
+ return 1;
+}
+
+void i2c_reset(i2c_t *obj) {
+ if (obj->i2c == I2C_1) {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ }
+ //if (obj->i2c == I2C_2) {
+ // RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ // RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ //}
+}
+
+#if DEVICE_I2CSLAVE
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ uint16_t tmpreg;
+
+ // Get the old register value
+ tmpreg = i2c->OAR1;
+ // Reset address bits
+ tmpreg &= 0xFC00;
+ // Set new address
+ tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
+ // Store the new register value
+ i2c->OAR1 = tmpreg;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ // Nothing to do
+}
+
+// See I2CSlave.h
+#define NoData 0 // the slave has not been addressed
+#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral 2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+int i2c_slave_receive(i2c_t *obj) {
+ // TO BE DONE
+ return(0);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int count = 0;
+
+ // Read all bytes
+ for (count = 0; count < length; count++) {
+ data[count] = i2c_byte_read(obj, 0);
+ }
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+
+ // Write all bytes
+ for (count = 0; count < length; count++) {
+ i2c_byte_write(obj, data[count]);
+ }
+
+ return count;
+}
+
+
+#endif // DEVICE_I2CSLAVE
+
+#endif // DEVICE_I2C
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pinmap.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pinmap.c Thu Jan 30 12:15:05 2014 +0000
@@ -83,6 +83,12 @@
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Configure Alternate Function
+ // Warning: Must be done before the GPIO is initialized
+ if (afnum != 0xFF) {
+ GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
+ }
// Configure GPIO
GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
@@ -91,11 +97,6 @@
GPIO_InitStructure.GPIO_OType = (GPIOOType_TypeDef)otype;
GPIO_InitStructure.GPIO_PuPd = (GPIOPuPd_TypeDef)pupd;
GPIO_Init(gpio, &GPIO_InitStructure);
-
- // Configure Alternate Function
- if (afnum != 0xFF) {
- GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
- }
// *** TODO ***
// Disconnect JTAG-DP + SW-DP signals.
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c Thu Jan 30 12:15:05 2014 +0000
@@ -71,10 +71,10 @@
}
// Configure I2C pins
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(scl, OpenDrain);
pinmap_pinout(sda, PinMap_I2C_SDA);
- pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(sda, OpenDrain);
- pin_mode(scl, OpenDrain);
// Reset to clear pending flags if any
i2c_reset(obj);
@@ -88,6 +88,8 @@
I2C_InitTypeDef I2C_InitStructure;
if ((hz != 0) && (hz <= 400000)) {
+ I2C_DeInit(i2c);
+
// I2C configuration
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
@@ -95,8 +97,9 @@
I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_InitStructure.I2C_ClockSpeed = hz;
+ I2C_Init(i2c, &I2C_InitStructure);
+
I2C_Cmd(i2c, ENABLE);
- I2C_Init(i2c, &I2C_InitStructure);
}
}
@@ -113,9 +116,10 @@
timeout = FLAG_TIMEOUT;
//while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_MODE_SELECT) == ERROR) {
while (I2C_GetFlagStatus(i2c, I2C_FLAG_SB) == RESET) {
- if ((timeout--) == 0) {
- return 1;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 1;
+ }
}
return 0;
@@ -141,7 +145,8 @@
// Wait until the bus is not busy anymore
timeout = LONG_TIMEOUT;
while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) {
- if ((timeout--) == 0) {
+ timeout--;
+ if (timeout == 0) {
return 0;
}
}
@@ -155,9 +160,10 @@
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) == ERROR) {
- if ((timeout--) == 0) {
- return 0;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
// Read all bytes except last one
@@ -188,7 +194,8 @@
// Wait until the bus is not busy anymore
timeout = LONG_TIMEOUT;
while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) {
- if ((timeout--) == 0) {
+ timeout--;
+ if (timeout == 0) {
return 0;
}
}
@@ -202,9 +209,10 @@
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == ERROR) {
- if ((timeout--) == 0) {
- return 0;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
for (count = 0; count < length; count++) {
@@ -238,9 +246,10 @@
// Wait until the byte is received
timeout = FLAG_TIMEOUT;
while (I2C_GetFlagStatus(i2c, I2C_FLAG_RXNE) == RESET) {
- if ((timeout--) == 0) {
- return 0;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
data = I2C_ReceiveData(i2c);
@@ -259,7 +268,8 @@
//while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED) == ERROR) {
while ((I2C_GetFlagStatus(i2c, I2C_FLAG_TXE) == RESET) &&
(I2C_GetFlagStatus(i2c, I2C_FLAG_BTF) == RESET)) {
- if ((timeout--) == 0) {
+ timeout--;
+ if (timeout == 0) {
return 0;
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c Thu Jan 30 12:15:05 2014 +0000
@@ -90,20 +90,21 @@
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
gpio = (GPIO_TypeDef *)gpio_add;
-
+
// Enable AFIO clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
+
+ // Configure Alternate Function
+ // Warning: Must be done before the GPIO is initialized
+ if (afnum > 0) {
+ GPIO_PinRemapConfig(AF_mapping[afnum], ENABLE);
+ }
// Configure GPIO
GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(gpio, &GPIO_InitStructure);
-
- // Configure Alternate Function
- if (afnum > 0) {
- GPIO_PinRemapConfig(AF_mapping[afnum], ENABLE);
- }
// Disconnect JTAG-DP + SW-DP signals.
// Warning: Need to reconnect under reset
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/device.h Thu Jan 30 09:45:05 2014 +0000 +++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/device.h Thu Jan 30 12:15:05 2014 +0000 @@ -41,10 +41,10 @@ #define DEVICE_SERIAL 1 -#define DEVICE_I2C 0 +#define DEVICE_I2C 1 #define DEVICE_I2CSLAVE 0 -#define DEVICE_SPI 0 +#define DEVICE_SPI 1 #define DEVICE_SPISLAVE 0 #define DEVICE_RTC 1
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/i2c_api.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/i2c_api.c Thu Jan 30 12:15:05 2014 +0000
@@ -42,12 +42,12 @@
#define LONG_TIMEOUT ((int)0x8000)
static const PinMap PinMap_I2C_SDA[] = {
- {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1
+ {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_I2C1)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
- {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1
+ {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_I2C1)},
{NC, NC, 0}
};
@@ -71,10 +71,10 @@
}
// Configure I2C pins
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(scl, OpenDrain);
pinmap_pinout(sda, PinMap_I2C_SDA);
- pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(sda, OpenDrain);
- pin_mode(scl, OpenDrain);
// Reset to clear pending flags if any
i2c_reset(obj);
@@ -88,6 +88,8 @@
I2C_InitTypeDef I2C_InitStructure;
if ((hz != 0) && (hz <= 400000)) {
+ I2C_DeInit(i2c);
+
// I2C configuration
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
@@ -95,8 +97,9 @@
I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_InitStructure.I2C_ClockSpeed = hz;
+ I2C_Init(i2c, &I2C_InitStructure);
+
I2C_Cmd(i2c, ENABLE);
- I2C_Init(i2c, &I2C_InitStructure);
}
}
@@ -113,9 +116,10 @@
timeout = FLAG_TIMEOUT;
//while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_MODE_SELECT) == ERROR) {
while (I2C_GetFlagStatus(i2c, I2C_FLAG_SB) == RESET) {
- if ((timeout--) == 0) {
- return 1;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 1;
+ }
}
return 0;
@@ -141,7 +145,8 @@
// Wait until the bus is not busy anymore
timeout = LONG_TIMEOUT;
while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) {
- if ((timeout--) == 0) {
+ timeout--;
+ if (timeout == 0) {
return 0;
}
}
@@ -155,9 +160,10 @@
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) == ERROR) {
- if ((timeout--) == 0) {
- return 0;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
// Read all bytes except last one
@@ -188,7 +194,8 @@
// Wait until the bus is not busy anymore
timeout = LONG_TIMEOUT;
while (I2C_GetFlagStatus(i2c, I2C_FLAG_BUSY) == SET) {
- if ((timeout--) == 0) {
+ timeout--;
+ if (timeout == 0) {
return 0;
}
}
@@ -202,9 +209,10 @@
// Wait address is acknowledged
timeout = FLAG_TIMEOUT;
while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == ERROR) {
- if ((timeout--) == 0) {
- return 0;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
for (count = 0; count < length; count++) {
@@ -238,9 +246,10 @@
// Wait until the byte is received
timeout = FLAG_TIMEOUT;
while (I2C_GetFlagStatus(i2c, I2C_FLAG_RXNE) == RESET) {
- if ((timeout--) == 0) {
- return 0;
- }
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
data = I2C_ReceiveData(i2c);
@@ -259,7 +268,8 @@
//while (I2C_CheckEvent(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED) == ERROR) {
while ((I2C_GetFlagStatus(i2c, I2C_FLAG_TXE) == RESET) &&
(I2C_GetFlagStatus(i2c, I2C_FLAG_BTF) == RESET)) {
- if ((timeout--) == 0) {
+ timeout--;
+ if (timeout == 0) {
return 0;
}
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c Thu Jan 30 12:15:05 2014 +0000
@@ -83,7 +83,13 @@
// Enable GPIO clock
uint32_t gpio_add = Set_GPIO_Clock(port_index);
gpio = (GPIO_TypeDef *)gpio_add;
-
+
+ // Configure Alternate Function
+ // Warning: Must be done before the GPIO is initialized
+ if (afnum != 0xFF) {
+ GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
+ }
+
// Configure GPIO
GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode;
@@ -91,11 +97,6 @@
GPIO_InitStructure.GPIO_OType = (GPIOOType_TypeDef)otype;
GPIO_InitStructure.GPIO_PuPd = (GPIOPuPd_TypeDef)pupd;
GPIO_Init(gpio, &GPIO_InitStructure);
-
- // Configure Alternate Function
- if (afnum != 0xFF) {
- GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
- }
// *** TODO ***
// Disconnect JTAG-DP + SW-DP signals.
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/sleep.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/sleep.c Thu Jan 30 12:15:05 2014 +0000
@@ -30,17 +30,97 @@
#include "sleep_api.h"
#include "cmsis.h"
+static void SetSysClock_HSI(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSI */
+ RCC->CR |= ((uint32_t)RCC_CR_HSION);
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC->CR & RCC_CR_HSIRDY;
+ } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+ {
+ HSIStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSIStatus = (uint32_t)0x00;
+ }
+
+ if (HSIStatus == (uint32_t)0x01)
+ {
+ /* Flash 0 wait state */
+ FLASH->ACR &= ~FLASH_ACR_LATENCY;
+
+ /* Disable Prefetch Buffer */
+ FLASH->ACR &= ~FLASH_ACR_PRFTEN;
+
+ /* Disable 64-bit access */
+ FLASH->ACR &= ~FLASH_ACR_ACC64;
+
+ /* Power enable */
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+ /* Select the Voltage Range 1 (1.8 V) */
+ PWR->CR = PWR_CR_VOS_0;
+
+ /* Wait Until the Voltage Regulator is ready */
+ while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+ {
+ }
+
+ /* HCLK = SYSCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+ /* PCLK2 = HCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSI as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
+
+ /* Wait till HSI is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)
+ {
+ }
+ }
+ else
+ {
+ /* If HSI fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+// MCU SLEEP mode
void sleep(void)
{
- SCB->SCR = 0; // Normal sleep mode for ARM core
- __WFI();
+ // Enable PWR clock
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+ // Request to enter SLEEP mode with regulator ON
+ PWR_EnterSleepMode(PWR_Regulator_ON, PWR_SLEEPEntry_WFI);
}
+// MCU STOP mode (Regulator in LP mode, LSI, HSI and HSE OFF)
void deepsleep(void)
{
// Enable PWR clock
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
- // Request to enter STOP mode with regulator in low power mode
+ // Enable Ultra low power mode
+ PWR_UltraLowPowerCmd(ENABLE);
+
+ // Enter Stop Mode
PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
+
+ // After wake-up from STOP reconfigure the system clock (HSI)
+ SetSysClock_HSI();
+
}
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/spi_api.c Thu Jan 30 09:45:05 2014 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/spi_api.c Thu Jan 30 12:15:05 2014 +0000
@@ -37,28 +37,27 @@
#include "error.h"
static const PinMap PinMap_SPI_MOSI[] = {
- {PA_7, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
- {PB_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap
+ {PA_7, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
+ {PA_12, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)}, // REMAP
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
- {PA_6, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
- {PB_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap
+ {PA_6, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
+ {PA_11, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)}, // REMAP
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SCLK[] = {
- {PA_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
- {PB_3, SPI_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 1)}, // Remap
+ {PA_5, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)}, // REMAP
{NC, NC, 0}
};
// Only used in Slave mode
static const PinMap PinMap_SPI_SSEL[] = {
- {PB_6, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, // Generic IO, not real H/W NSS pin
- //{PA_4, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)},
- //{PA_15, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 1)}, // Remap
+ {PA_4, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)},
+ {PA_15, SPI_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_SPI1)}, // REMAP
{NC, NC, 0}
};