mbed-src-test

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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c@590:0835b0fc9a03, 2015-07-14 (annotated)

Committer:: SteveKim
Date:: Tue Jul 14 10:20:51 2015 +0000
Revision:: 590:0835b0fc9a03
Parent:: 489:119543c9f674

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	489:119543c9f674	1	/**
mbed_official	489:119543c9f674	2	******************************************************************************
mbed_official	489:119543c9f674	3	* @file stm32f1xx_hal_spi.c
mbed_official	489:119543c9f674	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.0.0
mbed_official	489:119543c9f674	6	* @date 15-December-2014
mbed_official	489:119543c9f674	7	* @brief SPI HAL module driver.
mbed_official	489:119543c9f674	8	*
mbed_official	489:119543c9f674	9	* This file provides firmware functions to manage the following
mbed_official	489:119543c9f674	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official	489:119543c9f674	11	* + Initialization and de-initialization functions
mbed_official	489:119543c9f674	12	* + IO operation functions
mbed_official	489:119543c9f674	13	* + Peripheral Control functions
mbed_official	489:119543c9f674	14	* + Peripheral State functions
mbed_official	489:119543c9f674	15	@verbatim
mbed_official	489:119543c9f674	16	==============================================================================
mbed_official	489:119543c9f674	17	##### How to use this driver #####
mbed_official	489:119543c9f674	18	==============================================================================
mbed_official	489:119543c9f674	19	[..]
mbed_official	489:119543c9f674	20	The SPI HAL driver can be used as follows:
mbed_official	489:119543c9f674	21
mbed_official	489:119543c9f674	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	489:119543c9f674	23	SPI_HandleTypeDef hspi;
mbed_official	489:119543c9f674	24
mbed_official	489:119543c9f674	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
mbed_official	489:119543c9f674	26	(##) Enable the SPIx interface clock
mbed_official	489:119543c9f674	27	(##) SPI pins configuration
mbed_official	489:119543c9f674	28	(+++) Enable the clock for the SPI GPIOs
mbed_official	489:119543c9f674	29	(+++) Configure these SPI pins as alternate function push-pull
mbed_official	489:119543c9f674	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	489:119543c9f674	31	(+++) Configure the SPIx interrupt priority
mbed_official	489:119543c9f674	32	(+++) Enable the NVIC SPI IRQ handle
mbed_official	489:119543c9f674	33	(##) DMA Configuration if you need to use DMA process
mbed_official	489:119543c9f674	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
mbed_official	489:119543c9f674	35	(+++) Enable the DMAx clock
mbed_official	489:119543c9f674	36	(+++) Configure the DMA handle parameters
mbed_official	489:119543c9f674	37	(+++) Configure the DMA Tx or Rx Channel
mbed_official	489:119543c9f674	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
mbed_official	489:119543c9f674	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
mbed_official	489:119543c9f674	40
mbed_official	489:119543c9f674	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official	489:119543c9f674	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	489:119543c9f674	43
mbed_official	489:119543c9f674	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	489:119543c9f674	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	489:119543c9f674	46	by calling the customed HAL_SPI_MspInit() API.
mbed_official	489:119543c9f674	47	[..]
mbed_official	489:119543c9f674	48	Circular mode restriction:
mbed_official	489:119543c9f674	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
mbed_official	489:119543c9f674	50	(##) Master 2Lines RxOnly
mbed_official	489:119543c9f674	51	(##) Master 1Line Rx
mbed_official	489:119543c9f674	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
mbed_official	489:119543c9f674	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
mbed_official	489:119543c9f674	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
mbed_official	489:119543c9f674	55
mbed_official	489:119543c9f674	56	[..]
mbed_official	489:119543c9f674	57	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
mbed_official	489:119543c9f674	58	the following table resume the max SPI frequency reached with data size 8bits/16bits,
mbed_official	489:119543c9f674	59	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
mbed_official	489:119543c9f674	60
mbed_official	489:119543c9f674	61	For 8 bits SPI data size transfers :
mbed_official	489:119543c9f674	62	+--------------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	63	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
mbed_official	489:119543c9f674	64	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
mbed_official	489:119543c9f674	65	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
mbed_official	489:119543c9f674	66	\|==================================================================================================\|
mbed_official	489:119543c9f674	67	\| T \| Polling \| fPCLK/8 \| fPCLK/8 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	68	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	69	\| / \| Interrupt \| fPCLK/32 \| fPCLK/32 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	70	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	71	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	72	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
mbed_official	489:119543c9f674	73	\| \| Polling \| fPCLK/4 \| fPCLK/8 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/8 \|
mbed_official	489:119543c9f674	74	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	75	\| R \| Interrupt \| fPCLK/32 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \|
mbed_official	489:119543c9f674	76	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	77	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/2 \|
mbed_official	489:119543c9f674	78	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
mbed_official	489:119543c9f674	79	\| \| Polling \| fPCLK/4 \| fPCLK/4 \| NA \| NA \| fPCLK/4 \| fPCLK/64 \|
mbed_official	489:119543c9f674	80	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	81	\| T \| Interrupt \| fPCLK/8 \| fPCLK/16 \| NA \| NA \| fPCLK/8 \| fPCLK/128 \|
mbed_official	489:119543c9f674	82	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	83	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
mbed_official	489:119543c9f674	84	+--------------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	85
mbed_official	489:119543c9f674	86	For 16 bits SPI data size transfers :
mbed_official	489:119543c9f674	87	+--------------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	88	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
mbed_official	489:119543c9f674	89	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
mbed_official	489:119543c9f674	90	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
mbed_official	489:119543c9f674	91	\|==================================================================================================\|
mbed_official	489:119543c9f674	92	\| T \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	93	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	94	\| / \| Interrupt \| fPCLK/16 \| fPCLK/16 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	95	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	96	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	97	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
mbed_official	489:119543c9f674	98	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| fPCLK/64 \| fPCLK/8 \| fPCLK/64 \| fPCLK/4 \|
mbed_official	489:119543c9f674	99	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	100	\| R \| Interrupt \| fPCLK/16 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \|
mbed_official	489:119543c9f674	101	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	102	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/2 \|
mbed_official	489:119543c9f674	103	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
mbed_official	489:119543c9f674	104	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
mbed_official	489:119543c9f674	105	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	106	\| T \| Interrupt \| fPCLK/4 \| fPCLK/8 \| NA \| NA \| fPCLK/4 \| fPCLK/256 \|
mbed_official	489:119543c9f674	107	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
mbed_official	489:119543c9f674	108	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/32 \|
mbed_official	489:119543c9f674	109	+--------------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	110
mbed_official	489:119543c9f674	111	@note The max SPI frequency depend on SPI data size (8bits, 16bits),
mbed_official	489:119543c9f674	112	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
mbed_official	489:119543c9f674	113	@note
mbed_official	489:119543c9f674	114	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
mbed_official	489:119543c9f674	115	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official	489:119543c9f674	116	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official	489:119543c9f674	117
mbed_official	489:119543c9f674	118	@endverbatim
mbed_official	489:119543c9f674	119	******************************************************************************
mbed_official	489:119543c9f674	120	* @attention
mbed_official	489:119543c9f674	121	*
mbed_official	489:119543c9f674	122	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	489:119543c9f674	123	*
mbed_official	489:119543c9f674	124	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	489:119543c9f674	125	* are permitted provided that the following conditions are met:
mbed_official	489:119543c9f674	126	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	489:119543c9f674	127	* this list of conditions and the following disclaimer.
mbed_official	489:119543c9f674	128	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	489:119543c9f674	129	* this list of conditions and the following disclaimer in the documentation
mbed_official	489:119543c9f674	130	* and/or other materials provided with the distribution.
mbed_official	489:119543c9f674	131	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	489:119543c9f674	132	* may be used to endorse or promote products derived from this software
mbed_official	489:119543c9f674	133	* without specific prior written permission.
mbed_official	489:119543c9f674	134	*
mbed_official	489:119543c9f674	135	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	489:119543c9f674	136	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	489:119543c9f674	137	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	489:119543c9f674	138	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	489:119543c9f674	139	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	489:119543c9f674	140	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	489:119543c9f674	141	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	489:119543c9f674	142	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	489:119543c9f674	143	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	489:119543c9f674	144	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	489:119543c9f674	145	*
mbed_official	489:119543c9f674	146	******************************************************************************
mbed_official	489:119543c9f674	147	*/
mbed_official	489:119543c9f674	148
mbed_official	489:119543c9f674	149	/* Includes ------------------------------------------------------------------*/
mbed_official	489:119543c9f674	150	#include "stm32f1xx_hal.h"
mbed_official	489:119543c9f674	151
mbed_official	489:119543c9f674	152	/** @addtogroup STM32F1xx_HAL_Driver
mbed_official	489:119543c9f674	153	* @{
mbed_official	489:119543c9f674	154	*/
mbed_official	489:119543c9f674	155
mbed_official	489:119543c9f674	156	/** @defgroup SPI SPI
mbed_official	489:119543c9f674	157	* @brief SPI HAL module driver
mbed_official	489:119543c9f674	158	* @{
mbed_official	489:119543c9f674	159	*/
mbed_official	489:119543c9f674	160
mbed_official	489:119543c9f674	161	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	489:119543c9f674	162
mbed_official	489:119543c9f674	163	/* Private typedef -----------------------------------------------------------*/
mbed_official	489:119543c9f674	164	/* Private define ------------------------------------------------------------*/
mbed_official	489:119543c9f674	165	/** @defgroup SPI_Private_Constants SPI Private Constants
mbed_official	489:119543c9f674	166	* @{
mbed_official	489:119543c9f674	167	*/
mbed_official	489:119543c9f674	168	#define SPI_TIMEOUT_VALUE 10
mbed_official	489:119543c9f674	169	/**
mbed_official	489:119543c9f674	170	* @}
mbed_official	489:119543c9f674	171	*/
mbed_official	489:119543c9f674	172
mbed_official	489:119543c9f674	173	/* Private macro -------------------------------------------------------------*/
mbed_official	489:119543c9f674	174	/* Private variables ---------------------------------------------------------*/
mbed_official	489:119543c9f674	175	/* Private function prototypes -----------------------------------------------*/
mbed_official	489:119543c9f674	176	/** @defgroup SPI_Private_Functions SPI Private Functions
mbed_official	489:119543c9f674	177	* @{
mbed_official	489:119543c9f674	178	*/
mbed_official	489:119543c9f674	179	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	489:119543c9f674	180	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official	489:119543c9f674	181	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	489:119543c9f674	182	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official	489:119543c9f674	183	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official	489:119543c9f674	184	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	185	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	186	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	187	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	188	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	189	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	190	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	191	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	489:119543c9f674	192	/**
mbed_official	489:119543c9f674	193	* @}
mbed_official	489:119543c9f674	194	*/
mbed_official	489:119543c9f674	195
mbed_official	489:119543c9f674	196	/* Exported functions ---------------------------------------------------------*/
mbed_official	489:119543c9f674	197
mbed_official	489:119543c9f674	198	/** @defgroup SPI_Exported_Functions SPI Exported Functions
mbed_official	489:119543c9f674	199	* @{
mbed_official	489:119543c9f674	200	*/
mbed_official	489:119543c9f674	201
mbed_official	489:119543c9f674	202	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official	489:119543c9f674	203	* @brief Initialization and Configuration functions
mbed_official	489:119543c9f674	204	*
mbed_official	489:119543c9f674	205	@verbatim
mbed_official	489:119543c9f674	206	===============================================================================
mbed_official	489:119543c9f674	207	##### Initialization and de-initialization functions #####
mbed_official	489:119543c9f674	208	===============================================================================
mbed_official	489:119543c9f674	209	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	489:119543c9f674	210	de-initialiaze the SPIx peripheral:
mbed_official	489:119543c9f674	211
mbed_official	489:119543c9f674	212	(+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official	489:119543c9f674	213	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	489:119543c9f674	214
mbed_official	489:119543c9f674	215	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	489:119543c9f674	216	the selected configuration:
mbed_official	489:119543c9f674	217	(++) Mode
mbed_official	489:119543c9f674	218	(++) Direction
mbed_official	489:119543c9f674	219	(++) Data Size
mbed_official	489:119543c9f674	220	(++) Clock Polarity and Phase
mbed_official	489:119543c9f674	221	(++) NSS Management
mbed_official	489:119543c9f674	222	(++) BaudRate Prescaler
mbed_official	489:119543c9f674	223	(++) FirstBit
mbed_official	489:119543c9f674	224	(++) TIMode
mbed_official	489:119543c9f674	225	(++) CRC Calculation
mbed_official	489:119543c9f674	226	(++) CRC Polynomial if CRC enabled
mbed_official	489:119543c9f674	227
mbed_official	489:119543c9f674	228	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	489:119543c9f674	229	of the selected SPIx periperal.
mbed_official	489:119543c9f674	230
mbed_official	489:119543c9f674	231	@endverbatim
mbed_official	489:119543c9f674	232	* @{
mbed_official	489:119543c9f674	233	*/
mbed_official	489:119543c9f674	234
mbed_official	489:119543c9f674	235	/**
mbed_official	489:119543c9f674	236	* @brief Initializes the SPI according to the specified parameters
mbed_official	489:119543c9f674	237	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	489:119543c9f674	238	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	239	* the configuration information for SPI module.
mbed_official	489:119543c9f674	240	* @retval HAL status
mbed_official	489:119543c9f674	241	*/
mbed_official	489:119543c9f674	242	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	243	{
mbed_official	489:119543c9f674	244	/* Check the SPI handle allocation */
mbed_official	489:119543c9f674	245	if(hspi == NULL)
mbed_official	489:119543c9f674	246	{
mbed_official	489:119543c9f674	247	return HAL_ERROR;
mbed_official	489:119543c9f674	248	}
mbed_official	489:119543c9f674	249
mbed_official	489:119543c9f674	250	/* Check the parameters */
mbed_official	489:119543c9f674	251	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official	489:119543c9f674	252	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	489:119543c9f674	253	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official	489:119543c9f674	254	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	489:119543c9f674	255	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	489:119543c9f674	256	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	489:119543c9f674	257	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	489:119543c9f674	258	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	489:119543c9f674	259	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	489:119543c9f674	260	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	489:119543c9f674	261	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	489:119543c9f674	262	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	489:119543c9f674	263
mbed_official	489:119543c9f674	264	if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official	489:119543c9f674	265	{
mbed_official	489:119543c9f674	266	/* Allocate lock resource and initialize it */
mbed_official	489:119543c9f674	267	hspi-> Lock = HAL_UNLOCKED;
mbed_official	489:119543c9f674	268
mbed_official	489:119543c9f674	269	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	489:119543c9f674	270	HAL_SPI_MspInit(hspi);
mbed_official	489:119543c9f674	271	}
mbed_official	489:119543c9f674	272
mbed_official	489:119543c9f674	273	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	489:119543c9f674	274
mbed_official	489:119543c9f674	275	/* Disble the selected SPI peripheral */
mbed_official	489:119543c9f674	276	__HAL_SPI_DISABLE(hspi);
mbed_official	489:119543c9f674	277
mbed_official	489:119543c9f674	278	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
mbed_official	489:119543c9f674	279	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official	489:119543c9f674	280	Communication speed, First bit and CRC calculation state */
mbed_official	489:119543c9f674	281	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
mbed_official	489:119543c9f674	282	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	489:119543c9f674	283	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
mbed_official	489:119543c9f674	284
mbed_official	489:119543c9f674	285	/* Configure : NSS management */
mbed_official	489:119543c9f674	286	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
mbed_official	489:119543c9f674	287
mbed_official	489:119543c9f674	288	/---------------------------- SPIx CRCPOLY Configuration ------------------/
mbed_official	489:119543c9f674	289	/* Configure : CRC Polynomial */
mbed_official	489:119543c9f674	290	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
mbed_official	489:119543c9f674	291
mbed_official	489:119543c9f674	292	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	293	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	294
mbed_official	489:119543c9f674	295	return HAL_OK;
mbed_official	489:119543c9f674	296	}
mbed_official	489:119543c9f674	297
mbed_official	489:119543c9f674	298	/**
mbed_official	489:119543c9f674	299	* @brief DeInitializes the SPI peripheral
mbed_official	489:119543c9f674	300	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	301	* the configuration information for SPI module.
mbed_official	489:119543c9f674	302	* @retval HAL status
mbed_official	489:119543c9f674	303	*/
mbed_official	489:119543c9f674	304	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	305	{
mbed_official	489:119543c9f674	306	/* Check the SPI handle allocation */
mbed_official	489:119543c9f674	307	if(hspi == NULL)
mbed_official	489:119543c9f674	308	{
mbed_official	489:119543c9f674	309	return HAL_ERROR;
mbed_official	489:119543c9f674	310	}
mbed_official	489:119543c9f674	311
mbed_official	489:119543c9f674	312	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	489:119543c9f674	313
mbed_official	489:119543c9f674	314	/* Disable the SPI Peripheral Clock */
mbed_official	489:119543c9f674	315	__HAL_SPI_DISABLE(hspi);
mbed_official	489:119543c9f674	316
mbed_official	489:119543c9f674	317	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	489:119543c9f674	318	HAL_SPI_MspDeInit(hspi);
mbed_official	489:119543c9f674	319
mbed_official	489:119543c9f674	320	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	321	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	489:119543c9f674	322
mbed_official	489:119543c9f674	323	/* Release Lock */
mbed_official	489:119543c9f674	324	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	325
mbed_official	489:119543c9f674	326	return HAL_OK;
mbed_official	489:119543c9f674	327	}
mbed_official	489:119543c9f674	328
mbed_official	489:119543c9f674	329	/**
mbed_official	489:119543c9f674	330	* @brief SPI MSP Init
mbed_official	489:119543c9f674	331	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	332	* the configuration information for SPI module.
mbed_official	489:119543c9f674	333	* @retval None
mbed_official	489:119543c9f674	334	*/
mbed_official	489:119543c9f674	335	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	336	{
mbed_official	489:119543c9f674	337	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	338	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	489:119543c9f674	339	*/
mbed_official	489:119543c9f674	340	}
mbed_official	489:119543c9f674	341
mbed_official	489:119543c9f674	342	/**
mbed_official	489:119543c9f674	343	* @brief SPI MSP DeInit
mbed_official	489:119543c9f674	344	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	345	* the configuration information for SPI module.
mbed_official	489:119543c9f674	346	* @retval None
mbed_official	489:119543c9f674	347	*/
mbed_official	489:119543c9f674	348	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	349	{
mbed_official	489:119543c9f674	350	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	351	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	489:119543c9f674	352	*/
mbed_official	489:119543c9f674	353	}
mbed_official	489:119543c9f674	354
mbed_official	489:119543c9f674	355	/**
mbed_official	489:119543c9f674	356	* @}
mbed_official	489:119543c9f674	357	*/
mbed_official	489:119543c9f674	358
mbed_official	489:119543c9f674	359	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
mbed_official	489:119543c9f674	360	* @brief Data transfers functions
mbed_official	489:119543c9f674	361	*
mbed_official	489:119543c9f674	362	@verbatim
mbed_official	489:119543c9f674	363	==============================================================================
mbed_official	489:119543c9f674	364	##### IO operation functions #####
mbed_official	489:119543c9f674	365	===============================================================================
mbed_official	489:119543c9f674	366	This subsection provides a set of functions allowing to manage the SPI
mbed_official	489:119543c9f674	367	data transfers.
mbed_official	489:119543c9f674	368
mbed_official	489:119543c9f674	369	[..] The SPI supports master and slave mode :
mbed_official	489:119543c9f674	370
mbed_official	489:119543c9f674	371	(#) There are two modes of transfer:
mbed_official	489:119543c9f674	372	(++) Blocking mode: The communication is performed in polling mode.
mbed_official	489:119543c9f674	373	The HAL status of all data processing is returned by the same function
mbed_official	489:119543c9f674	374	after finishing transfer.
mbed_official	489:119543c9f674	375	(++) No-Blocking mode: The communication is performed using Interrupts
mbed_official	489:119543c9f674	376	or DMA, These APIs return the HAL status.
mbed_official	489:119543c9f674	377	The end of the data processing will be indicated through the
mbed_official	489:119543c9f674	378	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	489:119543c9f674	379	using DMA mode.
mbed_official	489:119543c9f674	380	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	489:119543c9f674	381	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	489:119543c9f674	382	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	489:119543c9f674	383
mbed_official	489:119543c9f674	384	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
mbed_official	489:119543c9f674	385	exist for 1Line (simplex) and 2Lines (full duplex) modes.
mbed_official	489:119543c9f674	386
mbed_official	489:119543c9f674	387	@endverbatim
mbed_official	489:119543c9f674	388	* @{
mbed_official	489:119543c9f674	389	*/
mbed_official	489:119543c9f674	390
mbed_official	489:119543c9f674	391	/**
mbed_official	489:119543c9f674	392	* @brief Transmit an amount of data in blocking mode
mbed_official	489:119543c9f674	393	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	394	* the configuration information for SPI module.
mbed_official	489:119543c9f674	395	* @param pData: pointer to data buffer
mbed_official	489:119543c9f674	396	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	397	* @param Timeout: Timeout duration
mbed_official	489:119543c9f674	398	* @retval HAL status
mbed_official	489:119543c9f674	399	*/
mbed_official	489:119543c9f674	400	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	489:119543c9f674	401	{
mbed_official	489:119543c9f674	402
mbed_official	489:119543c9f674	403	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	489:119543c9f674	404	{
mbed_official	489:119543c9f674	405	if((pData == NULL ) \|\| (Size == 0))
mbed_official	489:119543c9f674	406	{
mbed_official	489:119543c9f674	407	return HAL_ERROR;
mbed_official	489:119543c9f674	408	}
mbed_official	489:119543c9f674	409
mbed_official	489:119543c9f674	410	/* Check the parameters */
mbed_official	489:119543c9f674	411	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	489:119543c9f674	412
mbed_official	489:119543c9f674	413	/* Process Locked */
mbed_official	489:119543c9f674	414	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	415
mbed_official	489:119543c9f674	416	/* Configure communication */
mbed_official	489:119543c9f674	417	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	489:119543c9f674	418	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	419
mbed_official	489:119543c9f674	420	hspi->pTxBuffPtr = pData;
mbed_official	489:119543c9f674	421	hspi->TxXferSize = Size;
mbed_official	489:119543c9f674	422	hspi->TxXferCount = Size;
mbed_official	489:119543c9f674	423
mbed_official	489:119543c9f674	424	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	425	hspi->TxISR = 0;
mbed_official	489:119543c9f674	426	hspi->RxISR = 0;
mbed_official	489:119543c9f674	427	hspi->pRxBuffPtr = NULL;
mbed_official	489:119543c9f674	428	hspi->RxXferSize = 0;
mbed_official	489:119543c9f674	429	hspi->RxXferCount = 0;
mbed_official	489:119543c9f674	430
mbed_official	489:119543c9f674	431	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	432	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	433	{
mbed_official	489:119543c9f674	434	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	435	}
mbed_official	489:119543c9f674	436
mbed_official	489:119543c9f674	437	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	489:119543c9f674	438	{
mbed_official	489:119543c9f674	439	/* Configure communication direction : 1Line */
mbed_official	489:119543c9f674	440	SPI_1LINE_TX(hspi);
mbed_official	489:119543c9f674	441	}
mbed_official	489:119543c9f674	442
mbed_official	489:119543c9f674	443	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	444	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	445	{
mbed_official	489:119543c9f674	446	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	447	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	448	}
mbed_official	489:119543c9f674	449
mbed_official	489:119543c9f674	450	/* Transmit data in 8 Bit mode */
mbed_official	489:119543c9f674	451	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	489:119543c9f674	452	{
mbed_official	489:119543c9f674	453	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
mbed_official	489:119543c9f674	454	{
mbed_official	489:119543c9f674	455	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	489:119543c9f674	456	hspi->TxXferCount--;
mbed_official	489:119543c9f674	457	}
mbed_official	489:119543c9f674	458
mbed_official	489:119543c9f674	459	while(hspi->TxXferCount > 0)
mbed_official	489:119543c9f674	460	{
mbed_official	489:119543c9f674	461	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	462	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	463	{
mbed_official	489:119543c9f674	464	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	465	}
mbed_official	489:119543c9f674	466	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	489:119543c9f674	467	hspi->TxXferCount--;
mbed_official	489:119543c9f674	468	}
mbed_official	489:119543c9f674	469	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	470	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	471	{
mbed_official	489:119543c9f674	472	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	473	}
mbed_official	489:119543c9f674	474	}
mbed_official	489:119543c9f674	475	/* Transmit data in 16 Bit mode */
mbed_official	489:119543c9f674	476	else
mbed_official	489:119543c9f674	477	{
mbed_official	489:119543c9f674	478	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
mbed_official	489:119543c9f674	479	{
mbed_official	489:119543c9f674	480	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	489:119543c9f674	481	hspi->pTxBuffPtr+=2;
mbed_official	489:119543c9f674	482	hspi->TxXferCount--;
mbed_official	489:119543c9f674	483	}
mbed_official	489:119543c9f674	484
mbed_official	489:119543c9f674	485	while(hspi->TxXferCount > 0)
mbed_official	489:119543c9f674	486	{
mbed_official	489:119543c9f674	487	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	488	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	489	{
mbed_official	489:119543c9f674	490	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	491	}
mbed_official	489:119543c9f674	492	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	489:119543c9f674	493	hspi->pTxBuffPtr+=2;
mbed_official	489:119543c9f674	494	hspi->TxXferCount--;
mbed_official	489:119543c9f674	495	}
mbed_official	489:119543c9f674	496	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	497	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	498	{
mbed_official	489:119543c9f674	499	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	500	}
mbed_official	489:119543c9f674	501	}
mbed_official	489:119543c9f674	502
mbed_official	489:119543c9f674	503	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	504	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	505	{
mbed_official	489:119543c9f674	506	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	507	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	508	}
mbed_official	489:119543c9f674	509
mbed_official	489:119543c9f674	510	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	489:119543c9f674	511	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	512	{
mbed_official	489:119543c9f674	513	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	514	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	515	}
mbed_official	489:119543c9f674	516
mbed_official	489:119543c9f674	517	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	489:119543c9f674	518	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	489:119543c9f674	519	{
mbed_official	489:119543c9f674	520	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	489:119543c9f674	521	}
mbed_official	489:119543c9f674	522
mbed_official	489:119543c9f674	523	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	524
mbed_official	489:119543c9f674	525	/* Process Unlocked */
mbed_official	489:119543c9f674	526	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	527
mbed_official	489:119543c9f674	528	return HAL_OK;
mbed_official	489:119543c9f674	529	}
mbed_official	489:119543c9f674	530	else
mbed_official	489:119543c9f674	531	{
mbed_official	489:119543c9f674	532	return HAL_BUSY;
mbed_official	489:119543c9f674	533	}
mbed_official	489:119543c9f674	534	}
mbed_official	489:119543c9f674	535
mbed_official	489:119543c9f674	536	/**
mbed_official	489:119543c9f674	537	* @brief Receive an amount of data in blocking mode
mbed_official	489:119543c9f674	538	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	539	* the configuration information for SPI module.
mbed_official	489:119543c9f674	540	* @param pData: pointer to data buffer
mbed_official	489:119543c9f674	541	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	542	* @param Timeout: Timeout duration
mbed_official	489:119543c9f674	543	* @retval HAL status
mbed_official	489:119543c9f674	544	*/
mbed_official	489:119543c9f674	545	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	489:119543c9f674	546	{
mbed_official	489:119543c9f674	547	__IO uint16_t tmpreg = 0;
mbed_official	489:119543c9f674	548
mbed_official	489:119543c9f674	549	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	489:119543c9f674	550	{
mbed_official	489:119543c9f674	551	if((pData == NULL ) \|\| (Size == 0))
mbed_official	489:119543c9f674	552	{
mbed_official	489:119543c9f674	553	return HAL_ERROR;
mbed_official	489:119543c9f674	554	}
mbed_official	489:119543c9f674	555
mbed_official	489:119543c9f674	556	/* Process Locked */
mbed_official	489:119543c9f674	557	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	558
mbed_official	489:119543c9f674	559	/* Configure communication */
mbed_official	489:119543c9f674	560	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	489:119543c9f674	561	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	562
mbed_official	489:119543c9f674	563	hspi->pRxBuffPtr = pData;
mbed_official	489:119543c9f674	564	hspi->RxXferSize = Size;
mbed_official	489:119543c9f674	565	hspi->RxXferCount = Size;
mbed_official	489:119543c9f674	566
mbed_official	489:119543c9f674	567	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	568	hspi->RxISR = 0;
mbed_official	489:119543c9f674	569	hspi->TxISR = 0;
mbed_official	489:119543c9f674	570	hspi->pTxBuffPtr = NULL;
mbed_official	489:119543c9f674	571	hspi->TxXferSize = 0;
mbed_official	489:119543c9f674	572	hspi->TxXferCount = 0;
mbed_official	489:119543c9f674	573
mbed_official	489:119543c9f674	574	/* Configure communication direction : 1Line */
mbed_official	489:119543c9f674	575	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	489:119543c9f674	576	{
mbed_official	489:119543c9f674	577	SPI_1LINE_RX(hspi);
mbed_official	489:119543c9f674	578	}
mbed_official	489:119543c9f674	579
mbed_official	489:119543c9f674	580	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	581	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	582	{
mbed_official	489:119543c9f674	583	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	584	}
mbed_official	489:119543c9f674	585
mbed_official	489:119543c9f674	586	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	489:119543c9f674	587	{
mbed_official	489:119543c9f674	588	/* Process Unlocked */
mbed_official	489:119543c9f674	589	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	590
mbed_official	489:119543c9f674	591	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	489:119543c9f674	592	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official	489:119543c9f674	593	}
mbed_official	489:119543c9f674	594
mbed_official	489:119543c9f674	595	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	596	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	597	{
mbed_official	489:119543c9f674	598	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	599	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	600	}
mbed_official	489:119543c9f674	601
mbed_official	489:119543c9f674	602	/* Receive data in 8 Bit mode */
mbed_official	489:119543c9f674	603	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	489:119543c9f674	604	{
mbed_official	489:119543c9f674	605	while(hspi->RxXferCount > 1)
mbed_official	489:119543c9f674	606	{
mbed_official	489:119543c9f674	607	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	608	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	609	{
mbed_official	489:119543c9f674	610	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	611	}
mbed_official	489:119543c9f674	612
mbed_official	489:119543c9f674	613	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	489:119543c9f674	614	hspi->RxXferCount--;
mbed_official	489:119543c9f674	615	}
mbed_official	489:119543c9f674	616	/* Enable CRC Reception */
mbed_official	489:119543c9f674	617	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	618	{
mbed_official	489:119543c9f674	619	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	620	}
mbed_official	489:119543c9f674	621	}
mbed_official	489:119543c9f674	622	/* Receive data in 16 Bit mode */
mbed_official	489:119543c9f674	623	else
mbed_official	489:119543c9f674	624	{
mbed_official	489:119543c9f674	625	while(hspi->RxXferCount > 1)
mbed_official	489:119543c9f674	626	{
mbed_official	489:119543c9f674	627	/* Wait until RXNE flag is set to read data */
mbed_official	489:119543c9f674	628	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	629	{
mbed_official	489:119543c9f674	630	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	631	}
mbed_official	489:119543c9f674	632
mbed_official	489:119543c9f674	633	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	634	hspi->pRxBuffPtr+=2;
mbed_official	489:119543c9f674	635	hspi->RxXferCount--;
mbed_official	489:119543c9f674	636	}
mbed_official	489:119543c9f674	637	/* Enable CRC Reception */
mbed_official	489:119543c9f674	638	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	639	{
mbed_official	489:119543c9f674	640	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	641	}
mbed_official	489:119543c9f674	642	}
mbed_official	489:119543c9f674	643
mbed_official	489:119543c9f674	644	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	645	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	646	{
mbed_official	489:119543c9f674	647	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	648	}
mbed_official	489:119543c9f674	649
mbed_official	489:119543c9f674	650	/* Receive last data in 8 Bit mode */
mbed_official	489:119543c9f674	651	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	489:119543c9f674	652	{
mbed_official	489:119543c9f674	653	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	489:119543c9f674	654	}
mbed_official	489:119543c9f674	655	/* Receive last data in 16 Bit mode */
mbed_official	489:119543c9f674	656	else
mbed_official	489:119543c9f674	657	{
mbed_official	489:119543c9f674	658	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	659	hspi->pRxBuffPtr+=2;
mbed_official	489:119543c9f674	660	}
mbed_official	489:119543c9f674	661	hspi->RxXferCount--;
mbed_official	489:119543c9f674	662
mbed_official	489:119543c9f674	663	/* If CRC computation is enabled */
mbed_official	489:119543c9f674	664	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	665	{
mbed_official	489:119543c9f674	666	/* Wait until RXNE flag is set: CRC Received */
mbed_official	489:119543c9f674	667	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	668	{
mbed_official	489:119543c9f674	669	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	670	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	671	}
mbed_official	489:119543c9f674	672
mbed_official	489:119543c9f674	673	/* Read CRC to clear RXNE flag */
mbed_official	489:119543c9f674	674	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	675	UNUSED(tmpreg);
mbed_official	489:119543c9f674	676	}
mbed_official	489:119543c9f674	677
mbed_official	489:119543c9f674	678	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	489:119543c9f674	679	{
mbed_official	489:119543c9f674	680	/* Disable SPI peripheral */
mbed_official	489:119543c9f674	681	__HAL_SPI_DISABLE(hspi);
mbed_official	489:119543c9f674	682	}
mbed_official	489:119543c9f674	683
mbed_official	489:119543c9f674	684	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	685
mbed_official	489:119543c9f674	686	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	687	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
mbed_official	489:119543c9f674	688	{
mbed_official	489:119543c9f674	689	/* Check if CRC error is valid or not (workaround to be applied or not) */
mbed_official	489:119543c9f674	690	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
mbed_official	489:119543c9f674	691	{
mbed_official	489:119543c9f674	692	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	693
mbed_official	489:119543c9f674	694	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	695	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	696
mbed_official	489:119543c9f674	697	/* Process Unlocked */
mbed_official	489:119543c9f674	698	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	699
mbed_official	489:119543c9f674	700	return HAL_ERROR;
mbed_official	489:119543c9f674	701	}
mbed_official	489:119543c9f674	702	else
mbed_official	489:119543c9f674	703	{
mbed_official	489:119543c9f674	704	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	489:119543c9f674	705	}
mbed_official	489:119543c9f674	706	}
mbed_official	489:119543c9f674	707
mbed_official	489:119543c9f674	708	/* Process Unlocked */
mbed_official	489:119543c9f674	709	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	710
mbed_official	489:119543c9f674	711	return HAL_OK;
mbed_official	489:119543c9f674	712	}
mbed_official	489:119543c9f674	713	else
mbed_official	489:119543c9f674	714	{
mbed_official	489:119543c9f674	715	return HAL_BUSY;
mbed_official	489:119543c9f674	716	}
mbed_official	489:119543c9f674	717	}
mbed_official	489:119543c9f674	718
mbed_official	489:119543c9f674	719	/**
mbed_official	489:119543c9f674	720	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	489:119543c9f674	721	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	722	* the configuration information for SPI module.
mbed_official	489:119543c9f674	723	* @param pTxData: pointer to transmission data buffer
mbed_official	489:119543c9f674	724	* @param pRxData: pointer to reception data buffer to be
mbed_official	489:119543c9f674	725	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	726	* @param Timeout: Timeout duration
mbed_official	489:119543c9f674	727	* @retval HAL status
mbed_official	489:119543c9f674	728	*/
mbed_official	489:119543c9f674	729	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	489:119543c9f674	730	{
mbed_official	489:119543c9f674	731	__IO uint16_t tmpreg = 0;
mbed_official	489:119543c9f674	732
mbed_official	489:119543c9f674	733	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
mbed_official	489:119543c9f674	734	{
mbed_official	489:119543c9f674	735	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	489:119543c9f674	736	{
mbed_official	489:119543c9f674	737	return HAL_ERROR;
mbed_official	489:119543c9f674	738	}
mbed_official	489:119543c9f674	739
mbed_official	489:119543c9f674	740	/* Check the parameters */
mbed_official	489:119543c9f674	741	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	489:119543c9f674	742
mbed_official	489:119543c9f674	743	/* Process Locked */
mbed_official	489:119543c9f674	744	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	745
mbed_official	489:119543c9f674	746	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	489:119543c9f674	747	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	489:119543c9f674	748	{
mbed_official	489:119543c9f674	749	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	489:119543c9f674	750	}
mbed_official	489:119543c9f674	751
mbed_official	489:119543c9f674	752	/* Configure communication */
mbed_official	489:119543c9f674	753	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	754
mbed_official	489:119543c9f674	755	hspi->pRxBuffPtr = pRxData;
mbed_official	489:119543c9f674	756	hspi->RxXferSize = Size;
mbed_official	489:119543c9f674	757	hspi->RxXferCount = Size;
mbed_official	489:119543c9f674	758
mbed_official	489:119543c9f674	759	hspi->pTxBuffPtr = pTxData;
mbed_official	489:119543c9f674	760	hspi->TxXferSize = Size;
mbed_official	489:119543c9f674	761	hspi->TxXferCount = Size;
mbed_official	489:119543c9f674	762
mbed_official	489:119543c9f674	763	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	764	hspi->RxISR = 0;
mbed_official	489:119543c9f674	765	hspi->TxISR = 0;
mbed_official	489:119543c9f674	766
mbed_official	489:119543c9f674	767	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	768	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	769	{
mbed_official	489:119543c9f674	770	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	771	}
mbed_official	489:119543c9f674	772
mbed_official	489:119543c9f674	773	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	774	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	775	{
mbed_official	489:119543c9f674	776	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	777	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	778	}
mbed_official	489:119543c9f674	779
mbed_official	489:119543c9f674	780	/* Transmit and Receive data in 16 Bit mode */
mbed_official	489:119543c9f674	781	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	489:119543c9f674	782	{
mbed_official	489:119543c9f674	783	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official	489:119543c9f674	784	{
mbed_official	489:119543c9f674	785	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	489:119543c9f674	786	hspi->pTxBuffPtr+=2;
mbed_official	489:119543c9f674	787	hspi->TxXferCount--;
mbed_official	489:119543c9f674	788	}
mbed_official	489:119543c9f674	789	if(hspi->TxXferCount == 0)
mbed_official	489:119543c9f674	790	{
mbed_official	489:119543c9f674	791	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	792	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	793	{
mbed_official	489:119543c9f674	794	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	795	}
mbed_official	489:119543c9f674	796
mbed_official	489:119543c9f674	797	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	798	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	799	{
mbed_official	489:119543c9f674	800	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	801	}
mbed_official	489:119543c9f674	802
mbed_official	489:119543c9f674	803	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	804	hspi->pRxBuffPtr+=2;
mbed_official	489:119543c9f674	805	hspi->RxXferCount--;
mbed_official	489:119543c9f674	806	}
mbed_official	489:119543c9f674	807	else
mbed_official	489:119543c9f674	808	{
mbed_official	489:119543c9f674	809	while(hspi->TxXferCount > 0)
mbed_official	489:119543c9f674	810	{
mbed_official	489:119543c9f674	811	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	812	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	813	{
mbed_official	489:119543c9f674	814	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	815	}
mbed_official	489:119543c9f674	816
mbed_official	489:119543c9f674	817	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	489:119543c9f674	818	hspi->pTxBuffPtr+=2;
mbed_official	489:119543c9f674	819	hspi->TxXferCount--;
mbed_official	489:119543c9f674	820
mbed_official	489:119543c9f674	821	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	822	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official	489:119543c9f674	823	{
mbed_official	489:119543c9f674	824	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	825	}
mbed_official	489:119543c9f674	826
mbed_official	489:119543c9f674	827	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	828	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	829	{
mbed_official	489:119543c9f674	830	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	831	}
mbed_official	489:119543c9f674	832
mbed_official	489:119543c9f674	833	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	834	hspi->pRxBuffPtr+=2;
mbed_official	489:119543c9f674	835	hspi->RxXferCount--;
mbed_official	489:119543c9f674	836	}
mbed_official	489:119543c9f674	837	/* Receive the last byte */
mbed_official	489:119543c9f674	838	if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official	489:119543c9f674	839	{
mbed_official	489:119543c9f674	840	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	841	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	842	{
mbed_official	489:119543c9f674	843	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	844	}
mbed_official	489:119543c9f674	845
mbed_official	489:119543c9f674	846	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	847	hspi->pRxBuffPtr+=2;
mbed_official	489:119543c9f674	848	hspi->RxXferCount--;
mbed_official	489:119543c9f674	849	}
mbed_official	489:119543c9f674	850	}
mbed_official	489:119543c9f674	851	}
mbed_official	489:119543c9f674	852	/* Transmit and Receive data in 8 Bit mode */
mbed_official	489:119543c9f674	853	else
mbed_official	489:119543c9f674	854	{
mbed_official	489:119543c9f674	855	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official	489:119543c9f674	856	{
mbed_official	489:119543c9f674	857	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	489:119543c9f674	858	hspi->TxXferCount--;
mbed_official	489:119543c9f674	859	}
mbed_official	489:119543c9f674	860	if(hspi->TxXferCount == 0)
mbed_official	489:119543c9f674	861	{
mbed_official	489:119543c9f674	862	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	863	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	864	{
mbed_official	489:119543c9f674	865	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	866	}
mbed_official	489:119543c9f674	867
mbed_official	489:119543c9f674	868	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	869	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	870	{
mbed_official	489:119543c9f674	871	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	872	}
mbed_official	489:119543c9f674	873
mbed_official	489:119543c9f674	874	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	875	hspi->RxXferCount--;
mbed_official	489:119543c9f674	876	}
mbed_official	489:119543c9f674	877	else
mbed_official	489:119543c9f674	878	{
mbed_official	489:119543c9f674	879	while(hspi->TxXferCount > 0)
mbed_official	489:119543c9f674	880	{
mbed_official	489:119543c9f674	881	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	882	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	883	{
mbed_official	489:119543c9f674	884	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	885	}
mbed_official	489:119543c9f674	886
mbed_official	489:119543c9f674	887	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	489:119543c9f674	888	hspi->TxXferCount--;
mbed_official	489:119543c9f674	889
mbed_official	489:119543c9f674	890	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	891	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official	489:119543c9f674	892	{
mbed_official	489:119543c9f674	893	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	894	}
mbed_official	489:119543c9f674	895
mbed_official	489:119543c9f674	896	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	897	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	898	{
mbed_official	489:119543c9f674	899	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	900	}
mbed_official	489:119543c9f674	901
mbed_official	489:119543c9f674	902	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	489:119543c9f674	903	hspi->RxXferCount--;
mbed_official	489:119543c9f674	904	}
mbed_official	489:119543c9f674	905	if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official	489:119543c9f674	906	{
mbed_official	489:119543c9f674	907	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	908	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	909	{
mbed_official	489:119543c9f674	910	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	911	}
mbed_official	489:119543c9f674	912
mbed_official	489:119543c9f674	913	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	489:119543c9f674	914	hspi->RxXferCount--;
mbed_official	489:119543c9f674	915	}
mbed_official	489:119543c9f674	916	}
mbed_official	489:119543c9f674	917	}
mbed_official	489:119543c9f674	918
mbed_official	489:119543c9f674	919	/* Read CRC from DR to close CRC calculation process */
mbed_official	489:119543c9f674	920	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	921	{
mbed_official	489:119543c9f674	922	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	923	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	924	{
mbed_official	489:119543c9f674	925	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	926	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	927	}
mbed_official	489:119543c9f674	928	/* Read CRC */
mbed_official	489:119543c9f674	929	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	930	UNUSED(tmpreg);
mbed_official	489:119543c9f674	931	}
mbed_official	489:119543c9f674	932
mbed_official	489:119543c9f674	933	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	489:119543c9f674	934	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	935	{
mbed_official	489:119543c9f674	936	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	937	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	938	}
mbed_official	489:119543c9f674	939
mbed_official	489:119543c9f674	940	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	941
mbed_official	489:119543c9f674	942	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	943	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
mbed_official	489:119543c9f674	944	{
mbed_official	489:119543c9f674	945	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	946
mbed_official	489:119543c9f674	947	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	948
mbed_official	489:119543c9f674	949	/* Process Unlocked */
mbed_official	489:119543c9f674	950	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	951
mbed_official	489:119543c9f674	952	return HAL_ERROR;
mbed_official	489:119543c9f674	953	}
mbed_official	489:119543c9f674	954
mbed_official	489:119543c9f674	955	/* Process Unlocked */
mbed_official	489:119543c9f674	956	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	957
mbed_official	489:119543c9f674	958	return HAL_OK;
mbed_official	489:119543c9f674	959	}
mbed_official	489:119543c9f674	960	else
mbed_official	489:119543c9f674	961	{
mbed_official	489:119543c9f674	962	return HAL_BUSY;
mbed_official	489:119543c9f674	963	}
mbed_official	489:119543c9f674	964	}
mbed_official	489:119543c9f674	965
mbed_official	489:119543c9f674	966	/**
mbed_official	489:119543c9f674	967	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	489:119543c9f674	968	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	969	* the configuration information for SPI module.
mbed_official	489:119543c9f674	970	* @param pData: pointer to data buffer
mbed_official	489:119543c9f674	971	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	972	* @retval HAL status
mbed_official	489:119543c9f674	973	*/
mbed_official	489:119543c9f674	974	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	489:119543c9f674	975	{
mbed_official	489:119543c9f674	976	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	489:119543c9f674	977	{
mbed_official	489:119543c9f674	978	if((pData == NULL) \|\| (Size == 0))
mbed_official	489:119543c9f674	979	{
mbed_official	489:119543c9f674	980	return HAL_ERROR;
mbed_official	489:119543c9f674	981	}
mbed_official	489:119543c9f674	982
mbed_official	489:119543c9f674	983	/* Check the parameters */
mbed_official	489:119543c9f674	984	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	489:119543c9f674	985
mbed_official	489:119543c9f674	986	/* Process Locked */
mbed_official	489:119543c9f674	987	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	988
mbed_official	489:119543c9f674	989	/* Configure communication */
mbed_official	489:119543c9f674	990	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	489:119543c9f674	991	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	992
mbed_official	489:119543c9f674	993	hspi->TxISR = &SPI_TxISR;
mbed_official	489:119543c9f674	994	hspi->pTxBuffPtr = pData;
mbed_official	489:119543c9f674	995	hspi->TxXferSize = Size;
mbed_official	489:119543c9f674	996	hspi->TxXferCount = Size;
mbed_official	489:119543c9f674	997
mbed_official	489:119543c9f674	998	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	999	hspi->RxISR = 0;
mbed_official	489:119543c9f674	1000	hspi->pRxBuffPtr = NULL;
mbed_official	489:119543c9f674	1001	hspi->RxXferSize = 0;
mbed_official	489:119543c9f674	1002	hspi->RxXferCount = 0;
mbed_official	489:119543c9f674	1003
mbed_official	489:119543c9f674	1004	/* Configure communication direction : 1Line */
mbed_official	489:119543c9f674	1005	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	489:119543c9f674	1006	{
mbed_official	489:119543c9f674	1007	SPI_1LINE_TX(hspi);
mbed_official	489:119543c9f674	1008	}
mbed_official	489:119543c9f674	1009
mbed_official	489:119543c9f674	1010	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1011	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1012	{
mbed_official	489:119543c9f674	1013	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	1014	}
mbed_official	489:119543c9f674	1015
mbed_official	489:119543c9f674	1016	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	489:119543c9f674	1017	{
mbed_official	489:119543c9f674	1018	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	489:119543c9f674	1019	}
mbed_official	489:119543c9f674	1020	else
mbed_official	489:119543c9f674	1021	{
mbed_official	489:119543c9f674	1022	/* Enable TXE and ERR interrupt */
mbed_official	489:119543c9f674	1023	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	489:119543c9f674	1024	}
mbed_official	489:119543c9f674	1025	/* Process Unlocked */
mbed_official	489:119543c9f674	1026	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1027
mbed_official	489:119543c9f674	1028	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	1030	{
mbed_official	489:119543c9f674	1031	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	1032	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	1033	}
mbed_official	489:119543c9f674	1034
mbed_official	489:119543c9f674	1035	return HAL_OK;
mbed_official	489:119543c9f674	1036	}
mbed_official	489:119543c9f674	1037	else
mbed_official	489:119543c9f674	1038	{
mbed_official	489:119543c9f674	1039	return HAL_BUSY;
mbed_official	489:119543c9f674	1040	}
mbed_official	489:119543c9f674	1041	}
mbed_official	489:119543c9f674	1042
mbed_official	489:119543c9f674	1043	/**
mbed_official	489:119543c9f674	1044	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	489:119543c9f674	1045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1046	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1047	* @param pData: pointer to data buffer
mbed_official	489:119543c9f674	1048	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	1049	* @retval HAL status
mbed_official	489:119543c9f674	1050	*/
mbed_official	489:119543c9f674	1051	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	489:119543c9f674	1052	{
mbed_official	489:119543c9f674	1053	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	489:119543c9f674	1054	{
mbed_official	489:119543c9f674	1055	if((pData == NULL) \|\| (Size == 0))
mbed_official	489:119543c9f674	1056	{
mbed_official	489:119543c9f674	1057	return HAL_ERROR;
mbed_official	489:119543c9f674	1058	}
mbed_official	489:119543c9f674	1059
mbed_official	489:119543c9f674	1060	/* Process Locked */
mbed_official	489:119543c9f674	1061	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	1062
mbed_official	489:119543c9f674	1063	/* Configure communication */
mbed_official	489:119543c9f674	1064	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	489:119543c9f674	1065	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	1066
mbed_official	489:119543c9f674	1067	hspi->RxISR = &SPI_RxISR;
mbed_official	489:119543c9f674	1068	hspi->pRxBuffPtr = pData;
mbed_official	489:119543c9f674	1069	hspi->RxXferSize = Size;
mbed_official	489:119543c9f674	1070	hspi->RxXferCount = Size ;
mbed_official	489:119543c9f674	1071
mbed_official	489:119543c9f674	1072	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1073	hspi->TxISR = 0;
mbed_official	489:119543c9f674	1074	hspi->pTxBuffPtr = NULL;
mbed_official	489:119543c9f674	1075	hspi->TxXferSize = 0;
mbed_official	489:119543c9f674	1076	hspi->TxXferCount = 0;
mbed_official	489:119543c9f674	1077
mbed_official	489:119543c9f674	1078	/* Configure communication direction : 1Line */
mbed_official	489:119543c9f674	1079	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	489:119543c9f674	1080	{
mbed_official	489:119543c9f674	1081	SPI_1LINE_RX(hspi);
mbed_official	489:119543c9f674	1082	}
mbed_official	489:119543c9f674	1083	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	489:119543c9f674	1084	{
mbed_official	489:119543c9f674	1085	/* Process Unlocked */
mbed_official	489:119543c9f674	1086	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1087
mbed_official	489:119543c9f674	1088	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	489:119543c9f674	1089	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official	489:119543c9f674	1090	}
mbed_official	489:119543c9f674	1091
mbed_official	489:119543c9f674	1092	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1093	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1094	{
mbed_official	489:119543c9f674	1095	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	1096	}
mbed_official	489:119543c9f674	1097
mbed_official	489:119543c9f674	1098	/* Enable TXE and ERR interrupt */
mbed_official	489:119543c9f674	1099	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	489:119543c9f674	1100
mbed_official	489:119543c9f674	1101	/* Process Unlocked */
mbed_official	489:119543c9f674	1102	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1103
mbed_official	489:119543c9f674	1104	/* Note : The SPI must be enabled after unlocking current process
mbed_official	489:119543c9f674	1105	to avoid the risk of SPI interrupt handle execution before current
mbed_official	489:119543c9f674	1106	process unlock */
mbed_official	489:119543c9f674	1107
mbed_official	489:119543c9f674	1108	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	1109	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	1110	{
mbed_official	489:119543c9f674	1111	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	1112	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	1113	}
mbed_official	489:119543c9f674	1114
mbed_official	489:119543c9f674	1115	return HAL_OK;
mbed_official	489:119543c9f674	1116	}
mbed_official	489:119543c9f674	1117	else
mbed_official	489:119543c9f674	1118	{
mbed_official	489:119543c9f674	1119	return HAL_BUSY;
mbed_official	489:119543c9f674	1120	}
mbed_official	489:119543c9f674	1121	}
mbed_official	489:119543c9f674	1122
mbed_official	489:119543c9f674	1123	/**
mbed_official	489:119543c9f674	1124	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	489:119543c9f674	1125	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1126	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1127	* @param pTxData: pointer to transmission data buffer
mbed_official	489:119543c9f674	1128	* @param pRxData: pointer to reception data buffer to be
mbed_official	489:119543c9f674	1129	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	1130	* @retval HAL status
mbed_official	489:119543c9f674	1131	*/
mbed_official	489:119543c9f674	1132	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	489:119543c9f674	1133	{
mbed_official	489:119543c9f674	1134
mbed_official	489:119543c9f674	1135	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
mbed_official	489:119543c9f674	1136	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	489:119543c9f674	1137	{
mbed_official	489:119543c9f674	1138	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	489:119543c9f674	1139	{
mbed_official	489:119543c9f674	1140	return HAL_ERROR;
mbed_official	489:119543c9f674	1141	}
mbed_official	489:119543c9f674	1142
mbed_official	489:119543c9f674	1143	/* Check the parameters */
mbed_official	489:119543c9f674	1144	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	489:119543c9f674	1145
mbed_official	489:119543c9f674	1146	/* Process locked */
mbed_official	489:119543c9f674	1147	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	1148
mbed_official	489:119543c9f674	1149	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	489:119543c9f674	1150	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	489:119543c9f674	1151	{
mbed_official	489:119543c9f674	1152	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	489:119543c9f674	1153	}
mbed_official	489:119543c9f674	1154
mbed_official	489:119543c9f674	1155	/* Configure communication */
mbed_official	489:119543c9f674	1156	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	1157
mbed_official	489:119543c9f674	1158	hspi->TxISR = &SPI_TxISR;
mbed_official	489:119543c9f674	1159	hspi->pTxBuffPtr = pTxData;
mbed_official	489:119543c9f674	1160	hspi->TxXferSize = Size;
mbed_official	489:119543c9f674	1161	hspi->TxXferCount = Size;
mbed_official	489:119543c9f674	1162
mbed_official	489:119543c9f674	1163	hspi->RxISR = &SPI_2LinesRxISR;
mbed_official	489:119543c9f674	1164	hspi->pRxBuffPtr = pRxData;
mbed_official	489:119543c9f674	1165	hspi->RxXferSize = Size;
mbed_official	489:119543c9f674	1166	hspi->RxXferCount = Size;
mbed_official	489:119543c9f674	1167
mbed_official	489:119543c9f674	1168	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1169	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1170	{
mbed_official	489:119543c9f674	1171	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	1172	}
mbed_official	489:119543c9f674	1173
mbed_official	489:119543c9f674	1174	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	489:119543c9f674	1175	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	489:119543c9f674	1176
mbed_official	489:119543c9f674	1177	/* Process Unlocked */
mbed_official	489:119543c9f674	1178	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1179
mbed_official	489:119543c9f674	1180	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	1181	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	1182	{
mbed_official	489:119543c9f674	1183	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	1184	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	1185	}
mbed_official	489:119543c9f674	1186
mbed_official	489:119543c9f674	1187	return HAL_OK;
mbed_official	489:119543c9f674	1188	}
mbed_official	489:119543c9f674	1189	else
mbed_official	489:119543c9f674	1190	{
mbed_official	489:119543c9f674	1191	return HAL_BUSY;
mbed_official	489:119543c9f674	1192	}
mbed_official	489:119543c9f674	1193	}
mbed_official	489:119543c9f674	1194
mbed_official	489:119543c9f674	1195	/**
mbed_official	489:119543c9f674	1196	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	489:119543c9f674	1197	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1198	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1199	* @param pData: pointer to data buffer
mbed_official	489:119543c9f674	1200	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	1201	* @retval HAL status
mbed_official	489:119543c9f674	1202	*/
mbed_official	489:119543c9f674	1203	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	489:119543c9f674	1204	{
mbed_official	489:119543c9f674	1205	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	489:119543c9f674	1206	{
mbed_official	489:119543c9f674	1207	if((pData == NULL) \|\| (Size == 0))
mbed_official	489:119543c9f674	1208	{
mbed_official	489:119543c9f674	1209	return HAL_ERROR;
mbed_official	489:119543c9f674	1210	}
mbed_official	489:119543c9f674	1211
mbed_official	489:119543c9f674	1212	/* Check the parameters */
mbed_official	489:119543c9f674	1213	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	489:119543c9f674	1214
mbed_official	489:119543c9f674	1215	/* Process Locked */
mbed_official	489:119543c9f674	1216	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	1217
mbed_official	489:119543c9f674	1218	/* Configure communication */
mbed_official	489:119543c9f674	1219	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	489:119543c9f674	1220	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	1221
mbed_official	489:119543c9f674	1222	hspi->pTxBuffPtr = pData;
mbed_official	489:119543c9f674	1223	hspi->TxXferSize = Size;
mbed_official	489:119543c9f674	1224	hspi->TxXferCount = Size;
mbed_official	489:119543c9f674	1225
mbed_official	489:119543c9f674	1226	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1227	hspi->TxISR = 0;
mbed_official	489:119543c9f674	1228	hspi->RxISR = 0;
mbed_official	489:119543c9f674	1229	hspi->pRxBuffPtr = NULL;
mbed_official	489:119543c9f674	1230	hspi->RxXferSize = 0;
mbed_official	489:119543c9f674	1231	hspi->RxXferCount = 0;
mbed_official	489:119543c9f674	1232
mbed_official	489:119543c9f674	1233	/* Configure communication direction : 1Line */
mbed_official	489:119543c9f674	1234	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	489:119543c9f674	1235	{
mbed_official	489:119543c9f674	1236	SPI_1LINE_TX(hspi);
mbed_official	489:119543c9f674	1237	}
mbed_official	489:119543c9f674	1238
mbed_official	489:119543c9f674	1239	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1240	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1241	{
mbed_official	489:119543c9f674	1242	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	1243	}
mbed_official	489:119543c9f674	1244
mbed_official	489:119543c9f674	1245	/* Set the SPI TxDMA Half transfer complete callback */
mbed_official	489:119543c9f674	1246	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
mbed_official	489:119543c9f674	1247
mbed_official	489:119543c9f674	1248	/* Set the SPI TxDMA transfer complete callback */
mbed_official	489:119543c9f674	1249	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	489:119543c9f674	1250
mbed_official	489:119543c9f674	1251	/* Set the DMA error callback */
mbed_official	489:119543c9f674	1252	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	489:119543c9f674	1253
mbed_official	489:119543c9f674	1254	/* Reset content of SPI RxDMA descriptor */
mbed_official	489:119543c9f674	1255	hspi->hdmarx->XferHalfCpltCallback = 0;
mbed_official	489:119543c9f674	1256	hspi->hdmarx->XferCpltCallback = 0;
mbed_official	489:119543c9f674	1257	hspi->hdmarx->XferErrorCallback = 0;
mbed_official	489:119543c9f674	1258
mbed_official	489:119543c9f674	1259	/* Enable the Tx DMA Channel */
mbed_official	489:119543c9f674	1260	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	489:119543c9f674	1261
mbed_official	489:119543c9f674	1262	/* Enable Tx DMA Request */
mbed_official	489:119543c9f674	1263	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1264
mbed_official	489:119543c9f674	1265	/* Process Unlocked */
mbed_official	489:119543c9f674	1266	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1267
mbed_official	489:119543c9f674	1268	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	1269	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	1270	{
mbed_official	489:119543c9f674	1271	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	1272	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	1273	}
mbed_official	489:119543c9f674	1274
mbed_official	489:119543c9f674	1275	return HAL_OK;
mbed_official	489:119543c9f674	1276	}
mbed_official	489:119543c9f674	1277	else
mbed_official	489:119543c9f674	1278	{
mbed_official	489:119543c9f674	1279	return HAL_BUSY;
mbed_official	489:119543c9f674	1280	}
mbed_official	489:119543c9f674	1281	}
mbed_official	489:119543c9f674	1282
mbed_official	489:119543c9f674	1283	/**
mbed_official	489:119543c9f674	1284	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	489:119543c9f674	1285	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1286	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1287	* @param pData: pointer to data buffer
mbed_official	489:119543c9f674	1288	* @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official	489:119543c9f674	1289	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	1290	* @retval HAL status
mbed_official	489:119543c9f674	1291	*/
mbed_official	489:119543c9f674	1292	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	489:119543c9f674	1293	{
mbed_official	489:119543c9f674	1294	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	489:119543c9f674	1295	{
mbed_official	489:119543c9f674	1296	if((pData == NULL) \|\| (Size == 0))
mbed_official	489:119543c9f674	1297	{
mbed_official	489:119543c9f674	1298	return HAL_ERROR;
mbed_official	489:119543c9f674	1299	}
mbed_official	489:119543c9f674	1300
mbed_official	489:119543c9f674	1301	/* Process Locked */
mbed_official	489:119543c9f674	1302	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	1303
mbed_official	489:119543c9f674	1304	/* Configure communication */
mbed_official	489:119543c9f674	1305	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	489:119543c9f674	1306	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	1307
mbed_official	489:119543c9f674	1308	hspi->pRxBuffPtr = pData;
mbed_official	489:119543c9f674	1309	hspi->RxXferSize = Size;
mbed_official	489:119543c9f674	1310	hspi->RxXferCount = Size;
mbed_official	489:119543c9f674	1311
mbed_official	489:119543c9f674	1312	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1313	hspi->RxISR = 0;
mbed_official	489:119543c9f674	1314	hspi->TxISR = 0;
mbed_official	489:119543c9f674	1315	hspi->pTxBuffPtr = NULL;
mbed_official	489:119543c9f674	1316	hspi->TxXferSize = 0;
mbed_official	489:119543c9f674	1317	hspi->TxXferCount = 0;
mbed_official	489:119543c9f674	1318
mbed_official	489:119543c9f674	1319	/* Configure communication direction : 1Line */
mbed_official	489:119543c9f674	1320	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	489:119543c9f674	1321	{
mbed_official	489:119543c9f674	1322	SPI_1LINE_RX(hspi);
mbed_official	489:119543c9f674	1323	}
mbed_official	489:119543c9f674	1324	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	489:119543c9f674	1325	{
mbed_official	489:119543c9f674	1326	/* Process Unlocked */
mbed_official	489:119543c9f674	1327	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1328
mbed_official	489:119543c9f674	1329	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	489:119543c9f674	1330	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official	489:119543c9f674	1331	}
mbed_official	489:119543c9f674	1332
mbed_official	489:119543c9f674	1333	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1334	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1335	{
mbed_official	489:119543c9f674	1336	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	1337	}
mbed_official	489:119543c9f674	1338
mbed_official	489:119543c9f674	1339	/* Set the SPI RxDMA Half transfer complete callback */
mbed_official	489:119543c9f674	1340	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official	489:119543c9f674	1341
mbed_official	489:119543c9f674	1342	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	489:119543c9f674	1343	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	489:119543c9f674	1344
mbed_official	489:119543c9f674	1345	/* Set the DMA error callback */
mbed_official	489:119543c9f674	1346	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	489:119543c9f674	1347
mbed_official	489:119543c9f674	1348	/* Reset content of SPI TxDMA descriptor */
mbed_official	489:119543c9f674	1349	hspi->hdmatx->XferHalfCpltCallback = 0;
mbed_official	489:119543c9f674	1350	hspi->hdmatx->XferCpltCallback = 0;
mbed_official	489:119543c9f674	1351	hspi->hdmatx->XferErrorCallback = 0;
mbed_official	489:119543c9f674	1352
mbed_official	489:119543c9f674	1353	/* Enable the Rx DMA Channel */
mbed_official	489:119543c9f674	1354	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	489:119543c9f674	1355
mbed_official	489:119543c9f674	1356	/* Enable Rx DMA Request */
mbed_official	489:119543c9f674	1357	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	1358
mbed_official	489:119543c9f674	1359	/* Process Unlocked */
mbed_official	489:119543c9f674	1360	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1361
mbed_official	489:119543c9f674	1362	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	1363	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	1364	{
mbed_official	489:119543c9f674	1365	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	1366	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	1367	}
mbed_official	489:119543c9f674	1368
mbed_official	489:119543c9f674	1369	return HAL_OK;
mbed_official	489:119543c9f674	1370	}
mbed_official	489:119543c9f674	1371	else
mbed_official	489:119543c9f674	1372	{
mbed_official	489:119543c9f674	1373	return HAL_BUSY;
mbed_official	489:119543c9f674	1374	}
mbed_official	489:119543c9f674	1375	}
mbed_official	489:119543c9f674	1376
mbed_official	489:119543c9f674	1377	/**
mbed_official	489:119543c9f674	1378	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	489:119543c9f674	1379	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1380	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1381	* @param pTxData: pointer to transmission data buffer
mbed_official	489:119543c9f674	1382	* @param pRxData: pointer to reception data buffer
mbed_official	489:119543c9f674	1383	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official	489:119543c9f674	1384	* @param Size: amount of data to be sent
mbed_official	489:119543c9f674	1385	* @retval HAL status
mbed_official	489:119543c9f674	1386	*/
mbed_official	489:119543c9f674	1387	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	489:119543c9f674	1388	{
mbed_official	489:119543c9f674	1389	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
mbed_official	489:119543c9f674	1390	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	489:119543c9f674	1391	{
mbed_official	489:119543c9f674	1392	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	489:119543c9f674	1393	{
mbed_official	489:119543c9f674	1394	return HAL_ERROR;
mbed_official	489:119543c9f674	1395	}
mbed_official	489:119543c9f674	1396
mbed_official	489:119543c9f674	1397	/* Check the parameters */
mbed_official	489:119543c9f674	1398	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	489:119543c9f674	1399
mbed_official	489:119543c9f674	1400	/* Process locked */
mbed_official	489:119543c9f674	1401	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	1402
mbed_official	489:119543c9f674	1403	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	489:119543c9f674	1404	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	489:119543c9f674	1405	{
mbed_official	489:119543c9f674	1406	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	489:119543c9f674	1407	}
mbed_official	489:119543c9f674	1408
mbed_official	489:119543c9f674	1409	/* Configure communication */
mbed_official	489:119543c9f674	1410	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	489:119543c9f674	1411
mbed_official	489:119543c9f674	1412	hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official	489:119543c9f674	1413	hspi->TxXferSize = Size;
mbed_official	489:119543c9f674	1414	hspi->TxXferCount = Size;
mbed_official	489:119543c9f674	1415
mbed_official	489:119543c9f674	1416	hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official	489:119543c9f674	1417	hspi->RxXferSize = Size;
mbed_official	489:119543c9f674	1418	hspi->RxXferCount = Size;
mbed_official	489:119543c9f674	1419
mbed_official	489:119543c9f674	1420	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1421	hspi->RxISR = 0;
mbed_official	489:119543c9f674	1422	hspi->TxISR = 0;
mbed_official	489:119543c9f674	1423
mbed_official	489:119543c9f674	1424	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1425	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1426	{
mbed_official	489:119543c9f674	1427	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	1428	}
mbed_official	489:119543c9f674	1429
mbed_official	489:119543c9f674	1430	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official	489:119543c9f674	1431	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	489:119543c9f674	1432	{
mbed_official	489:119543c9f674	1433	/* Set the SPI Rx DMA Half transfer complete callback */
mbed_official	489:119543c9f674	1434	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official	489:119543c9f674	1435
mbed_official	489:119543c9f674	1436	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	489:119543c9f674	1437	}
mbed_official	489:119543c9f674	1438	else
mbed_official	489:119543c9f674	1439	{
mbed_official	489:119543c9f674	1440	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
mbed_official	489:119543c9f674	1441	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
mbed_official	489:119543c9f674	1442
mbed_official	489:119543c9f674	1443	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	489:119543c9f674	1444	}
mbed_official	489:119543c9f674	1445
mbed_official	489:119543c9f674	1446	/* Set the DMA error callback */
mbed_official	489:119543c9f674	1447	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	489:119543c9f674	1448
mbed_official	489:119543c9f674	1449	/* Enable the Rx DMA Channel */
mbed_official	489:119543c9f674	1450	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	489:119543c9f674	1451
mbed_official	489:119543c9f674	1452	/* Enable Rx DMA Request */
mbed_official	489:119543c9f674	1453	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	1454
mbed_official	489:119543c9f674	1455	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official	489:119543c9f674	1456	is performed in DMA reception complete callback */
mbed_official	489:119543c9f674	1457	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	489:119543c9f674	1458	{
mbed_official	489:119543c9f674	1459	/* Set the DMA error callback */
mbed_official	489:119543c9f674	1460	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	489:119543c9f674	1461	}
mbed_official	489:119543c9f674	1462	else
mbed_official	489:119543c9f674	1463	{
mbed_official	489:119543c9f674	1464	hspi->hdmatx->XferErrorCallback = NULL;
mbed_official	489:119543c9f674	1465	}
mbed_official	489:119543c9f674	1466
mbed_official	489:119543c9f674	1467	/* Enable the Tx DMA Channel */
mbed_official	489:119543c9f674	1468	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	489:119543c9f674	1469
mbed_official	489:119543c9f674	1470	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	1471	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	489:119543c9f674	1472	{
mbed_official	489:119543c9f674	1473	/* Enable SPI peripheral */
mbed_official	489:119543c9f674	1474	__HAL_SPI_ENABLE(hspi);
mbed_official	489:119543c9f674	1475	}
mbed_official	489:119543c9f674	1476
mbed_official	489:119543c9f674	1477	/* Enable Tx DMA Request */
mbed_official	489:119543c9f674	1478	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1479
mbed_official	489:119543c9f674	1480	/* Process Unlocked */
mbed_official	489:119543c9f674	1481	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1482
mbed_official	489:119543c9f674	1483	return HAL_OK;
mbed_official	489:119543c9f674	1484	}
mbed_official	489:119543c9f674	1485	else
mbed_official	489:119543c9f674	1486	{
mbed_official	489:119543c9f674	1487	return HAL_BUSY;
mbed_official	489:119543c9f674	1488	}
mbed_official	489:119543c9f674	1489	}
mbed_official	489:119543c9f674	1490
mbed_official	489:119543c9f674	1491
mbed_official	489:119543c9f674	1492	/**
mbed_official	489:119543c9f674	1493	* @brief Pauses the DMA Transfer.
mbed_official	489:119543c9f674	1494	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1495	* the configuration information for the specified SPI module.
mbed_official	489:119543c9f674	1496	* @retval HAL status
mbed_official	489:119543c9f674	1497	*/
mbed_official	489:119543c9f674	1498	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1499	{
mbed_official	489:119543c9f674	1500	/* Process Locked */
mbed_official	489:119543c9f674	1501	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	1502
mbed_official	489:119543c9f674	1503	/* Disable the SPI DMA Tx & Rx requests */
mbed_official	489:119543c9f674	1504	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1505	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	1506
mbed_official	489:119543c9f674	1507	/* Process Unlocked */
mbed_official	489:119543c9f674	1508	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1509
mbed_official	489:119543c9f674	1510	return HAL_OK;
mbed_official	489:119543c9f674	1511	}
mbed_official	489:119543c9f674	1512
mbed_official	489:119543c9f674	1513	/**
mbed_official	489:119543c9f674	1514	* @brief Resumes the DMA Transfer.
mbed_official	489:119543c9f674	1515	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1516	* the configuration information for the specified SPI module.
mbed_official	489:119543c9f674	1517	* @retval HAL status
mbed_official	489:119543c9f674	1518	*/
mbed_official	489:119543c9f674	1519	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1520	{
mbed_official	489:119543c9f674	1521	/* Process Locked */
mbed_official	489:119543c9f674	1522	__HAL_LOCK(hspi);
mbed_official	489:119543c9f674	1523
mbed_official	489:119543c9f674	1524	/* Enable the SPI DMA Tx & Rx requests */
mbed_official	489:119543c9f674	1525	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1526	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	1527
mbed_official	489:119543c9f674	1528	/* Process Unlocked */
mbed_official	489:119543c9f674	1529	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	1530
mbed_official	489:119543c9f674	1531	return HAL_OK;
mbed_official	489:119543c9f674	1532	}
mbed_official	489:119543c9f674	1533
mbed_official	489:119543c9f674	1534	/**
mbed_official	489:119543c9f674	1535	* @brief Stops the DMA Transfer.
mbed_official	489:119543c9f674	1536	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1537	* the configuration information for the specified SPI module.
mbed_official	489:119543c9f674	1538	* @retval HAL status
mbed_official	489:119543c9f674	1539	*/
mbed_official	489:119543c9f674	1540	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1541	{
mbed_official	489:119543c9f674	1542	/* The Lock is not implemented on this API to allow the user application
mbed_official	489:119543c9f674	1543	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
mbed_official	489:119543c9f674	1544	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
mbed_official	489:119543c9f674	1545	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
mbed_official	489:119543c9f674	1546	*/
mbed_official	489:119543c9f674	1547
mbed_official	489:119543c9f674	1548	/* Abort the SPI DMA tx Channel */
mbed_official	489:119543c9f674	1549	if(hspi->hdmatx != NULL)
mbed_official	489:119543c9f674	1550	{
mbed_official	489:119543c9f674	1551	HAL_DMA_Abort(hspi->hdmatx);
mbed_official	489:119543c9f674	1552	}
mbed_official	489:119543c9f674	1553	/* Abort the SPI DMA rx Channel */
mbed_official	489:119543c9f674	1554	if(hspi->hdmarx != NULL)
mbed_official	489:119543c9f674	1555	{
mbed_official	489:119543c9f674	1556	HAL_DMA_Abort(hspi->hdmarx);
mbed_official	489:119543c9f674	1557	}
mbed_official	489:119543c9f674	1558
mbed_official	489:119543c9f674	1559	/* Disable the SPI DMA Tx & Rx requests */
mbed_official	489:119543c9f674	1560	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1561	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	1562
mbed_official	489:119543c9f674	1563	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1564
mbed_official	489:119543c9f674	1565	return HAL_OK;
mbed_official	489:119543c9f674	1566	}
mbed_official	489:119543c9f674	1567
mbed_official	489:119543c9f674	1568	/**
mbed_official	489:119543c9f674	1569	* @brief This function handles SPI interrupt request.
mbed_official	489:119543c9f674	1570	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1571	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1572	* @retval None
mbed_official	489:119543c9f674	1573	*/
mbed_official	489:119543c9f674	1574	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1575	{
mbed_official	489:119543c9f674	1576	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official	489:119543c9f674	1577	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
mbed_official	489:119543c9f674	1578	{
mbed_official	489:119543c9f674	1579	hspi->RxISR(hspi);
mbed_official	489:119543c9f674	1580	return;
mbed_official	489:119543c9f674	1581	}
mbed_official	489:119543c9f674	1582
mbed_official	489:119543c9f674	1583	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	489:119543c9f674	1584	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
mbed_official	489:119543c9f674	1585	{
mbed_official	489:119543c9f674	1586	hspi->TxISR(hspi);
mbed_official	489:119543c9f674	1587	return;
mbed_official	489:119543c9f674	1588	}
mbed_official	489:119543c9f674	1589
mbed_official	489:119543c9f674	1590	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official	489:119543c9f674	1591	{
mbed_official	489:119543c9f674	1592	/* SPI CRC error interrupt occurred ---------------------------------------*/
mbed_official	489:119543c9f674	1593	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	489:119543c9f674	1594	{
mbed_official	489:119543c9f674	1595	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	1596	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	489:119543c9f674	1597	}
mbed_official	489:119543c9f674	1598	/* SPI Mode Fault error interrupt occurred --------------------------------*/
mbed_official	489:119543c9f674	1599	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	489:119543c9f674	1600	{
mbed_official	489:119543c9f674	1601	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
mbed_official	489:119543c9f674	1602	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	489:119543c9f674	1603	}
mbed_official	489:119543c9f674	1604
mbed_official	489:119543c9f674	1605	/* SPI Overrun error interrupt occurred -----------------------------------*/
mbed_official	489:119543c9f674	1606	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	489:119543c9f674	1607	{
mbed_official	489:119543c9f674	1608	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	489:119543c9f674	1609	{
mbed_official	489:119543c9f674	1610	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
mbed_official	489:119543c9f674	1611	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	489:119543c9f674	1612	}
mbed_official	489:119543c9f674	1613	}
mbed_official	489:119543c9f674	1614
mbed_official	489:119543c9f674	1615	/* Call the Error call Back in case of Errors */
mbed_official	489:119543c9f674	1616	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official	489:119543c9f674	1617	{
mbed_official	489:119543c9f674	1618	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
mbed_official	489:119543c9f674	1619	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1620	HAL_SPI_ErrorCallback(hspi);
mbed_official	489:119543c9f674	1621	}
mbed_official	489:119543c9f674	1622	}
mbed_official	489:119543c9f674	1623	}
mbed_official	489:119543c9f674	1624
mbed_official	489:119543c9f674	1625	/**
mbed_official	489:119543c9f674	1626	* @brief Tx Transfer completed callbacks
mbed_official	489:119543c9f674	1627	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1628	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1629	* @retval None
mbed_official	489:119543c9f674	1630	*/
mbed_official	489:119543c9f674	1631	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1632	{
mbed_official	489:119543c9f674	1633	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	1634	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	489:119543c9f674	1635	*/
mbed_official	489:119543c9f674	1636	}
mbed_official	489:119543c9f674	1637
mbed_official	489:119543c9f674	1638	/**
mbed_official	489:119543c9f674	1639	* @brief Rx Transfer completed callbacks
mbed_official	489:119543c9f674	1640	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1641	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1642	* @retval None
mbed_official	489:119543c9f674	1643	*/
mbed_official	489:119543c9f674	1644	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1645	{
mbed_official	489:119543c9f674	1646	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	1647	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official	489:119543c9f674	1648	*/
mbed_official	489:119543c9f674	1649	}
mbed_official	489:119543c9f674	1650
mbed_official	489:119543c9f674	1651	/**
mbed_official	489:119543c9f674	1652	* @brief Tx and Rx Transfer completed callbacks
mbed_official	489:119543c9f674	1653	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1654	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1655	* @retval None
mbed_official	489:119543c9f674	1656	*/
mbed_official	489:119543c9f674	1657	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1658	{
mbed_official	489:119543c9f674	1659	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	1660	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official	489:119543c9f674	1661	*/
mbed_official	489:119543c9f674	1662	}
mbed_official	489:119543c9f674	1663
mbed_official	489:119543c9f674	1664	/**
mbed_official	489:119543c9f674	1665	* @brief Tx Half Transfer completed callbacks
mbed_official	489:119543c9f674	1666	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1667	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1668	* @retval None
mbed_official	489:119543c9f674	1669	*/
mbed_official	489:119543c9f674	1670	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1671	{
mbed_official	489:119543c9f674	1672	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	1673	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
mbed_official	489:119543c9f674	1674	*/
mbed_official	489:119543c9f674	1675	}
mbed_official	489:119543c9f674	1676
mbed_official	489:119543c9f674	1677	/**
mbed_official	489:119543c9f674	1678	* @brief Rx Half Transfer completed callbacks
mbed_official	489:119543c9f674	1679	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1680	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1681	* @retval None
mbed_official	489:119543c9f674	1682	*/
mbed_official	489:119543c9f674	1683	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1684	{
mbed_official	489:119543c9f674	1685	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	1686	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
mbed_official	489:119543c9f674	1687	*/
mbed_official	489:119543c9f674	1688	}
mbed_official	489:119543c9f674	1689
mbed_official	489:119543c9f674	1690	/**
mbed_official	489:119543c9f674	1691	* @brief Tx and Rx Transfer completed callbacks
mbed_official	489:119543c9f674	1692	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1693	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1694	* @retval None
mbed_official	489:119543c9f674	1695	*/
mbed_official	489:119543c9f674	1696	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1697	{
mbed_official	489:119543c9f674	1698	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	1699	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
mbed_official	489:119543c9f674	1700	*/
mbed_official	489:119543c9f674	1701	}
mbed_official	489:119543c9f674	1702
mbed_official	489:119543c9f674	1703	/**
mbed_official	489:119543c9f674	1704	* @brief SPI error callbacks
mbed_official	489:119543c9f674	1705	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1706	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1707	* @retval None
mbed_official	489:119543c9f674	1708	*/
mbed_official	489:119543c9f674	1709	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1710	{
mbed_official	489:119543c9f674	1711	/* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	1712	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official	489:119543c9f674	1713	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official	489:119543c9f674	1714	and user can use HAL_SPI_GetError() API to check the latest error occurred.
mbed_official	489:119543c9f674	1715	*/
mbed_official	489:119543c9f674	1716	}
mbed_official	489:119543c9f674	1717
mbed_official	489:119543c9f674	1718	/**
mbed_official	489:119543c9f674	1719	* @}
mbed_official	489:119543c9f674	1720	*/
mbed_official	489:119543c9f674	1721
mbed_official	489:119543c9f674	1722	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
mbed_official	489:119543c9f674	1723	* @brief SPI control functions
mbed_official	489:119543c9f674	1724	*
mbed_official	489:119543c9f674	1725	@verbatim
mbed_official	489:119543c9f674	1726	===============================================================================
mbed_official	489:119543c9f674	1727	##### Peripheral State and Errors functions #####
mbed_official	489:119543c9f674	1728	===============================================================================
mbed_official	489:119543c9f674	1729	[..]
mbed_official	489:119543c9f674	1730	This subsection provides a set of functions allowing to control the SPI.
mbed_official	489:119543c9f674	1731	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official	489:119543c9f674	1732	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official	489:119543c9f674	1733	@endverbatim
mbed_official	489:119543c9f674	1734	* @{
mbed_official	489:119543c9f674	1735	*/
mbed_official	489:119543c9f674	1736
mbed_official	489:119543c9f674	1737	/**
mbed_official	489:119543c9f674	1738	* @brief Return the SPI state
mbed_official	489:119543c9f674	1739	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1740	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1741	* @retval SPI state
mbed_official	489:119543c9f674	1742	*/
mbed_official	489:119543c9f674	1743	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1744	{
mbed_official	489:119543c9f674	1745	return hspi->State;
mbed_official	489:119543c9f674	1746	}
mbed_official	489:119543c9f674	1747
mbed_official	489:119543c9f674	1748	/**
mbed_official	489:119543c9f674	1749	* @brief Return the SPI error code
mbed_official	489:119543c9f674	1750	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1751	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1752	* @retval SPI Error Code
mbed_official	489:119543c9f674	1753	*/
mbed_official	489:119543c9f674	1754	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1755	{
mbed_official	489:119543c9f674	1756	return hspi->ErrorCode;
mbed_official	489:119543c9f674	1757	}
mbed_official	489:119543c9f674	1758
mbed_official	489:119543c9f674	1759	/**
mbed_official	489:119543c9f674	1760	* @}
mbed_official	489:119543c9f674	1761	*/
mbed_official	489:119543c9f674	1762
mbed_official	489:119543c9f674	1763	/**
mbed_official	489:119543c9f674	1764	* @}
mbed_official	489:119543c9f674	1765	*/
mbed_official	489:119543c9f674	1766
mbed_official	489:119543c9f674	1767
mbed_official	489:119543c9f674	1768
mbed_official	489:119543c9f674	1769	/** @addtogroup SPI_Private_Functions
mbed_official	489:119543c9f674	1770	* @{
mbed_official	489:119543c9f674	1771	*/
mbed_official	489:119543c9f674	1772
mbed_official	489:119543c9f674	1773
mbed_official	489:119543c9f674	1774	/**
mbed_official	489:119543c9f674	1775	* @brief Interrupt Handler to close Tx transfer
mbed_official	489:119543c9f674	1776	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1777	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1778	* @retval None
mbed_official	489:119543c9f674	1779	*/
mbed_official	489:119543c9f674	1780	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1781	{
mbed_official	489:119543c9f674	1782	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	1783	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	1784	{
mbed_official	489:119543c9f674	1785	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	1786	}
mbed_official	489:119543c9f674	1787
mbed_official	489:119543c9f674	1788	/* Disable TXE interrupt */
mbed_official	489:119543c9f674	1789	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	489:119543c9f674	1790
mbed_official	489:119543c9f674	1791	/* Disable ERR interrupt if Receive process is finished */
mbed_official	489:119543c9f674	1792	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official	489:119543c9f674	1793	{
mbed_official	489:119543c9f674	1794	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	489:119543c9f674	1795
mbed_official	489:119543c9f674	1796	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	489:119543c9f674	1797	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	1798	{
mbed_official	489:119543c9f674	1799	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	1800	}
mbed_official	489:119543c9f674	1801
mbed_official	489:119543c9f674	1802	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	489:119543c9f674	1803	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	489:119543c9f674	1804	{
mbed_official	489:119543c9f674	1805	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	489:119543c9f674	1806	}
mbed_official	489:119543c9f674	1807
mbed_official	489:119543c9f674	1808	/* Check if Errors has been detected during transfer */
mbed_official	489:119543c9f674	1809	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	489:119543c9f674	1810	{
mbed_official	489:119543c9f674	1811	/* Check if we are in Tx or in Rx/Tx Mode */
mbed_official	489:119543c9f674	1812	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	489:119543c9f674	1813	{
mbed_official	489:119543c9f674	1814	/* Set state to READY before run the Callback Complete */
mbed_official	489:119543c9f674	1815	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1816	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	489:119543c9f674	1817	}
mbed_official	489:119543c9f674	1818	else
mbed_official	489:119543c9f674	1819	{
mbed_official	489:119543c9f674	1820	/* Set state to READY before run the Callback Complete */
mbed_official	489:119543c9f674	1821	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1822	HAL_SPI_TxCpltCallback(hspi);
mbed_official	489:119543c9f674	1823	}
mbed_official	489:119543c9f674	1824	}
mbed_official	489:119543c9f674	1825	else
mbed_official	489:119543c9f674	1826	{
mbed_official	489:119543c9f674	1827	/* Set state to READY before run the Callback Complete */
mbed_official	489:119543c9f674	1828	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1829	/* Call Error call back in case of Error */
mbed_official	489:119543c9f674	1830	HAL_SPI_ErrorCallback(hspi);
mbed_official	489:119543c9f674	1831	}
mbed_official	489:119543c9f674	1832	}
mbed_official	489:119543c9f674	1833	}
mbed_official	489:119543c9f674	1834
mbed_official	489:119543c9f674	1835	/**
mbed_official	489:119543c9f674	1836	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official	489:119543c9f674	1837	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1838	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1839	* @retval None
mbed_official	489:119543c9f674	1840	*/
mbed_official	489:119543c9f674	1841	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1842	{
mbed_official	489:119543c9f674	1843	/* Transmit data in 8 Bit mode */
mbed_official	489:119543c9f674	1844	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	489:119543c9f674	1845	{
mbed_official	489:119543c9f674	1846	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	489:119543c9f674	1847	}
mbed_official	489:119543c9f674	1848	/* Transmit data in 16 Bit mode */
mbed_official	489:119543c9f674	1849	else
mbed_official	489:119543c9f674	1850	{
mbed_official	489:119543c9f674	1851	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	489:119543c9f674	1852	hspi->pTxBuffPtr+=2;
mbed_official	489:119543c9f674	1853	}
mbed_official	489:119543c9f674	1854	hspi->TxXferCount--;
mbed_official	489:119543c9f674	1855
mbed_official	489:119543c9f674	1856	if(hspi->TxXferCount == 0)
mbed_official	489:119543c9f674	1857	{
mbed_official	489:119543c9f674	1858	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1859	{
mbed_official	489:119543c9f674	1860	/* calculate and transfer CRC on Tx line */
mbed_official	489:119543c9f674	1861	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	1862	}
mbed_official	489:119543c9f674	1863	SPI_TxCloseIRQHandler(hspi);
mbed_official	489:119543c9f674	1864	}
mbed_official	489:119543c9f674	1865	}
mbed_official	489:119543c9f674	1866
mbed_official	489:119543c9f674	1867	/**
mbed_official	489:119543c9f674	1868	* @brief Interrupt Handler to close Rx transfer
mbed_official	489:119543c9f674	1869	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1870	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1871	* @retval None
mbed_official	489:119543c9f674	1872	*/
mbed_official	489:119543c9f674	1873	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1874	{
mbed_official	489:119543c9f674	1875	__IO uint16_t tmpreg = 0;
mbed_official	489:119543c9f674	1876
mbed_official	489:119543c9f674	1877	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	1878	{
mbed_official	489:119543c9f674	1879	/* Wait until RXNE flag is set to read CRC data */
mbed_official	489:119543c9f674	1880	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	1881	{
mbed_official	489:119543c9f674	1882	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	1883	}
mbed_official	489:119543c9f674	1884
mbed_official	489:119543c9f674	1885	/* Read CRC to reset RXNE flag */
mbed_official	489:119543c9f674	1886	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	1887	UNUSED(tmpreg);
mbed_official	489:119543c9f674	1888
mbed_official	489:119543c9f674	1889	/* Wait until RXNE flag is reset */
mbed_official	489:119543c9f674	1890	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	1891	{
mbed_official	489:119543c9f674	1892	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	1893	}
mbed_official	489:119543c9f674	1894
mbed_official	489:119543c9f674	1895	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	1896	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	489:119543c9f674	1897	{
mbed_official	489:119543c9f674	1898	/* Check if CRC error is valid or not (workaround to be applied or not) */
mbed_official	489:119543c9f674	1899	if ( (hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	489:119543c9f674	1900	\|\| (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) )
mbed_official	489:119543c9f674	1901	{
mbed_official	489:119543c9f674	1902	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	1903
mbed_official	489:119543c9f674	1904	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1905	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	1906	}
mbed_official	489:119543c9f674	1907	else
mbed_official	489:119543c9f674	1908	{
mbed_official	489:119543c9f674	1909	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	489:119543c9f674	1910	}
mbed_official	489:119543c9f674	1911	}
mbed_official	489:119543c9f674	1912	}
mbed_official	489:119543c9f674	1913
mbed_official	489:119543c9f674	1914	/* Disable RXNE interrupt */
mbed_official	489:119543c9f674	1915	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official	489:119543c9f674	1916
mbed_official	489:119543c9f674	1917	/* if Transmit process is finished */
mbed_official	489:119543c9f674	1918	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official	489:119543c9f674	1919	{
mbed_official	489:119543c9f674	1920	/* Disable ERR interrupt */
mbed_official	489:119543c9f674	1921	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	489:119543c9f674	1922
mbed_official	489:119543c9f674	1923	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	489:119543c9f674	1924	{
mbed_official	489:119543c9f674	1925	/* Disable SPI peripheral */
mbed_official	489:119543c9f674	1926	__HAL_SPI_DISABLE(hspi);
mbed_official	489:119543c9f674	1927	}
mbed_official	489:119543c9f674	1928
mbed_official	489:119543c9f674	1929	/* Check if Errors has been detected during transfer */
mbed_official	489:119543c9f674	1930	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	489:119543c9f674	1931	{
mbed_official	489:119543c9f674	1932	/* Check if we are in Rx or in Rx/Tx Mode */
mbed_official	489:119543c9f674	1933	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	489:119543c9f674	1934	{
mbed_official	489:119543c9f674	1935	/* Set state to READY before run the Callback Complete */
mbed_official	489:119543c9f674	1936	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1937	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	489:119543c9f674	1938	}
mbed_official	489:119543c9f674	1939	else
mbed_official	489:119543c9f674	1940	{
mbed_official	489:119543c9f674	1941	/* Set state to READY before run the Callback Complete */
mbed_official	489:119543c9f674	1942	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1943	HAL_SPI_RxCpltCallback(hspi);
mbed_official	489:119543c9f674	1944	}
mbed_official	489:119543c9f674	1945	}
mbed_official	489:119543c9f674	1946	else
mbed_official	489:119543c9f674	1947	{
mbed_official	489:119543c9f674	1948	/* Set state to READY before run the Callback Complete */
mbed_official	489:119543c9f674	1949	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	1950	/* Call Error call back in case of Error */
mbed_official	489:119543c9f674	1951	HAL_SPI_ErrorCallback(hspi);
mbed_official	489:119543c9f674	1952	}
mbed_official	489:119543c9f674	1953	}
mbed_official	489:119543c9f674	1954	}
mbed_official	489:119543c9f674	1955
mbed_official	489:119543c9f674	1956	/**
mbed_official	489:119543c9f674	1957	* @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official	489:119543c9f674	1958	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1959	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1960	* @retval None
mbed_official	489:119543c9f674	1961	*/
mbed_official	489:119543c9f674	1962	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1963	{
mbed_official	489:119543c9f674	1964	/* Receive data in 8 Bit mode */
mbed_official	489:119543c9f674	1965	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	489:119543c9f674	1966	{
mbed_official	489:119543c9f674	1967	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	489:119543c9f674	1968	}
mbed_official	489:119543c9f674	1969	/* Receive data in 16 Bit mode */
mbed_official	489:119543c9f674	1970	else
mbed_official	489:119543c9f674	1971	{
mbed_official	489:119543c9f674	1972	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	1973	hspi->pRxBuffPtr+=2;
mbed_official	489:119543c9f674	1974	}
mbed_official	489:119543c9f674	1975	hspi->RxXferCount--;
mbed_official	489:119543c9f674	1976
mbed_official	489:119543c9f674	1977	if(hspi->RxXferCount==0)
mbed_official	489:119543c9f674	1978	{
mbed_official	489:119543c9f674	1979	SPI_RxCloseIRQHandler(hspi);
mbed_official	489:119543c9f674	1980	}
mbed_official	489:119543c9f674	1981	}
mbed_official	489:119543c9f674	1982
mbed_official	489:119543c9f674	1983	/**
mbed_official	489:119543c9f674	1984	* @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official	489:119543c9f674	1985	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1986	* the configuration information for SPI module.
mbed_official	489:119543c9f674	1987	* @retval None
mbed_official	489:119543c9f674	1988	*/
mbed_official	489:119543c9f674	1989	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	1990	{
mbed_official	489:119543c9f674	1991	/* Receive data in 8 Bit mode */
mbed_official	489:119543c9f674	1992	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	489:119543c9f674	1993	{
mbed_official	489:119543c9f674	1994	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	489:119543c9f674	1995	}
mbed_official	489:119543c9f674	1996	/* Receive data in 16 Bit mode */
mbed_official	489:119543c9f674	1997	else
mbed_official	489:119543c9f674	1998	{
mbed_official	489:119543c9f674	1999	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	489:119543c9f674	2000	hspi->pRxBuffPtr+=2;
mbed_official	489:119543c9f674	2001	}
mbed_official	489:119543c9f674	2002	hspi->RxXferCount--;
mbed_official	489:119543c9f674	2003
mbed_official	489:119543c9f674	2004	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	2005	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official	489:119543c9f674	2006	{
mbed_official	489:119543c9f674	2007	/* Set CRC Next to calculate CRC on Rx side */
mbed_official	489:119543c9f674	2008	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	489:119543c9f674	2009	}
mbed_official	489:119543c9f674	2010
mbed_official	489:119543c9f674	2011	if(hspi->RxXferCount == 0)
mbed_official	489:119543c9f674	2012	{
mbed_official	489:119543c9f674	2013	SPI_RxCloseIRQHandler(hspi);
mbed_official	489:119543c9f674	2014	}
mbed_official	489:119543c9f674	2015	}
mbed_official	489:119543c9f674	2016
mbed_official	489:119543c9f674	2017	/**
mbed_official	489:119543c9f674	2018	* @brief DMA SPI transmit process complete callback
mbed_official	489:119543c9f674	2019	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2020	* the configuration information for the specified DMA module.
mbed_official	489:119543c9f674	2021	* @retval None
mbed_official	489:119543c9f674	2022	*/
mbed_official	489:119543c9f674	2023	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	489:119543c9f674	2024	{
mbed_official	489:119543c9f674	2025	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2026
mbed_official	489:119543c9f674	2027	/* DMA Normal Mode */
mbed_official	489:119543c9f674	2028	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
mbed_official	489:119543c9f674	2029	{
mbed_official	489:119543c9f674	2030	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	2031	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2032	{
mbed_official	489:119543c9f674	2033	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2034	}
mbed_official	489:119543c9f674	2035
mbed_official	489:119543c9f674	2036	/* Disable Tx DMA Request */
mbed_official	489:119543c9f674	2037	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	2038
mbed_official	489:119543c9f674	2039	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	489:119543c9f674	2040	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2041	{
mbed_official	489:119543c9f674	2042	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2043	}
mbed_official	489:119543c9f674	2044
mbed_official	489:119543c9f674	2045	hspi->TxXferCount = 0;
mbed_official	489:119543c9f674	2046	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	2047	}
mbed_official	489:119543c9f674	2048
mbed_official	489:119543c9f674	2049	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	489:119543c9f674	2050	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	489:119543c9f674	2051	{
mbed_official	489:119543c9f674	2052	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	489:119543c9f674	2053	}
mbed_official	489:119543c9f674	2054
mbed_official	489:119543c9f674	2055	/* Check if Errors has been detected during transfer */
mbed_official	489:119543c9f674	2056	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	489:119543c9f674	2057	{
mbed_official	489:119543c9f674	2058	HAL_SPI_ErrorCallback(hspi);
mbed_official	489:119543c9f674	2059	}
mbed_official	489:119543c9f674	2060	else
mbed_official	489:119543c9f674	2061	{
mbed_official	489:119543c9f674	2062	HAL_SPI_TxCpltCallback(hspi);
mbed_official	489:119543c9f674	2063	}
mbed_official	489:119543c9f674	2064	}
mbed_official	489:119543c9f674	2065
mbed_official	489:119543c9f674	2066	/**
mbed_official	489:119543c9f674	2067	* @brief DMA SPI receive process complete callback
mbed_official	489:119543c9f674	2068	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2069	* the configuration information for the specified DMA module.
mbed_official	489:119543c9f674	2070	* @retval None
mbed_official	489:119543c9f674	2071	*/
mbed_official	489:119543c9f674	2072	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	489:119543c9f674	2073	{
mbed_official	489:119543c9f674	2074	__IO uint16_t tmpreg = 0;
mbed_official	489:119543c9f674	2075	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2076
mbed_official	489:119543c9f674	2077	/* DMA Normal mode */
mbed_official	489:119543c9f674	2078	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
mbed_official	489:119543c9f674	2079	{
mbed_official	489:119543c9f674	2080	/* Disable Rx DMA Request */
mbed_official	489:119543c9f674	2081	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	2082
mbed_official	489:119543c9f674	2083	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
mbed_official	489:119543c9f674	2084	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	2085
mbed_official	489:119543c9f674	2086	/* CRC Calculation handling */
mbed_official	489:119543c9f674	2087	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	2088	{
mbed_official	489:119543c9f674	2089	/* Wait until RXNE flag is set (CRC ready) */
mbed_official	489:119543c9f674	2090	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2091	{
mbed_official	489:119543c9f674	2092	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2093	}
mbed_official	489:119543c9f674	2094
mbed_official	489:119543c9f674	2095	/* Read CRC */
mbed_official	489:119543c9f674	2096	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	2097	UNUSED(tmpreg);
mbed_official	489:119543c9f674	2098
mbed_official	489:119543c9f674	2099	/* Wait until RXNE flag is reset */
mbed_official	489:119543c9f674	2100	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2101	{
mbed_official	489:119543c9f674	2102	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2103	}
mbed_official	489:119543c9f674	2104
mbed_official	489:119543c9f674	2105	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	2106	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	489:119543c9f674	2107	{
mbed_official	489:119543c9f674	2108	/* Check if CRC error is valid or not (workaround to be applied or not) */
mbed_official	489:119543c9f674	2109	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
mbed_official	489:119543c9f674	2110	{
mbed_official	489:119543c9f674	2111	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	2112
mbed_official	489:119543c9f674	2113	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	2114	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	2115	}
mbed_official	489:119543c9f674	2116	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	489:119543c9f674	2117	}
mbed_official	489:119543c9f674	2118	}
mbed_official	489:119543c9f674	2119
mbed_official	489:119543c9f674	2120	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	489:119543c9f674	2121	{
mbed_official	489:119543c9f674	2122	/* Disable SPI peripheral */
mbed_official	489:119543c9f674	2123	__HAL_SPI_DISABLE(hspi);
mbed_official	489:119543c9f674	2124	}
mbed_official	489:119543c9f674	2125
mbed_official	489:119543c9f674	2126	hspi->RxXferCount = 0;
mbed_official	489:119543c9f674	2127	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	2128
mbed_official	489:119543c9f674	2129	/* Check if Errors has been detected during transfer */
mbed_official	489:119543c9f674	2130	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	489:119543c9f674	2131	{
mbed_official	489:119543c9f674	2132	HAL_SPI_ErrorCallback(hspi);
mbed_official	489:119543c9f674	2133	}
mbed_official	489:119543c9f674	2134	else
mbed_official	489:119543c9f674	2135	{
mbed_official	489:119543c9f674	2136	HAL_SPI_RxCpltCallback(hspi);
mbed_official	489:119543c9f674	2137	}
mbed_official	489:119543c9f674	2138	}
mbed_official	489:119543c9f674	2139	else
mbed_official	489:119543c9f674	2140	{
mbed_official	489:119543c9f674	2141	HAL_SPI_RxCpltCallback(hspi);
mbed_official	489:119543c9f674	2142	}
mbed_official	489:119543c9f674	2143	}
mbed_official	489:119543c9f674	2144
mbed_official	489:119543c9f674	2145	/**
mbed_official	489:119543c9f674	2146	* @brief DMA SPI transmit receive process complete callback
mbed_official	489:119543c9f674	2147	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2148	* the configuration information for the specified DMA module.
mbed_official	489:119543c9f674	2149	* @retval None
mbed_official	489:119543c9f674	2150	*/
mbed_official	489:119543c9f674	2151	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	489:119543c9f674	2152	{
mbed_official	489:119543c9f674	2153	__IO uint16_t tmpreg = 0;
mbed_official	489:119543c9f674	2154
mbed_official	489:119543c9f674	2155	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2156
mbed_official	489:119543c9f674	2157	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
mbed_official	489:119543c9f674	2158	{
mbed_official	489:119543c9f674	2159	/* CRC Calculation handling */
mbed_official	489:119543c9f674	2160	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	2161	{
mbed_official	489:119543c9f674	2162	/* Check if CRC is done on going (RXNE flag set) */
mbed_official	489:119543c9f674	2163	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official	489:119543c9f674	2164	{
mbed_official	489:119543c9f674	2165	/* Wait until RXNE flag is set to send data */
mbed_official	489:119543c9f674	2166	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2167	{
mbed_official	489:119543c9f674	2168	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2169	}
mbed_official	489:119543c9f674	2170	}
mbed_official	489:119543c9f674	2171	/* Read CRC */
mbed_official	489:119543c9f674	2172	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	2173	UNUSED(tmpreg);
mbed_official	489:119543c9f674	2174
mbed_official	489:119543c9f674	2175	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	2176	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	489:119543c9f674	2177	{
mbed_official	489:119543c9f674	2178	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	2179	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	489:119543c9f674	2180	}
mbed_official	489:119543c9f674	2181	}
mbed_official	489:119543c9f674	2182
mbed_official	489:119543c9f674	2183	/* Wait until TXE flag is set to send data */
mbed_official	489:119543c9f674	2184	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2185	{
mbed_official	489:119543c9f674	2186	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2187	}
mbed_official	489:119543c9f674	2188
mbed_official	489:119543c9f674	2189	/* Disable Tx DMA Request */
mbed_official	489:119543c9f674	2190	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	2191
mbed_official	489:119543c9f674	2192	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	489:119543c9f674	2193	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2194	{
mbed_official	489:119543c9f674	2195	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2196	}
mbed_official	489:119543c9f674	2197
mbed_official	489:119543c9f674	2198	/* Disable Rx DMA Request */
mbed_official	489:119543c9f674	2199	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	2200
mbed_official	489:119543c9f674	2201	hspi->TxXferCount = 0;
mbed_official	489:119543c9f674	2202	hspi->RxXferCount = 0;
mbed_official	489:119543c9f674	2203
mbed_official	489:119543c9f674	2204	hspi->State = HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	2205
mbed_official	489:119543c9f674	2206	/* Check if Errors has been detected during transfer */
mbed_official	489:119543c9f674	2207	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	489:119543c9f674	2208	{
mbed_official	489:119543c9f674	2209	HAL_SPI_ErrorCallback(hspi);
mbed_official	489:119543c9f674	2210	}
mbed_official	489:119543c9f674	2211	else
mbed_official	489:119543c9f674	2212	{
mbed_official	489:119543c9f674	2213	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	489:119543c9f674	2214	}
mbed_official	489:119543c9f674	2215	}
mbed_official	489:119543c9f674	2216	else
mbed_official	489:119543c9f674	2217	{
mbed_official	489:119543c9f674	2218	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	489:119543c9f674	2219	}
mbed_official	489:119543c9f674	2220	}
mbed_official	489:119543c9f674	2221
mbed_official	489:119543c9f674	2222	/**
mbed_official	489:119543c9f674	2223	* @brief DMA SPI half transmit process complete callback
mbed_official	489:119543c9f674	2224	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2225	* the configuration information for the specified DMA module.
mbed_official	489:119543c9f674	2226	* @retval None
mbed_official	489:119543c9f674	2227	*/
mbed_official	489:119543c9f674	2228	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	489:119543c9f674	2229	{
mbed_official	489:119543c9f674	2230	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2231
mbed_official	489:119543c9f674	2232	HAL_SPI_TxHalfCpltCallback(hspi);
mbed_official	489:119543c9f674	2233	}
mbed_official	489:119543c9f674	2234
mbed_official	489:119543c9f674	2235	/**
mbed_official	489:119543c9f674	2236	* @brief DMA SPI half receive process complete callback
mbed_official	489:119543c9f674	2237	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2238	* the configuration information for the specified DMA module.
mbed_official	489:119543c9f674	2239	* @retval None
mbed_official	489:119543c9f674	2240	*/
mbed_official	489:119543c9f674	2241	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	489:119543c9f674	2242	{
mbed_official	489:119543c9f674	2243	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2244
mbed_official	489:119543c9f674	2245	HAL_SPI_RxHalfCpltCallback(hspi);
mbed_official	489:119543c9f674	2246	}
mbed_official	489:119543c9f674	2247
mbed_official	489:119543c9f674	2248	/**
mbed_official	489:119543c9f674	2249	* @brief DMA SPI Half transmit receive process complete callback
mbed_official	489:119543c9f674	2250	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2251	* the configuration information for the specified DMA module.
mbed_official	489:119543c9f674	2252	* @retval None
mbed_official	489:119543c9f674	2253	*/
mbed_official	489:119543c9f674	2254	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	489:119543c9f674	2255	{
mbed_official	489:119543c9f674	2256	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2257
mbed_official	489:119543c9f674	2258	HAL_SPI_TxRxHalfCpltCallback(hspi);
mbed_official	489:119543c9f674	2259	}
mbed_official	489:119543c9f674	2260
mbed_official	489:119543c9f674	2261	/**
mbed_official	489:119543c9f674	2262	* @brief DMA SPI communication error callback
mbed_official	489:119543c9f674	2263	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2264	* the configuration information for the specified DMA module.
mbed_official	489:119543c9f674	2265	* @retval None
mbed_official	489:119543c9f674	2266	*/
mbed_official	489:119543c9f674	2267	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	489:119543c9f674	2268	{
mbed_official	489:119543c9f674	2269	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2270	hspi->TxXferCount = 0;
mbed_official	489:119543c9f674	2271	hspi->RxXferCount = 0;
mbed_official	489:119543c9f674	2272	hspi->State= HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	2273	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
mbed_official	489:119543c9f674	2274	HAL_SPI_ErrorCallback(hspi);
mbed_official	489:119543c9f674	2275	}
mbed_official	489:119543c9f674	2276
mbed_official	489:119543c9f674	2277	/**
mbed_official	489:119543c9f674	2278	* @brief This function handles SPI Communication Timeout.
mbed_official	489:119543c9f674	2279	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2280	* the configuration information for SPI module.
mbed_official	489:119543c9f674	2281	* @param Flag: SPI flag to check
mbed_official	489:119543c9f674	2282	* @param Status: Flag status to check: RESET or set
mbed_official	489:119543c9f674	2283	* @param Timeout: Timeout duration
mbed_official	489:119543c9f674	2284	* @retval HAL status
mbed_official	489:119543c9f674	2285	*/
mbed_official	489:119543c9f674	2286	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	489:119543c9f674	2287	{
mbed_official	489:119543c9f674	2288	uint32_t tickstart = 0;
mbed_official	489:119543c9f674	2289
mbed_official	489:119543c9f674	2290	/* Get tick */
mbed_official	489:119543c9f674	2291	tickstart = HAL_GetTick();
mbed_official	489:119543c9f674	2292
mbed_official	489:119543c9f674	2293	/* Wait until flag is set */
mbed_official	489:119543c9f674	2294	if(Status == RESET)
mbed_official	489:119543c9f674	2295	{
mbed_official	489:119543c9f674	2296	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official	489:119543c9f674	2297	{
mbed_official	489:119543c9f674	2298	if(Timeout != HAL_MAX_DELAY)
mbed_official	489:119543c9f674	2299	{
mbed_official	489:119543c9f674	2300	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
mbed_official	489:119543c9f674	2301	{
mbed_official	489:119543c9f674	2302	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	489:119543c9f674	2303	on both master and slave sides in order to resynchronize the master
mbed_official	489:119543c9f674	2304	and slave for their respective CRC calculation */
mbed_official	489:119543c9f674	2305
mbed_official	489:119543c9f674	2306	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	489:119543c9f674	2307	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	489:119543c9f674	2308
mbed_official	489:119543c9f674	2309	/* Disable SPI peripheral */
mbed_official	489:119543c9f674	2310	__HAL_SPI_DISABLE(hspi);
mbed_official	489:119543c9f674	2311
mbed_official	489:119543c9f674	2312	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	2313	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	2314	{
mbed_official	489:119543c9f674	2315	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	2316	}
mbed_official	489:119543c9f674	2317
mbed_official	489:119543c9f674	2318	hspi->State= HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	2319
mbed_official	489:119543c9f674	2320	/* Process Unlocked */
mbed_official	489:119543c9f674	2321	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	2322
mbed_official	489:119543c9f674	2323	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	2324	}
mbed_official	489:119543c9f674	2325	}
mbed_official	489:119543c9f674	2326	}
mbed_official	489:119543c9f674	2327	}
mbed_official	489:119543c9f674	2328	else
mbed_official	489:119543c9f674	2329	{
mbed_official	489:119543c9f674	2330	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official	489:119543c9f674	2331	{
mbed_official	489:119543c9f674	2332	if(Timeout != HAL_MAX_DELAY)
mbed_official	489:119543c9f674	2333	{
mbed_official	489:119543c9f674	2334	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
mbed_official	489:119543c9f674	2335	{
mbed_official	489:119543c9f674	2336	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	489:119543c9f674	2337	on both master and slave sides in order to resynchronize the master
mbed_official	489:119543c9f674	2338	and slave for their respective CRC calculation */
mbed_official	489:119543c9f674	2339
mbed_official	489:119543c9f674	2340	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	489:119543c9f674	2341	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	489:119543c9f674	2342
mbed_official	489:119543c9f674	2343	/* Disable SPI peripheral */
mbed_official	489:119543c9f674	2344	__HAL_SPI_DISABLE(hspi);
mbed_official	489:119543c9f674	2345
mbed_official	489:119543c9f674	2346	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	2347	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	2348	{
mbed_official	489:119543c9f674	2349	SPI_RESET_CRC(hspi);
mbed_official	489:119543c9f674	2350	}
mbed_official	489:119543c9f674	2351
mbed_official	489:119543c9f674	2352	hspi->State= HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	2353
mbed_official	489:119543c9f674	2354	/* Process Unlocked */
mbed_official	489:119543c9f674	2355	__HAL_UNLOCK(hspi);
mbed_official	489:119543c9f674	2356
mbed_official	489:119543c9f674	2357	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	2358	}
mbed_official	489:119543c9f674	2359	}
mbed_official	489:119543c9f674	2360	}
mbed_official	489:119543c9f674	2361	}
mbed_official	489:119543c9f674	2362	return HAL_OK;
mbed_official	489:119543c9f674	2363	}
mbed_official	489:119543c9f674	2364
mbed_official	489:119543c9f674	2365	/**
mbed_official	489:119543c9f674	2366	* @}
mbed_official	489:119543c9f674	2367	*/
mbed_official	489:119543c9f674	2368
mbed_official	489:119543c9f674	2369	/** @addtogroup SPI_Private_Functions
mbed_official	489:119543c9f674	2370	* @{
mbed_official	489:119543c9f674	2371	*/
mbed_official	489:119543c9f674	2372
mbed_official	489:119543c9f674	2373	/**
mbed_official	489:119543c9f674	2374	* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
mbed_official	489:119543c9f674	2375	* according to SPI instance, Device type, and revision ID.
mbed_official	489:119543c9f674	2376	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	2377	* the configuration information for SPI module.
mbed_official	489:119543c9f674	2378	* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
mbed_official	489:119543c9f674	2379	*/
mbed_official	489:119543c9f674	2380	__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
mbed_official	489:119543c9f674	2381	{
mbed_official	489:119543c9f674	2382	return (SPI_VALID_CRC_ERROR);
mbed_official	489:119543c9f674	2383	}
mbed_official	489:119543c9f674	2384	/**
mbed_official	489:119543c9f674	2385	* @}
mbed_official	489:119543c9f674	2386	*/
mbed_official	489:119543c9f674	2387
mbed_official	489:119543c9f674	2388
mbed_official	489:119543c9f674	2389	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	489:119543c9f674	2390	/**
mbed_official	489:119543c9f674	2391	* @}
mbed_official	489:119543c9f674	2392	*/
mbed_official	489:119543c9f674	2393
mbed_official	489:119543c9f674	2394	/**
mbed_official	489:119543c9f674	2395	* @}
mbed_official	489:119543c9f674	2396	*/
mbed_official	489:119543c9f674	2397
mbed_official	489:119543c9f674	2398	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	14 Jul 2015
Imports:	0
Forks:	0
Commits:	591
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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c@590:0835b0fc9a03, 2015-07-14 (annotated)

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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c@590:0835b0fc9a03, 2015-07-14 (annotated)

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