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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@382:ee426a420dbb, 2014-11-03 (annotated)

Committer:: mbed_official
Date:: Mon Nov 03 10:45:07 2014 +0000
Revision:: 382:ee426a420dbb
Parent:: targets/cmsis/TARGET_STM/TARGET_DISCO_L053C8/stm32l0xx_hal_rcc.h@376:cb4d9db17537
Child:: 384:ef87175507f1

Synchronized with git revision d54467eb07f62efd9ccdf44f1ede7fe1c1b0cf83



Full URL: https://github.com/mbedmicro/mbed/commit/d54467eb07f62efd9ccdf44f1ede7fe1c1b0cf83/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	376:cb4d9db17537	1	/**
mbed_official	376:cb4d9db17537	2	******************************************************************************
mbed_official	376:cb4d9db17537	3	* @file stm32l0xx_hal_rcc.h
mbed_official	376:cb4d9db17537	4	* @author MCD Application Team
mbed_official	376:cb4d9db17537	5	* @version V1.1.0
mbed_official	376:cb4d9db17537	6	* @date 18-June-2014
mbed_official	376:cb4d9db17537	7	* @brief Header file of RCC HAL module.
mbed_official	376:cb4d9db17537	8	******************************************************************************
mbed_official	376:cb4d9db17537	9	* @attention
mbed_official	376:cb4d9db17537	10	*
mbed_official	376:cb4d9db17537	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	376:cb4d9db17537	12	*
mbed_official	376:cb4d9db17537	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	376:cb4d9db17537	14	* are permitted provided that the following conditions are met:
mbed_official	376:cb4d9db17537	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	376:cb4d9db17537	16	* this list of conditions and the following disclaimer.
mbed_official	376:cb4d9db17537	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	376:cb4d9db17537	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	376:cb4d9db17537	19	* and/or other materials provided with the distribution.
mbed_official	376:cb4d9db17537	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	376:cb4d9db17537	21	* may be used to endorse or promote products derived from this software
mbed_official	376:cb4d9db17537	22	* without specific prior written permission.
mbed_official	376:cb4d9db17537	23	*
mbed_official	376:cb4d9db17537	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	376:cb4d9db17537	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	376:cb4d9db17537	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	376:cb4d9db17537	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	376:cb4d9db17537	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	376:cb4d9db17537	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	376:cb4d9db17537	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	376:cb4d9db17537	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	376:cb4d9db17537	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	376:cb4d9db17537	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	376:cb4d9db17537	34	*
mbed_official	376:cb4d9db17537	35	******************************************************************************
mbed_official	376:cb4d9db17537	36	*/
mbed_official	376:cb4d9db17537	37
mbed_official	376:cb4d9db17537	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	376:cb4d9db17537	39	#ifndef __STM32L0xx_HAL_RCC_H
mbed_official	376:cb4d9db17537	40	#define __STM32L0xx_HAL_RCC_H
mbed_official	376:cb4d9db17537	41
mbed_official	376:cb4d9db17537	42	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	43	extern "C" {
mbed_official	376:cb4d9db17537	44	#endif
mbed_official	376:cb4d9db17537	45
mbed_official	376:cb4d9db17537	46	/* Includes ------------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	47	#include "stm32l0xx_hal_def.h"
mbed_official	376:cb4d9db17537	48
mbed_official	376:cb4d9db17537	49	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	376:cb4d9db17537	50	* @{
mbed_official	376:cb4d9db17537	51	*/
mbed_official	376:cb4d9db17537	52
mbed_official	376:cb4d9db17537	53	/** @addtogroup RCC
mbed_official	376:cb4d9db17537	54	* @{
mbed_official	376:cb4d9db17537	55	*/
mbed_official	376:cb4d9db17537	56
mbed_official	376:cb4d9db17537	57	/* Exported types ------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	58
mbed_official	376:cb4d9db17537	59	/**
mbed_official	376:cb4d9db17537	60	* @brief RCC PLL configuration structure definition
mbed_official	376:cb4d9db17537	61	*/
mbed_official	376:cb4d9db17537	62	typedef struct
mbed_official	376:cb4d9db17537	63	{
mbed_official	376:cb4d9db17537	64	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	376:cb4d9db17537	65	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	376:cb4d9db17537	66
mbed_official	376:cb4d9db17537	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official	376:cb4d9db17537	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	376:cb4d9db17537	69
mbed_official	376:cb4d9db17537	70	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
mbed_official	376:cb4d9db17537	71	This parameter must of @ref RCC_PLLMultiplication_Factor */
mbed_official	376:cb4d9db17537	72
mbed_official	376:cb4d9db17537	73	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
mbed_official	376:cb4d9db17537	74	This parameter must be a value of @ref RCC_PLLDivider_Factor */
mbed_official	376:cb4d9db17537	75
mbed_official	376:cb4d9db17537	76	}RCC_PLLInitTypeDef;
mbed_official	376:cb4d9db17537	77
mbed_official	376:cb4d9db17537	78	/**
mbed_official	376:cb4d9db17537	79	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	376:cb4d9db17537	80	*/
mbed_official	376:cb4d9db17537	81	typedef struct
mbed_official	376:cb4d9db17537	82	{
mbed_official	376:cb4d9db17537	83	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	376:cb4d9db17537	84	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	376:cb4d9db17537	85
mbed_official	376:cb4d9db17537	86	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	376:cb4d9db17537	87	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	376:cb4d9db17537	88
mbed_official	376:cb4d9db17537	89	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	376:cb4d9db17537	90	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	376:cb4d9db17537	91
mbed_official	376:cb4d9db17537	92	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	376:cb4d9db17537	93	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	376:cb4d9db17537	94
mbed_official	376:cb4d9db17537	95	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	376:cb4d9db17537	96	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	376:cb4d9db17537	97
mbed_official	376:cb4d9db17537	98	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	376:cb4d9db17537	99	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	376:cb4d9db17537	100
mbed_official	376:cb4d9db17537	101	uint32_t HSI48State; /*!< The new state of the HSI48.
mbed_official	376:cb4d9db17537	102	This parameter can be a value of @ref RCC_HSI48_Config */
mbed_official	376:cb4d9db17537	103
mbed_official	376:cb4d9db17537	104	uint32_t MSIState; /*!< The new state of the MSI.
mbed_official	376:cb4d9db17537	105	This parameter can be a value of @ref RCC_MSI_Config */
mbed_official	376:cb4d9db17537	106
mbed_official	376:cb4d9db17537	107	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
mbed_official	376:cb4d9db17537	108	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
mbed_official	376:cb4d9db17537	109
mbed_official	376:cb4d9db17537	110	uint32_t MSIClockRange; /*!< The MSI frequency range.
mbed_official	376:cb4d9db17537	111	This parameter can be a value of @ref RCC_MSI_Clock_Range */
mbed_official	376:cb4d9db17537	112
mbed_official	376:cb4d9db17537	113	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	376:cb4d9db17537	114
mbed_official	376:cb4d9db17537	115	}RCC_OscInitTypeDef;
mbed_official	376:cb4d9db17537	116
mbed_official	376:cb4d9db17537	117	/**
mbed_official	376:cb4d9db17537	118	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	376:cb4d9db17537	119	*/
mbed_official	376:cb4d9db17537	120	typedef struct
mbed_official	376:cb4d9db17537	121	{
mbed_official	376:cb4d9db17537	122	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	376:cb4d9db17537	123	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	376:cb4d9db17537	124
mbed_official	376:cb4d9db17537	125	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	376:cb4d9db17537	126	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	376:cb4d9db17537	127
mbed_official	376:cb4d9db17537	128	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	376:cb4d9db17537	129	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	376:cb4d9db17537	130
mbed_official	376:cb4d9db17537	131	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	376:cb4d9db17537	132	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	376:cb4d9db17537	133
mbed_official	376:cb4d9db17537	134	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	376:cb4d9db17537	135	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	376:cb4d9db17537	136
mbed_official	376:cb4d9db17537	137	}RCC_ClkInitTypeDef;
mbed_official	376:cb4d9db17537	138
mbed_official	376:cb4d9db17537	139	/* Exported constants --------------------------------------------------------*/
mbed_official	376:cb4d9db17537	140	/** @defgroup RCC_Exported_Constants
mbed_official	376:cb4d9db17537	141	* @{
mbed_official	376:cb4d9db17537	142	*/
mbed_official	376:cb4d9db17537	143
mbed_official	376:cb4d9db17537	144	/** @defgroup RCC_BitAddress_AliasRegion
mbed_official	376:cb4d9db17537	145	* @brief RCC registers bit address in the alias region
mbed_official	376:cb4d9db17537	146	* @{
mbed_official	376:cb4d9db17537	147	*/
mbed_official	376:cb4d9db17537	148	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	376:cb4d9db17537	149	/* --- CR Register ---*/
mbed_official	376:cb4d9db17537	150	/* Alias word address of HSION bit */
mbed_official	376:cb4d9db17537	151	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	376:cb4d9db17537	152	/* --- CFGR Register ---*/
mbed_official	376:cb4d9db17537	153	/* Alias word address of I2SSRC bit */
mbed_official	376:cb4d9db17537	154	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
mbed_official	376:cb4d9db17537	155	/* --- CSR Register ---*/
mbed_official	376:cb4d9db17537	156	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
mbed_official	376:cb4d9db17537	157
mbed_official	376:cb4d9db17537	158	/* CR register byte 3 (Bits[23:16]) base address */
mbed_official	376:cb4d9db17537	159	#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
mbed_official	376:cb4d9db17537	160
mbed_official	376:cb4d9db17537	161	/* CIER register byte 0 (Bits[0:8]) base address */
mbed_official	376:cb4d9db17537	162	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
mbed_official	376:cb4d9db17537	163
mbed_official	376:cb4d9db17537	164	#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	376:cb4d9db17537	165	#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	376:cb4d9db17537	166
mbed_official	376:cb4d9db17537	167	/**
mbed_official	376:cb4d9db17537	168	* @}
mbed_official	376:cb4d9db17537	169	*/
mbed_official	376:cb4d9db17537	170
mbed_official	376:cb4d9db17537	171	/** @defgroup RCC_Oscillator_Type
mbed_official	376:cb4d9db17537	172	* @{
mbed_official	376:cb4d9db17537	173	*/
mbed_official	376:cb4d9db17537	174	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	175	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	376:cb4d9db17537	176	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	376:cb4d9db17537	177	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	376:cb4d9db17537	178	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	376:cb4d9db17537	179	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
mbed_official	376:cb4d9db17537	180	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
mbed_official	376:cb4d9db17537	181
mbed_official	376:cb4d9db17537	182	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 0x3F)
mbed_official	376:cb4d9db17537	183
mbed_official	376:cb4d9db17537	184	/**
mbed_official	376:cb4d9db17537	185	* @}
mbed_official	376:cb4d9db17537	186	*/
mbed_official	376:cb4d9db17537	187
mbed_official	376:cb4d9db17537	188	/** @defgroup RCC_HSE_Config
mbed_official	376:cb4d9db17537	189	* @{
mbed_official	376:cb4d9db17537	190	*/
mbed_official	376:cb4d9db17537	191	#define RCC_HSE_OFF ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	192	#define RCC_HSE_ON RCC_CR_HSEON
mbed_official	376:cb4d9db17537	193	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
mbed_official	376:cb4d9db17537	194
mbed_official	376:cb4d9db17537	195	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
mbed_official	376:cb4d9db17537	196	((HSE) == RCC_HSE_BYPASS))
mbed_official	376:cb4d9db17537	197	/**
mbed_official	376:cb4d9db17537	198	* @}
mbed_official	376:cb4d9db17537	199	*/
mbed_official	376:cb4d9db17537	200
mbed_official	376:cb4d9db17537	201	/** @defgroup RCC_LSE_Config
mbed_official	376:cb4d9db17537	202	* @{
mbed_official	376:cb4d9db17537	203	*/
mbed_official	376:cb4d9db17537	204	#define RCC_LSE_OFF ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	205	#define RCC_LSE_ON RCC_CSR_LSEON
mbed_official	376:cb4d9db17537	206	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
mbed_official	376:cb4d9db17537	207
mbed_official	376:cb4d9db17537	208	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
mbed_official	376:cb4d9db17537	209	((LSE) == RCC_LSE_BYPASS))
mbed_official	376:cb4d9db17537	210	/**
mbed_official	376:cb4d9db17537	211	* @}
mbed_official	376:cb4d9db17537	212	*/
mbed_official	376:cb4d9db17537	213
mbed_official	376:cb4d9db17537	214	/** @defgroup RCC_HSI_Config
mbed_official	376:cb4d9db17537	215	* @{
mbed_official	376:cb4d9db17537	216	*/
mbed_official	376:cb4d9db17537	217	#define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	218	#define RCC_HSI_ON ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	219	#define RCC_HSI_DIV4 ((uint8_t)0x09)
mbed_official	376:cb4d9db17537	220	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON) \|\| \
mbed_official	376:cb4d9db17537	221	((HSI) == RCC_HSI_DIV4))
mbed_official	376:cb4d9db17537	222
mbed_official	376:cb4d9db17537	223	/**
mbed_official	376:cb4d9db17537	224	* @}
mbed_official	376:cb4d9db17537	225	*/
mbed_official	376:cb4d9db17537	226
mbed_official	376:cb4d9db17537	227	/** @defgroup RCC_MSI_Clock_Range
mbed_official	376:cb4d9db17537	228	* @{
mbed_official	376:cb4d9db17537	229	*/
mbed_official	376:cb4d9db17537	230
mbed_official	376:cb4d9db17537	231	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
mbed_official	376:cb4d9db17537	232	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
mbed_official	376:cb4d9db17537	233	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
mbed_official	376:cb4d9db17537	234	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
mbed_official	376:cb4d9db17537	235	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
mbed_official	376:cb4d9db17537	236	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
mbed_official	376:cb4d9db17537	237	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
mbed_official	376:cb4d9db17537	238
mbed_official	376:cb4d9db17537	239	#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRANGE_0) \|\| \
mbed_official	376:cb4d9db17537	240	((RANGE) == RCC_MSIRANGE_1) \|\| \
mbed_official	376:cb4d9db17537	241	((RANGE) == RCC_MSIRANGE_2) \|\| \
mbed_official	376:cb4d9db17537	242	((RANGE) == RCC_MSIRANGE_3) \|\| \
mbed_official	376:cb4d9db17537	243	((RANGE) == RCC_MSIRANGE_4) \|\| \
mbed_official	376:cb4d9db17537	244	((RANGE) == RCC_MSIRANGE_5) \|\| \
mbed_official	376:cb4d9db17537	245	((RANGE) == RCC_MSIRANGE_6))
mbed_official	376:cb4d9db17537	246
mbed_official	376:cb4d9db17537	247	/**
mbed_official	376:cb4d9db17537	248	* @}
mbed_official	376:cb4d9db17537	249	*/
mbed_official	376:cb4d9db17537	250
mbed_official	376:cb4d9db17537	251	/** @defgroup RCC_LSI_Config
mbed_official	376:cb4d9db17537	252	* @{
mbed_official	376:cb4d9db17537	253	*/
mbed_official	376:cb4d9db17537	254	#define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	255	#define RCC_LSI_ON ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	256
mbed_official	376:cb4d9db17537	257	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
mbed_official	376:cb4d9db17537	258	/**
mbed_official	376:cb4d9db17537	259	* @}
mbed_official	376:cb4d9db17537	260	*/
mbed_official	376:cb4d9db17537	261
mbed_official	376:cb4d9db17537	262
mbed_official	376:cb4d9db17537	263	/** @defgroup RCC_MSI_Config
mbed_official	376:cb4d9db17537	264	* @{
mbed_official	376:cb4d9db17537	265	*/
mbed_official	376:cb4d9db17537	266	#define RCC_MSI_OFF ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	267	#define RCC_MSI_ON ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	268
mbed_official	376:cb4d9db17537	269	#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_OFF) \|\| ((MSI) == RCC_MSI_ON))
mbed_official	376:cb4d9db17537	270	/**
mbed_official	376:cb4d9db17537	271	* @}
mbed_official	376:cb4d9db17537	272	*/
mbed_official	376:cb4d9db17537	273
mbed_official	376:cb4d9db17537	274	/** @defgroup RCC_HSI48_Config
mbed_official	376:cb4d9db17537	275	* @{
mbed_official	376:cb4d9db17537	276	*/
mbed_official	376:cb4d9db17537	277	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	278	#define RCC_HSI48_ON ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	279
mbed_official	376:cb4d9db17537	280	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
mbed_official	376:cb4d9db17537	281	/**
mbed_official	376:cb4d9db17537	282	* @}
mbed_official	376:cb4d9db17537	283	*/
mbed_official	376:cb4d9db17537	284
mbed_official	376:cb4d9db17537	285	/** @defgroup RCC_PLL_Config
mbed_official	376:cb4d9db17537	286	* @{
mbed_official	376:cb4d9db17537	287	*/
mbed_official	376:cb4d9db17537	288	#define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	289	#define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	290	#define RCC_PLL_ON ((uint8_t)0x02)
mbed_official	376:cb4d9db17537	291
mbed_official	376:cb4d9db17537	292	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
mbed_official	376:cb4d9db17537	293	/**
mbed_official	376:cb4d9db17537	294	* @}
mbed_official	376:cb4d9db17537	295	*/
mbed_official	376:cb4d9db17537	296
mbed_official	376:cb4d9db17537	297	/** @defgroup RCC_PLL_Clock_Source
mbed_official	376:cb4d9db17537	298	* @{
mbed_official	376:cb4d9db17537	299	*/
mbed_official	376:cb4d9db17537	300	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
mbed_official	376:cb4d9db17537	301	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
mbed_official	376:cb4d9db17537	302
mbed_official	376:cb4d9db17537	303	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	376:cb4d9db17537	304	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	376:cb4d9db17537	305
mbed_official	376:cb4d9db17537	306	/**
mbed_official	376:cb4d9db17537	307	* @}
mbed_official	376:cb4d9db17537	308	*/
mbed_official	376:cb4d9db17537	309
mbed_official	376:cb4d9db17537	310	/** @defgroup RCC_PLLMultiplication_Factor
mbed_official	376:cb4d9db17537	311	* @{
mbed_official	376:cb4d9db17537	312	*/
mbed_official	376:cb4d9db17537	313
mbed_official	376:cb4d9db17537	314	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
mbed_official	376:cb4d9db17537	315	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
mbed_official	376:cb4d9db17537	316	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
mbed_official	376:cb4d9db17537	317	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
mbed_official	376:cb4d9db17537	318	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
mbed_official	376:cb4d9db17537	319	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
mbed_official	376:cb4d9db17537	320	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
mbed_official	376:cb4d9db17537	321	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
mbed_official	376:cb4d9db17537	322	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
mbed_official	376:cb4d9db17537	323	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMUL_3) \|\| ((MUL) == RCC_PLLMUL_4) \|\| \
mbed_official	376:cb4d9db17537	324	((MUL) == RCC_PLLMUL_6) \|\| ((MUL) == RCC_PLLMUL_8) \|\| \
mbed_official	376:cb4d9db17537	325	((MUL) == RCC_PLLMUL_12) \|\| ((MUL) == RCC_PLLMUL_16) \|\| \
mbed_official	376:cb4d9db17537	326	((MUL) == RCC_PLLMUL_24) \|\| ((MUL) == RCC_PLLMUL_32) \|\| \
mbed_official	376:cb4d9db17537	327	((MUL) == RCC_PLLMUL_48))
mbed_official	376:cb4d9db17537	328	/**
mbed_official	376:cb4d9db17537	329	* @}
mbed_official	376:cb4d9db17537	330	*/
mbed_official	376:cb4d9db17537	331
mbed_official	376:cb4d9db17537	332	/** @defgroup RCC_PLLDivider_Factor
mbed_official	376:cb4d9db17537	333	* @{
mbed_official	376:cb4d9db17537	334	*/
mbed_official	376:cb4d9db17537	335
mbed_official	376:cb4d9db17537	336	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
mbed_official	376:cb4d9db17537	337	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
mbed_official	376:cb4d9db17537	338	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
mbed_official	376:cb4d9db17537	339	#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDIV_2) \|\| ((DIV) == RCC_PLLDIV_3) \|\| \
mbed_official	376:cb4d9db17537	340	((DIV) == RCC_PLLDIV_4))
mbed_official	376:cb4d9db17537	341	/**
mbed_official	376:cb4d9db17537	342	* @}
mbed_official	376:cb4d9db17537	343	*/
mbed_official	376:cb4d9db17537	344
mbed_official	376:cb4d9db17537	345	/** @defgroup RCC_System_Clock_Type
mbed_official	376:cb4d9db17537	346	* @{
mbed_official	376:cb4d9db17537	347	*/
mbed_official	376:cb4d9db17537	348	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	376:cb4d9db17537	349	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	376:cb4d9db17537	350	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	376:cb4d9db17537	351	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official	376:cb4d9db17537	352
mbed_official	376:cb4d9db17537	353	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
mbed_official	376:cb4d9db17537	354	/**
mbed_official	376:cb4d9db17537	355	* @}
mbed_official	376:cb4d9db17537	356	*/
mbed_official	376:cb4d9db17537	357
mbed_official	376:cb4d9db17537	358	/** @defgroup RCC_System_Clock_Source
mbed_official	376:cb4d9db17537	359	* @{
mbed_official	376:cb4d9db17537	360	*/
mbed_official	376:cb4d9db17537	361	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
mbed_official	376:cb4d9db17537	362	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official	376:cb4d9db17537	363	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official	376:cb4d9db17537	364	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official	376:cb4d9db17537	365
mbed_official	376:cb4d9db17537	366	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	376:cb4d9db17537	367	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	376:cb4d9db17537	368	((SOURCE) == RCC_SYSCLKSOURCE_MSI) \|\| \
mbed_official	376:cb4d9db17537	369	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	376:cb4d9db17537	370	/**
mbed_official	376:cb4d9db17537	371	* @}
mbed_official	376:cb4d9db17537	372	*/
mbed_official	376:cb4d9db17537	373
mbed_official	376:cb4d9db17537	374	/** @defgroup RCC_AHB_Clock_Source
mbed_official	376:cb4d9db17537	375	* @{
mbed_official	376:cb4d9db17537	376	*/
mbed_official	376:cb4d9db17537	377	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official	376:cb4d9db17537	378	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official	376:cb4d9db17537	379	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official	376:cb4d9db17537	380	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official	376:cb4d9db17537	381	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official	376:cb4d9db17537	382	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official	376:cb4d9db17537	383	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official	376:cb4d9db17537	384	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official	376:cb4d9db17537	385	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official	376:cb4d9db17537	386
mbed_official	376:cb4d9db17537	387	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	376:cb4d9db17537	388	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	376:cb4d9db17537	389	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	376:cb4d9db17537	390	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	376:cb4d9db17537	391	((HCLK) == RCC_SYSCLK_DIV512))
mbed_official	376:cb4d9db17537	392	/**
mbed_official	376:cb4d9db17537	393	* @}
mbed_official	376:cb4d9db17537	394	*/
mbed_official	376:cb4d9db17537	395
mbed_official	376:cb4d9db17537	396	/** @defgroup RCC_APB1_APB2_Clock_Source
mbed_official	376:cb4d9db17537	397	* @{
mbed_official	376:cb4d9db17537	398	*/
mbed_official	376:cb4d9db17537	399	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
mbed_official	376:cb4d9db17537	400	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
mbed_official	376:cb4d9db17537	401	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
mbed_official	376:cb4d9db17537	402	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
mbed_official	376:cb4d9db17537	403	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
mbed_official	376:cb4d9db17537	404
mbed_official	376:cb4d9db17537	405	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
mbed_official	376:cb4d9db17537	406	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
mbed_official	376:cb4d9db17537	407	((PCLK) == RCC_HCLK_DIV16))
mbed_official	376:cb4d9db17537	408	/**
mbed_official	376:cb4d9db17537	409	* @}
mbed_official	376:cb4d9db17537	410	*/
mbed_official	376:cb4d9db17537	411
mbed_official	376:cb4d9db17537	412	/** @defgroup RCC_RTC_Clock_Source
mbed_official	376:cb4d9db17537	413	* @{
mbed_official	376:cb4d9db17537	414	*/
mbed_official	376:cb4d9db17537	415	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
mbed_official	376:cb4d9db17537	416	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
mbed_official	376:cb4d9db17537	417	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
mbed_official	376:cb4d9db17537	418	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
mbed_official	376:cb4d9db17537	419	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
mbed_official	376:cb4d9db17537	420	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
mbed_official	376:cb4d9db17537	421	#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	376:cb4d9db17537	422	((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	376:cb4d9db17537	423	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
mbed_official	376:cb4d9db17537	424	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
mbed_official	376:cb4d9db17537	425	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
mbed_official	376:cb4d9db17537	426	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16))
mbed_official	376:cb4d9db17537	427	/**
mbed_official	376:cb4d9db17537	428	* @}
mbed_official	376:cb4d9db17537	429	*/
mbed_official	376:cb4d9db17537	430
mbed_official	376:cb4d9db17537	431	/** @defgroup RCC_MCO_Clock_Source
mbed_official	376:cb4d9db17537	432	* @{
mbed_official	376:cb4d9db17537	433	*/
mbed_official	376:cb4d9db17537	434	#define RCC_MCO1SOURCE_NOCLOCK ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	435	#define RCC_MCO1SOURCE_SYSCLK ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	436	#define RCC_MCO1SOURCE_HSI ((uint8_t)0x02)
mbed_official	376:cb4d9db17537	437	#define RCC_MCO1SOURCE_MSI ((uint8_t)0x03)
mbed_official	376:cb4d9db17537	438	#define RCC_MCO1SOURCE_HSE ((uint8_t)0x04)
mbed_official	376:cb4d9db17537	439	#define RCC_MCO1SOURCE_PLLCLK ((uint8_t)0x05)
mbed_official	376:cb4d9db17537	440	#define RCC_MCO1SOURCE_LSI ((uint8_t)0x06)
mbed_official	376:cb4d9db17537	441	#define RCC_MCO1SOURCE_LSE ((uint8_t)0x07)
mbed_official	376:cb4d9db17537	442	#define RCC_MCO1SOURCE_HSI48 ((uint8_t)0x08)
mbed_official	376:cb4d9db17537	443
mbed_official	376:cb4d9db17537	444	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
mbed_official	376:cb4d9db17537	445	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_MSI) \|\| \
mbed_official	376:cb4d9db17537	446	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
mbed_official	376:cb4d9db17537	447	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
mbed_official	376:cb4d9db17537	448	((SOURCE) == RCC_MCO1SOURCE_HSI48))
mbed_official	376:cb4d9db17537	449	/**
mbed_official	376:cb4d9db17537	450	* @}
mbed_official	376:cb4d9db17537	451	*/
mbed_official	376:cb4d9db17537	452
mbed_official	376:cb4d9db17537	453	/** @defgroup RCC_MCOPrescaler
mbed_official	376:cb4d9db17537	454	* @{
mbed_official	376:cb4d9db17537	455	*/
mbed_official	376:cb4d9db17537	456
mbed_official	376:cb4d9db17537	457	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
mbed_official	376:cb4d9db17537	458	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
mbed_official	376:cb4d9db17537	459	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
mbed_official	376:cb4d9db17537	460	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
mbed_official	376:cb4d9db17537	461	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
mbed_official	376:cb4d9db17537	462
mbed_official	376:cb4d9db17537	463	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| \
mbed_official	376:cb4d9db17537	464	((DIV) == RCC_MCODIV_2) \|\| \
mbed_official	376:cb4d9db17537	465	((DIV) == RCC_MCODIV_4) \|\| \
mbed_official	376:cb4d9db17537	466	((DIV) == RCC_MCODIV_8) \|\| \
mbed_official	376:cb4d9db17537	467	((DIV) == RCC_MCODIV_16))
mbed_official	376:cb4d9db17537	468	/**
mbed_official	376:cb4d9db17537	469	* @}
mbed_official	376:cb4d9db17537	470	*/
mbed_official	376:cb4d9db17537	471
mbed_official	376:cb4d9db17537	472	/** @defgroup RCC_MCO_Index
mbed_official	376:cb4d9db17537	473	* @{
mbed_official	376:cb4d9db17537	474	*/
mbed_official	376:cb4d9db17537	475	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	476	#define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official	376:cb4d9db17537	477
mbed_official	376:cb4d9db17537	478	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
mbed_official	376:cb4d9db17537	479	/**
mbed_official	376:cb4d9db17537	480	* @}
mbed_official	376:cb4d9db17537	481	*/
mbed_official	376:cb4d9db17537	482
mbed_official	376:cb4d9db17537	483	/** @defgroup RCC_Interrupt
mbed_official	376:cb4d9db17537	484	* @{
mbed_official	376:cb4d9db17537	485	*/
mbed_official	376:cb4d9db17537	486	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
mbed_official	376:cb4d9db17537	487	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
mbed_official	376:cb4d9db17537	488	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
mbed_official	376:cb4d9db17537	489	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
mbed_official	376:cb4d9db17537	490	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
mbed_official	376:cb4d9db17537	491	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
mbed_official	376:cb4d9db17537	492	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
mbed_official	376:cb4d9db17537	493	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF
mbed_official	376:cb4d9db17537	494	#define RCC_IT_CSS RCC_CIFR_CSSF
mbed_official	376:cb4d9db17537	495
mbed_official	376:cb4d9db17537	496	#define IS_RCC_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \
mbed_official	376:cb4d9db17537	497	((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \
mbed_official	376:cb4d9db17537	498	((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \
mbed_official	376:cb4d9db17537	499	((IT) == RCC_IT_HSI48RDY) \|\| ((IT) == RCC_IT_LSECSS))
mbed_official	376:cb4d9db17537	500
mbed_official	376:cb4d9db17537	501	#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \
mbed_official	376:cb4d9db17537	502	((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \
mbed_official	376:cb4d9db17537	503	((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \
mbed_official	376:cb4d9db17537	504	((IT) == RCC_IT_CSS) \|\| ((IT) == RCC_IT_HSI48RDY) \|\| \
mbed_official	376:cb4d9db17537	505	((IT) == RCC_IT_LSECSS))
mbed_official	376:cb4d9db17537	506
mbed_official	376:cb4d9db17537	507	#define IS_RCC_CLEAR_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \
mbed_official	376:cb4d9db17537	508	((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \
mbed_official	376:cb4d9db17537	509	((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \
mbed_official	376:cb4d9db17537	510	((IT) == RCC_IT_CSS) \|\| ((IT) == RCC_IT_HSI48RDY) \|\| \
mbed_official	376:cb4d9db17537	511	((IT) == RCC_IT_LSECSS))
mbed_official	376:cb4d9db17537	512
mbed_official	376:cb4d9db17537	513	/**
mbed_official	376:cb4d9db17537	514	* @}
mbed_official	376:cb4d9db17537	515	*/
mbed_official	376:cb4d9db17537	516
mbed_official	376:cb4d9db17537	517	/** @defgroup RCC_Flag
mbed_official	376:cb4d9db17537	518	* Elements values convention: 0XXYYYYYb
mbed_official	376:cb4d9db17537	519	* - YYYYY : Flag position in the register
mbed_official	376:cb4d9db17537	520	* - 0XX : Register index
mbed_official	376:cb4d9db17537	521	* - 01: CR register
mbed_official	376:cb4d9db17537	522	* - 10: CSR register
mbed_official	376:cb4d9db17537	523	* - 11: CRRCR register
mbed_official	376:cb4d9db17537	524	* @{
mbed_official	376:cb4d9db17537	525	*/
mbed_official	376:cb4d9db17537	526	/* Flags in the CR register */
mbed_official	376:cb4d9db17537	527	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
mbed_official	376:cb4d9db17537	528	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
mbed_official	376:cb4d9db17537	529	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
mbed_official	376:cb4d9db17537	530	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
mbed_official	376:cb4d9db17537	531	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
mbed_official	376:cb4d9db17537	532
mbed_official	376:cb4d9db17537	533	/* Flags in the CSR register */
mbed_official	376:cb4d9db17537	534	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
mbed_official	376:cb4d9db17537	535	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
mbed_official	376:cb4d9db17537	536	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
mbed_official	376:cb4d9db17537	537	#define RCC_FLAG_FIREWALLRST ((uint8_t)0x58)
mbed_official	376:cb4d9db17537	538	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
mbed_official	376:cb4d9db17537	539	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
mbed_official	376:cb4d9db17537	540	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
mbed_official	376:cb4d9db17537	541	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
mbed_official	376:cb4d9db17537	542	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
mbed_official	376:cb4d9db17537	543	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
mbed_official	376:cb4d9db17537	544	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
mbed_official	376:cb4d9db17537	545
mbed_official	376:cb4d9db17537	546	/* Flags in the CRRCR register */
mbed_official	376:cb4d9db17537	547	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
mbed_official	376:cb4d9db17537	548
mbed_official	376:cb4d9db17537	549
mbed_official	376:cb4d9db17537	550
mbed_official	376:cb4d9db17537	551	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
mbed_official	376:cb4d9db17537	552	#define IS_RCC_MSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0xFF)
mbed_official	376:cb4d9db17537	553	/**
mbed_official	376:cb4d9db17537	554	* @}
mbed_official	376:cb4d9db17537	555	*/
mbed_official	376:cb4d9db17537	556
mbed_official	376:cb4d9db17537	557	/**
mbed_official	376:cb4d9db17537	558	* @}
mbed_official	376:cb4d9db17537	559	*/
mbed_official	376:cb4d9db17537	560	/* Exported macro ------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	561	/** @defgroup RCC_Exported macro
mbed_official	376:cb4d9db17537	562	* @{
mbed_official	376:cb4d9db17537	563	*/
mbed_official	376:cb4d9db17537	564
mbed_official	376:cb4d9db17537	565	/** @brief Enable or disable the AHB peripheral clock.
mbed_official	376:cb4d9db17537	566	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	567	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	568	* using it.
mbed_official	376:cb4d9db17537	569	*/
mbed_official	376:cb4d9db17537	570	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
mbed_official	376:cb4d9db17537	571	#define __MIF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_MIFEN))
mbed_official	376:cb4d9db17537	572	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
mbed_official	376:cb4d9db17537	573
mbed_official	376:cb4d9db17537	574
mbed_official	376:cb4d9db17537	575	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
mbed_official	376:cb4d9db17537	576	#define __MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
mbed_official	376:cb4d9db17537	577	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
mbed_official	376:cb4d9db17537	578
mbed_official	376:cb4d9db17537	579
mbed_official	376:cb4d9db17537	580	/** @brief Enable or disable the IOPORT peripheral clock.
mbed_official	376:cb4d9db17537	581	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	582	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	583	* using it.
mbed_official	376:cb4d9db17537	584	*/
mbed_official	376:cb4d9db17537	585	#define __GPIOA_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOAEN))
mbed_official	376:cb4d9db17537	586	#define __GPIOB_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOBEN))
mbed_official	376:cb4d9db17537	587	#define __GPIOC_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOCEN))
mbed_official	376:cb4d9db17537	588	#define __GPIOD_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIODEN))
mbed_official	376:cb4d9db17537	589	#define __GPIOH_CLK_ENABLE() (RCC->IOPENR \|= (RCC_IOPENR_GPIOHEN))
mbed_official	376:cb4d9db17537	590
mbed_official	376:cb4d9db17537	591	#define __GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
mbed_official	376:cb4d9db17537	592	#define __GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
mbed_official	376:cb4d9db17537	593	#define __GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
mbed_official	376:cb4d9db17537	594	#define __GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
mbed_official	376:cb4d9db17537	595	#define __GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
mbed_official	376:cb4d9db17537	596
mbed_official	376:cb4d9db17537	597
mbed_official	376:cb4d9db17537	598	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	376:cb4d9db17537	599	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	600	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	601	* using it.
mbed_official	376:cb4d9db17537	602	*/
mbed_official	376:cb4d9db17537	603	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	376:cb4d9db17537	604	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
mbed_official	376:cb4d9db17537	605
mbed_official	376:cb4d9db17537	606	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
mbed_official	376:cb4d9db17537	607	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
mbed_official	376:cb4d9db17537	608
mbed_official	376:cb4d9db17537	609	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	376:cb4d9db17537	610	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	611	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	612	* using it.
mbed_official	376:cb4d9db17537	613	*/
mbed_official	376:cb4d9db17537	614	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
mbed_official	376:cb4d9db17537	615	#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
mbed_official	376:cb4d9db17537	616
mbed_official	376:cb4d9db17537	617	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
mbed_official	376:cb4d9db17537	618	#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
mbed_official	376:cb4d9db17537	619
mbed_official	376:cb4d9db17537	620	/** @brief Force or release AHB peripheral reset.
mbed_official	376:cb4d9db17537	621	*/
mbed_official	376:cb4d9db17537	622	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	376:cb4d9db17537	623	#define __DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
mbed_official	376:cb4d9db17537	624	#define __MIF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_MIFRST))
mbed_official	376:cb4d9db17537	625	#define __CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
mbed_official	376:cb4d9db17537	626
mbed_official	376:cb4d9db17537	627	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	376:cb4d9db17537	628	#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
mbed_official	376:cb4d9db17537	629	#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
mbed_official	376:cb4d9db17537	630	#define __MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
mbed_official	376:cb4d9db17537	631
mbed_official	376:cb4d9db17537	632
mbed_official	376:cb4d9db17537	633	/** @brief Force or release IOPORT peripheral reset.
mbed_official	376:cb4d9db17537	634	*/
mbed_official	376:cb4d9db17537	635	#define __IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
mbed_official	376:cb4d9db17537	636	#define __GPIOA_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOARST))
mbed_official	376:cb4d9db17537	637	#define __GPIOB_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOBRST))
mbed_official	376:cb4d9db17537	638	#define __GPIOC_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOCRST))
mbed_official	376:cb4d9db17537	639	#define __GPIOD_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIODRST))
mbed_official	376:cb4d9db17537	640	#define __GPIOH_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOHRST))
mbed_official	376:cb4d9db17537	641
mbed_official	376:cb4d9db17537	642	#define __IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
mbed_official	376:cb4d9db17537	643	#define __GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
mbed_official	376:cb4d9db17537	644	#define __GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
mbed_official	376:cb4d9db17537	645	#define __GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
mbed_official	376:cb4d9db17537	646	#define __GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
mbed_official	376:cb4d9db17537	647	#define __GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
mbed_official	376:cb4d9db17537	648
mbed_official	376:cb4d9db17537	649	/** @brief Force or release APB1 peripheral reset.
mbed_official	376:cb4d9db17537	650	*/
mbed_official	376:cb4d9db17537	651	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	376:cb4d9db17537	652	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	376:cb4d9db17537	653	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	376:cb4d9db17537	654
mbed_official	376:cb4d9db17537	655	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	376:cb4d9db17537	656	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
mbed_official	376:cb4d9db17537	657	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
mbed_official	376:cb4d9db17537	658
mbed_official	376:cb4d9db17537	659	/** @brief Force or release APB2 peripheral reset.
mbed_official	376:cb4d9db17537	660	*/
mbed_official	376:cb4d9db17537	661	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	376:cb4d9db17537	662	#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
mbed_official	376:cb4d9db17537	663	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	376:cb4d9db17537	664
mbed_official	376:cb4d9db17537	665	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	376:cb4d9db17537	666	#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
mbed_official	376:cb4d9db17537	667	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
mbed_official	376:cb4d9db17537	668
mbed_official	376:cb4d9db17537	669	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	670	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	671	* power consumption.
mbed_official	376:cb4d9db17537	672	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	376:cb4d9db17537	673	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	674	*/
mbed_official	376:cb4d9db17537	675	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_CRCSMEN))
mbed_official	376:cb4d9db17537	676	#define __MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_MIFSMEN))
mbed_official	376:cb4d9db17537	677	#define __SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_SRAMSMEN))
mbed_official	376:cb4d9db17537	678	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_DMA1SMEN))
mbed_official	376:cb4d9db17537	679
mbed_official	376:cb4d9db17537	680	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
mbed_official	376:cb4d9db17537	681	#define __MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
mbed_official	376:cb4d9db17537	682	#define __SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
mbed_official	376:cb4d9db17537	683	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
mbed_official	376:cb4d9db17537	684
mbed_official	376:cb4d9db17537	685	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	686	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	687	* power consumption.
mbed_official	376:cb4d9db17537	688	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	376:cb4d9db17537	689	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	690	*/
mbed_official	376:cb4d9db17537	691
mbed_official	376:cb4d9db17537	692	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOASMEN))
mbed_official	376:cb4d9db17537	693	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOBSMEN))
mbed_official	376:cb4d9db17537	694	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOCSMEN))
mbed_official	376:cb4d9db17537	695	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIODSMEN))
mbed_official	376:cb4d9db17537	696	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOHSMEN))
mbed_official	376:cb4d9db17537	697
mbed_official	376:cb4d9db17537	698	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
mbed_official	376:cb4d9db17537	699	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
mbed_official	376:cb4d9db17537	700	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
mbed_official	376:cb4d9db17537	701	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
mbed_official	376:cb4d9db17537	702	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
mbed_official	376:cb4d9db17537	703
mbed_official	376:cb4d9db17537	704	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	705	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	706	* power consumption.
mbed_official	376:cb4d9db17537	707	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	376:cb4d9db17537	708	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	709	*/
mbed_official	376:cb4d9db17537	710	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_WWDGSMEN))
mbed_official	376:cb4d9db17537	711	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_PWRSMEN))
mbed_official	376:cb4d9db17537	712
mbed_official	376:cb4d9db17537	713	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
mbed_official	376:cb4d9db17537	714	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
mbed_official	376:cb4d9db17537	715
mbed_official	376:cb4d9db17537	716	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	717	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	718	* power consumption.
mbed_official	376:cb4d9db17537	719	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	376:cb4d9db17537	720	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	721	*/
mbed_official	376:cb4d9db17537	722	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	376:cb4d9db17537	723	#define __DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	376:cb4d9db17537	724
mbed_official	376:cb4d9db17537	725	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	376:cb4d9db17537	726	#define __DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	376:cb4d9db17537	727
mbed_official	376:cb4d9db17537	728	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	376:cb4d9db17537	729	* @note After enabling the HSI, the application software should wait on
mbed_official	376:cb4d9db17537	730	* HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official	376:cb4d9db17537	731	* be used to clock the PLL and/or system clock.
mbed_official	376:cb4d9db17537	732	* @note HSI can not be stopped if it is used directly or through the PLL
mbed_official	376:cb4d9db17537	733	* as system clock. In this case, you have to select another source
mbed_official	376:cb4d9db17537	734	* of the system clock then stop the HSI.
mbed_official	376:cb4d9db17537	735	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	736	* @param __STATE__: specifies the new state of the HSI.
mbed_official	376:cb4d9db17537	737	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	738	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
mbed_official	376:cb4d9db17537	739	* @arg RCC_HSI_ON: turn ON the HSI oscillator
mbed_official	376:cb4d9db17537	740	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
mbed_official	376:cb4d9db17537	741	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	376:cb4d9db17537	742	* clock cycles.
mbed_official	376:cb4d9db17537	743	*/
mbed_official	376:cb4d9db17537	744	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
mbed_official	376:cb4d9db17537	745	MODIFY_REG(RCC->CR, RCC_CR_HSION\|RCC_CR_HSIDIVEN, (uint32_t)(__STATE__))
mbed_official	376:cb4d9db17537	746
mbed_official	376:cb4d9db17537	747	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	376:cb4d9db17537	748	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	749	* It is used (enabled by hardware) as system clock source after startup
mbed_official	376:cb4d9db17537	750	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	376:cb4d9db17537	751	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	376:cb4d9db17537	752	* Security System CSS is enabled).
mbed_official	376:cb4d9db17537	753	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	376:cb4d9db17537	754	* you have to select another source of the system clock then stop the HSI.
mbed_official	376:cb4d9db17537	755	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	376:cb4d9db17537	756	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	376:cb4d9db17537	757	* system clock source.
mbed_official	376:cb4d9db17537	758	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	376:cb4d9db17537	759	* clock cycles.
mbed_official	376:cb4d9db17537	760	*/
mbed_official	376:cb4d9db17537	761	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	376:cb4d9db17537	762	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	376:cb4d9db17537	763
mbed_official	376:cb4d9db17537	764	/**
mbed_official	376:cb4d9db17537	765	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
mbed_official	376:cb4d9db17537	766	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	767	* It is used (enabled by hardware) as system clock source after
mbed_official	376:cb4d9db17537	768	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
mbed_official	376:cb4d9db17537	769	* of failure of the HSE used directly or indirectly as system clock
mbed_official	376:cb4d9db17537	770	* (if the Clock Security System CSS is enabled).
mbed_official	376:cb4d9db17537	771	* @note MSI can not be stopped if it is used as system clock source.
mbed_official	376:cb4d9db17537	772	* In this case, you have to select another source of the system
mbed_official	376:cb4d9db17537	773	* clock then stop the MSI.
mbed_official	376:cb4d9db17537	774	* @note After enabling the MSI, the application software should wait on
mbed_official	376:cb4d9db17537	775	* MSIRDY flag to be set indicating that MSI clock is stable and can
mbed_official	376:cb4d9db17537	776	* be used as system clock source.
mbed_official	376:cb4d9db17537	777	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
mbed_official	376:cb4d9db17537	778	* clock cycles.
mbed_official	376:cb4d9db17537	779	*/
mbed_official	376:cb4d9db17537	780	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	376:cb4d9db17537	781	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	376:cb4d9db17537	782
mbed_official	376:cb4d9db17537	783	/**
mbed_official	376:cb4d9db17537	784	* @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
mbed_official	376:cb4d9db17537	785	* @note After enabling the HSI48, the application software should wait on
mbed_official	376:cb4d9db17537	786	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
mbed_official	376:cb4d9db17537	787	* be used to clock the USB.
mbed_official	376:cb4d9db17537	788	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	789	*/
mbed_official	376:cb4d9db17537	790	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
mbed_official	376:cb4d9db17537	791	RCC->APB2ENR \|= RCC_APB2ENR_SYSCFGEN; \
mbed_official	376:cb4d9db17537	792	SYSCFG->CFGR3 \|= (SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT); \
mbed_official	376:cb4d9db17537	793	} while (0)
mbed_official	376:cb4d9db17537	794	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
mbed_official	376:cb4d9db17537	795	SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT)); \
mbed_official	376:cb4d9db17537	796	} while (0)
mbed_official	376:cb4d9db17537	797
mbed_official	376:cb4d9db17537	798	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	376:cb4d9db17537	799	* @note The calibration is used to compensate for the variations in voltage
mbed_official	376:cb4d9db17537	800	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	376:cb4d9db17537	801	* @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official	376:cb4d9db17537	802	* This parameter must be a number between 0 and 0x1F.
mbed_official	376:cb4d9db17537	803	*/
mbed_official	376:cb4d9db17537	804	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	376:cb4d9db17537	805	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
mbed_official	376:cb4d9db17537	806
mbed_official	376:cb4d9db17537	807	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
mbed_official	376:cb4d9db17537	808	* @note The calibration is used to compensate for the variations in voltage
mbed_official	376:cb4d9db17537	809	* and temperature that influence the frequency of the internal MSI RC.
mbed_official	376:cb4d9db17537	810	* Refer to the Application Note AN3300 for more details on how to
mbed_official	376:cb4d9db17537	811	* calibrate the MSI.
mbed_official	376:cb4d9db17537	812	* @param __MSICalibrationValue__: specifies the calibration trimming value.
mbed_official	376:cb4d9db17537	813	* This parameter must be a number between 0 and 0xFF.
mbed_official	376:cb4d9db17537	814	*/
mbed_official	376:cb4d9db17537	815	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	376:cb4d9db17537	816	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
mbed_official	376:cb4d9db17537	817
mbed_official	376:cb4d9db17537	818	/**
mbed_official	376:cb4d9db17537	819	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
mbed_official	376:cb4d9db17537	820	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
mbed_official	376:cb4d9db17537	821	* around 2.097 MHz. The MSI clock does not change after wake-up from
mbed_official	376:cb4d9db17537	822	* STOP mode.
mbed_official	376:cb4d9db17537	823	* @note The MSI clock range can be modified on the fly.
mbed_official	376:cb4d9db17537	824	* @param RCC_MSIRange: specifies the MSI Clock range.
mbed_official	376:cb4d9db17537	825	* This parameter must be one of the following values:
mbed_official	376:cb4d9db17537	826	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
mbed_official	376:cb4d9db17537	827	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
mbed_official	376:cb4d9db17537	828	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
mbed_official	376:cb4d9db17537	829	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
mbed_official	376:cb4d9db17537	830	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
mbed_official	376:cb4d9db17537	831	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
mbed_official	376:cb4d9db17537	832	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
mbed_official	376:cb4d9db17537	833	*/
mbed_official	376:cb4d9db17537	834	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	376:cb4d9db17537	835	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
mbed_official	376:cb4d9db17537	836
mbed_official	376:cb4d9db17537	837	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	376:cb4d9db17537	838	* @note After enabling the LSI, the application software should wait on
mbed_official	376:cb4d9db17537	839	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	376:cb4d9db17537	840	* be used to clock the IWDG and/or the RTC.
mbed_official	376:cb4d9db17537	841	* @note LSI can not be disabled if the IWDG is running.
mbed_official	376:cb4d9db17537	842	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	376:cb4d9db17537	843	* clock cycles.
mbed_official	376:cb4d9db17537	844	*/
mbed_official	376:cb4d9db17537	845	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	376:cb4d9db17537	846	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	376:cb4d9db17537	847
mbed_official	376:cb4d9db17537	848	/**
mbed_official	376:cb4d9db17537	849	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	376:cb4d9db17537	850	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	376:cb4d9db17537	851	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	376:cb4d9db17537	852	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	376:cb4d9db17537	853	* @note HSE state can not be changed if it is used directly or through the
mbed_official	376:cb4d9db17537	854	* PLL as system clock. In this case, you have to select another source
mbed_official	376:cb4d9db17537	855	* of the system clock then change the HSE state (ex. disable it).
mbed_official	376:cb4d9db17537	856	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	857	* @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official	376:cb4d9db17537	858	* was previously enabled you have to enable it again after calling this
mbed_official	376:cb4d9db17537	859	* function.
mbed_official	376:cb4d9db17537	860	* @param __STATE__: specifies the new state of the HSE.
mbed_official	376:cb4d9db17537	861	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	862	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	376:cb4d9db17537	863	* 6 HSE oscillator clock cycles.
mbed_official	376:cb4d9db17537	864	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official	376:cb4d9db17537	865	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official	376:cb4d9db17537	866	*/
mbed_official	376:cb4d9db17537	867	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
mbed_official	376:cb4d9db17537	868	MODIFY_REG(RCC->CR, RCC_CR_HSEON\|RCC_CR_HSEBYP, (uint32_t)(__STATE__))
mbed_official	376:cb4d9db17537	869
mbed_official	376:cb4d9db17537	870	/**
mbed_official	376:cb4d9db17537	871	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	376:cb4d9db17537	872	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	376:cb4d9db17537	873	* this domain after reset, you have to enable write access using
mbed_official	376:cb4d9db17537	874	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	376:cb4d9db17537	875	* (to be done once after reset).
mbed_official	376:cb4d9db17537	876	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	376:cb4d9db17537	877	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	376:cb4d9db17537	878	* is stable and can be used to clock the RTC.
mbed_official	376:cb4d9db17537	879	* @param __STATE__: specifies the new state of the LSE.
mbed_official	376:cb4d9db17537	880	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	881	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	376:cb4d9db17537	882	* 6 LSE oscillator clock cycles.
mbed_official	376:cb4d9db17537	883	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	376:cb4d9db17537	884	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	376:cb4d9db17537	885	*/
mbed_official	376:cb4d9db17537	886	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
mbed_official	376:cb4d9db17537	887	MODIFY_REG(RCC->CSR, RCC_CSR_LSEON\|RCC_CSR_LSEBYP, (uint32_t)(__STATE__))
mbed_official	376:cb4d9db17537	888
mbed_official	376:cb4d9db17537	889	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	376:cb4d9db17537	890	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	376:cb4d9db17537	891	*/
mbed_official	376:cb4d9db17537	892	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	376:cb4d9db17537	893	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	376:cb4d9db17537	894
mbed_official	376:cb4d9db17537	895	/**
mbed_official	376:cb4d9db17537	896	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
mbed_official	376:cb4d9db17537	897	* @note As the RTC clock configuration bits are in the RTC domain and write
mbed_official	376:cb4d9db17537	898	* access is denied to this domain after reset, you have to enable write
mbed_official	376:cb4d9db17537	899	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
mbed_official	376:cb4d9db17537	900	* the RTC clock source (to be done once after reset).
mbed_official	376:cb4d9db17537	901	* @note Once the RTC clock is configured it can't be changed unless the RTC
mbed_official	376:cb4d9db17537	902	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
mbed_official	376:cb4d9db17537	903	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
mbed_official	376:cb4d9db17537	904	*
mbed_official	376:cb4d9db17537	905	* @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official	376:cb4d9db17537	906	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	907	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	376:cb4d9db17537	908	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	376:cb4d9db17537	909	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
mbed_official	376:cb4d9db17537	910	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
mbed_official	376:cb4d9db17537	911	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
mbed_official	376:cb4d9db17537	912	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
mbed_official	376:cb4d9db17537	913	*
mbed_official	376:cb4d9db17537	914	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	376:cb4d9db17537	915	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	376:cb4d9db17537	916	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	376:cb4d9db17537	917	* cannot be used in STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	918	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	376:cb4d9db17537	919	* RTC clock source).
mbed_official	376:cb4d9db17537	920	*/
mbed_official	376:cb4d9db17537	921	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
mbed_official	376:cb4d9db17537	922	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
mbed_official	376:cb4d9db17537	923
mbed_official	376:cb4d9db17537	924	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
mbed_official	376:cb4d9db17537	925	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
mbed_official	376:cb4d9db17537	926	} while (0)
mbed_official	376:cb4d9db17537	927
mbed_official	376:cb4d9db17537	928	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
mbed_official	376:cb4d9db17537	929
mbed_official	376:cb4d9db17537	930	/** @brief Macros to force or release the Backup domain reset.
mbed_official	376:cb4d9db17537	931	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	376:cb4d9db17537	932	* and the RTC clock source selection in RCC_CSR register.
mbed_official	376:cb4d9db17537	933	* @note The BKPSRAM is not affected by this reset.
mbed_official	376:cb4d9db17537	934	*/
mbed_official	376:cb4d9db17537	935	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
mbed_official	376:cb4d9db17537	936	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
mbed_official	376:cb4d9db17537	937
mbed_official	376:cb4d9db17537	938	/** @brief Macros to enable or disable the main PLL.
mbed_official	376:cb4d9db17537	939	* @note After enabling the main PLL, the application software should wait on
mbed_official	376:cb4d9db17537	940	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	376:cb4d9db17537	941	* be used as system clock source.
mbed_official	376:cb4d9db17537	942	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	376:cb4d9db17537	943	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	944	*/
mbed_official	376:cb4d9db17537	945	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	376:cb4d9db17537	946	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	376:cb4d9db17537	947
mbed_official	376:cb4d9db17537	948	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	376:cb4d9db17537	949	* @note This function must be used only when the main PLL is disabled.
mbed_official	376:cb4d9db17537	950	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	376:cb4d9db17537	951	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	952	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	376:cb4d9db17537	953	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	376:cb4d9db17537	954	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
mbed_official	376:cb4d9db17537	955	* This parameter must be one of the following values:
mbed_official	376:cb4d9db17537	956	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
mbed_official	376:cb4d9db17537	957	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
mbed_official	376:cb4d9db17537	958	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
mbed_official	376:cb4d9db17537	959	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
mbed_official	376:cb4d9db17537	960	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
mbed_official	376:cb4d9db17537	961	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
mbed_official	376:cb4d9db17537	962	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
mbed_official	376:cb4d9db17537	963	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
mbed_official	376:cb4d9db17537	964	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
mbed_official	376:cb4d9db17537	965	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
mbed_official	376:cb4d9db17537	966	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
mbed_official	376:cb4d9db17537	967	* in Range 3.
mbed_official	376:cb4d9db17537	968	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
mbed_official	376:cb4d9db17537	969	* This parameter must be one of the following values:
mbed_official	376:cb4d9db17537	970	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
mbed_official	376:cb4d9db17537	971	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
mbed_official	376:cb4d9db17537	972	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
mbed_official	376:cb4d9db17537	973	*/
mbed_official	376:cb4d9db17537	974
mbed_official	376:cb4d9db17537	975	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
mbed_official	376:cb4d9db17537	976	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSource__)))
mbed_official	376:cb4d9db17537	977
mbed_official	376:cb4d9db17537	978	/** @brief Macro to get the clock source used as system clock.
mbed_official	376:cb4d9db17537	979	* @retval The clock source used as system clock. The returned value can be one
mbed_official	376:cb4d9db17537	980	* of the following:
mbed_official	376:cb4d9db17537	981	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
mbed_official	376:cb4d9db17537	982	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
mbed_official	376:cb4d9db17537	983	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
mbed_official	376:cb4d9db17537	984	*/
mbed_official	376:cb4d9db17537	985	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	376:cb4d9db17537	986
mbed_official	376:cb4d9db17537	987	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	376:cb4d9db17537	988	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	376:cb4d9db17537	989	* of the following:
mbed_official	376:cb4d9db17537	990	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	376:cb4d9db17537	991	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	376:cb4d9db17537	992	*/
mbed_official	376:cb4d9db17537	993	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
mbed_official	376:cb4d9db17537	994
mbed_official	376:cb4d9db17537	995	/** @defgroup RCC_Flags_Interrupts_Management
mbed_official	376:cb4d9db17537	996	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	376:cb4d9db17537	997	* @{
mbed_official	376:cb4d9db17537	998	*/
mbed_official	376:cb4d9db17537	999
mbed_official	376:cb4d9db17537	1000	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
mbed_official	376:cb4d9db17537	1001	* the selected interrupts).
mbed_official	376:cb4d9db17537	1002	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	376:cb4d9db17537	1003	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	376:cb4d9db17537	1004	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	376:cb4d9db17537	1005	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	376:cb4d9db17537	1006	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	376:cb4d9db17537	1007	* pending bit is cleared.
mbed_official	376:cb4d9db17537	1008	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	376:cb4d9db17537	1009	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1010	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1011	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1012	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1013	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1014	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	376:cb4d9db17537	1015	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	376:cb4d9db17537	1016	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	376:cb4d9db17537	1017	*/
mbed_official	376:cb4d9db17537	1018	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIER_BYTE0_ADDRESS \|= (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1019
mbed_official	376:cb4d9db17537	1020	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
mbed_official	376:cb4d9db17537	1021	* the selected interrupts).
mbed_official	376:cb4d9db17537	1022	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	376:cb4d9db17537	1023	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	376:cb4d9db17537	1024	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	376:cb4d9db17537	1025	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	376:cb4d9db17537	1026	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	376:cb4d9db17537	1027	* pending bit is cleared.
mbed_official	376:cb4d9db17537	1028	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	376:cb4d9db17537	1029	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1030	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1031	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1032	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1033	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1034	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	376:cb4d9db17537	1035	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	376:cb4d9db17537	1036	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	376:cb4d9db17537	1037	*/
mbed_official	376:cb4d9db17537	1038	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIER_BYTE0_ADDRESS &= ~(__INTERRUPT__))
mbed_official	376:cb4d9db17537	1039
mbed_official	376:cb4d9db17537	1040	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official	376:cb4d9db17537	1041	* bits to clear the selected interrupt pending bits.
mbed_official	376:cb4d9db17537	1042	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	376:cb4d9db17537	1043	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1044	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1045	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1046	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1047	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1048	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	376:cb4d9db17537	1049	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	376:cb4d9db17537	1050	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	376:cb4d9db17537	1051	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	376:cb4d9db17537	1052	*/
mbed_official	376:cb4d9db17537	1053	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1054
mbed_official	376:cb4d9db17537	1055	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	376:cb4d9db17537	1056	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	376:cb4d9db17537	1057	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1058	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1059	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1060	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1061	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1062	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	376:cb4d9db17537	1063	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	376:cb4d9db17537	1064	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	376:cb4d9db17537	1065	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	376:cb4d9db17537	1066	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	376:cb4d9db17537	1067	*/
mbed_official	376:cb4d9db17537	1068	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1069
mbed_official	376:cb4d9db17537	1070	/** @brief Set RMVF bit to clear the reset flags.
mbed_official	376:cb4d9db17537	1071	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official	376:cb4d9db17537	1072	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
mbed_official	376:cb4d9db17537	1073	*/
mbed_official	376:cb4d9db17537	1074	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	376:cb4d9db17537	1075
mbed_official	376:cb4d9db17537	1076	/** @brief Check RCC flag is set or not.
mbed_official	376:cb4d9db17537	1077	* @param __FLAG__: specifies the flag to check.
mbed_official	376:cb4d9db17537	1078	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1079	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	376:cb4d9db17537	1080	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
mbed_official	376:cb4d9db17537	1081	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	376:cb4d9db17537	1082	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	376:cb4d9db17537	1083	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
mbed_official	376:cb4d9db17537	1084	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	376:cb4d9db17537	1085	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	376:cb4d9db17537	1086	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official	376:cb4d9db17537	1087	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	376:cb4d9db17537	1088	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	376:cb4d9db17537	1089	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	376:cb4d9db17537	1090	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	376:cb4d9db17537	1091	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	376:cb4d9db17537	1092	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	376:cb4d9db17537	1093	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	376:cb4d9db17537	1094	*/
mbed_official	376:cb4d9db17537	1095	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	376:cb4d9db17537	1096	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
mbed_official	376:cb4d9db17537	1097	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
mbed_official	376:cb4d9db17537	1098
mbed_official	376:cb4d9db17537	1099	/**
mbed_official	376:cb4d9db17537	1100	* @}
mbed_official	376:cb4d9db17537	1101	*/
mbed_official	376:cb4d9db17537	1102
mbed_official	376:cb4d9db17537	1103	#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
mbed_official	376:cb4d9db17537	1104	/**
mbed_official	376:cb4d9db17537	1105	* @}
mbed_official	376:cb4d9db17537	1106	*/
mbed_official	376:cb4d9db17537	1107
mbed_official	376:cb4d9db17537	1108	/* Include RCC HAL Extension module */
mbed_official	376:cb4d9db17537	1109	#include "stm32L0xx_hal_rcc_ex.h"
mbed_official	376:cb4d9db17537	1110
mbed_official	376:cb4d9db17537	1111	/* Exported functions --------------------------------------------------------*/
mbed_official	376:cb4d9db17537	1112	/* Initialization and de-initialization methods ******************************/
mbed_official	376:cb4d9db17537	1113	void HAL_RCC_DeInit(void);
mbed_official	376:cb4d9db17537	1114	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	376:cb4d9db17537	1115	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	376:cb4d9db17537	1116
mbed_official	376:cb4d9db17537	1117	/* Peripheral Control methods ************************************************/
mbed_official	376:cb4d9db17537	1118	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	376:cb4d9db17537	1119	void HAL_RCC_EnableCSS(void);
mbed_official	376:cb4d9db17537	1120	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	376:cb4d9db17537	1121	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	376:cb4d9db17537	1122	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	376:cb4d9db17537	1123	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	376:cb4d9db17537	1124	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	376:cb4d9db17537	1125	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	376:cb4d9db17537	1126
mbed_official	376:cb4d9db17537	1127	/* CSS NMI IRQ handler */
mbed_official	376:cb4d9db17537	1128	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	376:cb4d9db17537	1129
mbed_official	376:cb4d9db17537	1130	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	376:cb4d9db17537	1131	void HAL_RCC_CCSCallback(void);
mbed_official	376:cb4d9db17537	1132
mbed_official	376:cb4d9db17537	1133	/**
mbed_official	376:cb4d9db17537	1134	* @}
mbed_official	376:cb4d9db17537	1135	*/
mbed_official	376:cb4d9db17537	1136
mbed_official	376:cb4d9db17537	1137	/**
mbed_official	376:cb4d9db17537	1138	* @}
mbed_official	376:cb4d9db17537	1139	*/
mbed_official	376:cb4d9db17537	1140
mbed_official	376:cb4d9db17537	1141	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	1142	}
mbed_official	376:cb4d9db17537	1143	#endif
mbed_official	376:cb4d9db17537	1144
mbed_official	376:cb4d9db17537	1145	#endif /* __STM32L0xx_HAL_RCC_H */
mbed_official	376:cb4d9db17537	1146
mbed_official	376:cb4d9db17537	1147	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	14 Jul 2015
Imports:	0
Forks:	0
Commits:	591
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@382:ee426a420dbb, 2014-11-03 (annotated)

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