Erik - / FastIO

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Devices/FastIO_K20D50M_KPSDK.h@22:45b32f07e790, 2016-09-20 (annotated)

Committer:
Sissors
Date:
Tue Sep 20 20:41:42 2016 +0000
Revision:
22:45b32f07e790
Parent:
10:bb22a3dbedb4 
Fixed bug in enabling of port hardware of the F030 (via: https://developer.mbed.org/users/viquiram/)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 9:ab5547eeecfc 1 #if defined(TARGET_K20D50M) | defined(TARGET_KPSDK_MCUS)
Sissors 9:ab5547eeecfc 2
Sissors 9:ab5547eeecfc 3 #include "mbed.h"
Sissors 9:ab5547eeecfc 4 #include "pinmap.h"
Sissors 9:ab5547eeecfc 5
Sissors 9:ab5547eeecfc 6 typedef struct {
Sissors 9:ab5547eeecfc 7 uint32_t mask;
Sissors 9:ab5547eeecfc 8 } fastio_vars;
Sissors 9:ab5547eeecfc 9
Sissors 9:ab5547eeecfc 10 //K20D50M and KPSDK use slightly different pinnames, shifted 2
Sissors 9:ab5547eeecfc 11 #ifdef TARGET_KPSDK_MCUS
Sissors 9:ab5547eeecfc 12 #define PORT_SHIFT GPIO_PORT_SHIFT
Sissors 9:ab5547eeecfc 13 #define PINMASK (1 << (pin & 0x1F))
Sissors 9:ab5547eeecfc 14 #define PCR ((__IO uint32_t*)(PORTA_BASE + ((pin & 0x1F) << 2) + ((pin >> PORT_SHIFT) << PORT_SHIFT) ))
Sissors 9:ab5547eeecfc 15 #else
Sissors 9:ab5547eeecfc 16 #define PINMASK (1 << ((pin & 0x7F) >> 2))
Sissors 9:ab5547eeecfc 17 #define PCR ((__IO uint32_t*)(PORTA_BASE + pin))
Sissors 9:ab5547eeecfc 18 #endif
Sissors 9:ab5547eeecfc 19
Sissors 9:ab5547eeecfc 20 #define PORT_BASE ((GPIO_Type *)(PTA_BASE + ((unsigned int)pin >> PORT_SHIFT) * 0x40))
Sissors 9:ab5547eeecfc 21
Sissors 10:bb22a3dbedb4 22 #define INIT_PIN container.mask = PINMASK; pin_function(pin, 1)
Sissors 9:ab5547eeecfc 23 #define DESTROY_PIN
Sissors 9:ab5547eeecfc 24
Sissors 9:ab5547eeecfc 25 #define SET_DIR_INPUT (PORT_BASE->PDDR &= ~PINMASK)
Sissors 9:ab5547eeecfc 26 #define SET_DIR_OUTPUT (PORT_BASE->PDDR |= PINMASK)
Sissors 9:ab5547eeecfc 27 #define SET_MODE(pull) (*PCR = (*PCR & ~0x3) | pull)
Sissors 9:ab5547eeecfc 28
Sissors 9:ab5547eeecfc 29 #define WRITE_PIN_SET (PORT_BASE->PSOR |= container.mask)
Sissors 9:ab5547eeecfc 30 #define WRITE_PIN_CLR (PORT_BASE->PCOR |= container.mask)
Sissors 9:ab5547eeecfc 31
Sissors 9:ab5547eeecfc 32 #define READ_PIN ((PORT_BASE->PDIR & container.mask) ? 1 : 0)
Sissors 9:ab5547eeecfc 33
Sissors 9:ab5547eeecfc 34 #endif