Erik - / FastIO

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Devices/FastIO_STM32L073XX.h@22:45b32f07e790, 2016-09-20 (annotated)

Committer:
Sissors
Date:
Tue Sep 20 20:41:42 2016 +0000
Revision:
22:45b32f07e790
Parent:
21:a1dfa6c65400 
Fixed bug in enabling of port hardware of the F030 (via: https://developer.mbed.org/users/viquiram/)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
viquiram 21:a1dfa6c65400 1 #if defined(STM32L073xx)
viquiram 21:a1dfa6c65400 2
viquiram 21:a1dfa6c65400 3 #include "mbed.h"
viquiram 21:a1dfa6c65400 4 #include "pinmap.h"
viquiram 21:a1dfa6c65400 5
viquiram 21:a1dfa6c65400 6 typedef struct {
viquiram 21:a1dfa6c65400 7 uint32_t mask;
viquiram 21:a1dfa6c65400 8 } fastio_vars;
viquiram 21:a1dfa6c65400 9
viquiram 21:a1dfa6c65400 10 #define PINMASK (1 << STM_PIN(pin))
viquiram 21:a1dfa6c65400 11 #define PORT ((GPIO_TypeDef *)(GPIOA_BASE + 0x0400 * STM_PORT(pin)))
viquiram 21:a1dfa6c65400 12
viquiram 21:a1dfa6c65400 13 #define INIT_PIN RCC->IOPENR |= (1 << STM_PORT(pin)); (PORT->MODER &= ~(GPIO_MODER_MODE0_1 << (STM_PIN(pin) * 2))); container.mask = PINMASK
viquiram 21:a1dfa6c65400 14 #define DESTROY_PIN
viquiram 21:a1dfa6c65400 15
viquiram 21:a1dfa6c65400 16 #define SET_DIR_INPUT (PORT->MODER &= ~(GPIO_MODER_MODE0_0 << (STM_PIN(pin) * 2)))
viquiram 21:a1dfa6c65400 17 #define SET_DIR_OUTPUT (PORT->MODER |= (GPIO_MODER_MODE0_0 << (STM_PIN(pin) * 2)))
viquiram 21:a1dfa6c65400 18 #define SET_MODE(pull) pin_mode(pin, pull);
viquiram 21:a1dfa6c65400 19
viquiram 21:a1dfa6c65400 20 #define WRITE_PIN_SET (PORT->BSRR = PINMASK)
viquiram 21:a1dfa6c65400 21 #define WRITE_PIN_CLR (PORT->BRR = PINMASK)
viquiram 21:a1dfa6c65400 22
viquiram 21:a1dfa6c65400 23 #define READ_PIN ((PORT->IDR & container.mask) ? 1 : 0)
viquiram 21:a1dfa6c65400 24
viquiram 21:a1dfa6c65400 25 #endif