system_LPC407x_8x_177x_8x.c

00001 /**********************************************************************
00002 * $Id$      system_LPC407x_8x_177x_8x.c         2012-01-16
00003 *//**
00004 * @file     system_LPC407x_8x_177x_8x.c
00005 * @brief    CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
00006 *           for the NXP LPC407x_8x_177x_8x Device Series
00007 *
00008 *           ARM Limited (ARM) is supplying this software for use with
00009 *           Cortex-M processor based microcontrollers.  This file can be
00010 *           freely distributed within development tools that are supporting
00011 *           such ARM based processors.
00012 *
00013 * @version  1.2
00014 * @date     20. June. 2012
00015 * @author   NXP MCU SW Application Team
00016 *
00017 * Copyright(C) 2012, NXP Semiconductor
00018 * All rights reserved.
00019 *
00020 ***********************************************************************
00021 * Software that is described herein is for illustrative purposes only
00022 * which provides customers with programming information regarding the
00023 * products. This software is supplied "AS IS" without any warranties.
00024 * NXP Semiconductors assumes no responsibility or liability for the
00025 * use of the software, conveys no license or title under any patent,
00026 * copyright, or mask work right to the product. NXP Semiconductors
00027 * reserves the right to make changes in the software without
00028 * notification. NXP Semiconductors also make no representation or
00029 * warranty that such application will be suitable for the specified
00030 * use without further testing or modification.
00031 **********************************************************************/
00032 
00033 #include <stdint.h>
00034 #include "LPC407x_8x_177x_8x.h"
00035 #include "system_LPC407x_8x_177x_8x.h"
00036 
00037 #define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
00038 
00039 /*
00040 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
00041 */
00042 /*--------------------- Clock Configuration ----------------------------------
00043 //
00044 //  <e> Clock Configuration
00045 //      <h> System Controls and Status Register (SCS - address 0x400F C1A0)
00046 //          <o1.0>  EMC Shift Control Bit
00047 //                  <i>     Controls how addresses are output on the EMC address pins for static memories
00048 //                  <0=>    Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
00049 //                  <1=>    Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
00050 //
00051 //          <o1.1>  EMC Reset Disable Bit
00052 //                  <i>     If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
00053 //                  <i>     If 1, EMC is still retained its state through a warm reset
00054 //                  <0=>    Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
00055 //                  <1=>    Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
00056 //
00057 //          <o1.2>  EMC Burst Control
00058 //                  <i>     Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
00059 //                  <0=>    Burst enabled (Bit 2 is 0)
00060 //                  <1=>    Bust disbled (Bit 2 is 1)
00061 //
00062 //          <o1.3>  MCIPWR Active Level
00063 //                  <i>     Selects the active level for the SD card interface signal SD_PWR
00064 //                  <0=>    SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
00065 //                  <1=>    SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
00066 //
00067 //          <o1.4>  Main Oscillator Range Select
00068 //                  <0=>    In Range 1 MHz to 20 MHz (Bit 4 is 0)
00069 //                  <1=>    In Range 15 MHz to 25 MHz (Bit 4 is 1)
00070 //
00071 //          <o1.5>  Main Oscillator enable
00072 //                  <i>     0 (zero) means disabled, 1 means enable
00073 //
00074 //          <o1.6>  Main Oscillator status (Read-Only)
00075 //      </h>
00076 //
00077 //      <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
00078 //          <o2.0>  CLKSRC: Select the clock source for sysclk to PLL0 clock
00079 //                  <0=>    Internal RC oscillator (Bit 0 is 0)
00080 //                  <1=>    Main oscillator (Bit 0 is 1)
00081 //      </h>
00082 //
00083 //      <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
00084 //          <i>         F_in  is in the range of 1 MHz to 25 MHz
00085 //          <i>         F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
00086 //          <i>         PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
00087 //
00088 //          <o4.0..4>   MSEL: PLL Multiplier Value
00089 //                      <i>             M Value
00090 //                      <1-32><#-1>
00091 //
00092 //          <o4.5..6>   PSEL: PLL Divider Value
00093 //                      <i>             P Value
00094 //                      <0=>            1
00095 //                      <1=>            2
00096 //                      <2=>            4
00097 //                      <3=>            8
00098 //      </e>
00099 //
00100 //      <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
00101 //          <i>         F_in  is in the range of 1 MHz to 25 MHz
00102 //          <i>         F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
00103 //          <i>         PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
00104 //
00105 //          <o6.0..4>   MSEL: PLL Multiplier Value
00106 //                      <i>             M Value
00107 //                      <1-32><#-1>
00108 //
00109 //          <o6.5..6>   PSEL: PLL Divider Value
00110 //                      <i>     P Value
00111 //                      <0=>    1
00112 //                      <1=>    2
00113 //                      <2=>    4
00114 //                      <3=>    8
00115 //      </e>
00116 //
00117 //      <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
00118 //          <o7.0..4>   CCLKDIV: Select the value for divider of CPU clock (CCLK)
00119 //                      <i>     0: The divider is turned off. No clock will be provided to the CPU
00120 //                      <i>     n: The input clock is divided by n to produce the CPU clock
00121 //                      <0-31>
00122 //
00123 //          <o7.8>      CCLKSEL: Select the input to the divider of CPU clock
00124 //                      <0=>    sysclk clock is used
00125 //                      <1=>    Main PLL0 clock is used
00126 //      </h>
00127 //
00128 //      <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
00129 //          <o8.0..4>   USBDIV: USB clock (source PLL0) divider selection
00130 //                      <0=>    Divider is off and no clock provides to USB subsystem
00131 //                      <4=>    Divider value is 4 (The source clock is divided by 4)
00132 //                      <6=>    Divider value is 6 (The source clock is divided by 6)
00133 //
00134 //          <o8.8..9>   USBSEL: Select the source for USB clock divider
00135 //                      <i>     When CPU clock is selected, the USB can be accessed
00136 //                      <i>     by software but cannot perform USB functions
00137 //                      <0=>    sysclk clock (the clock input to PLL0)
00138 //                      <1=>    The clock output from PLL0
00139 //                      <2=>    The clock output from PLL1
00140 //      </h>
00141 //
00142 //      <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
00143 //          <o9.0>  EMCDIV: Set the divider for EMC clock
00144 //                  <0=> Divider value is 1
00145 //                  <1=> Divider value is 2 (EMC clock is equal a half of input clock)
00146 //      </h>
00147 //
00148 //      <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
00149 //          <o10.0..4>  PCLKDIV: APB Peripheral clock divider
00150 //                      <i> 0: The divider is turned off. No clock will be provided to APB peripherals
00151 //                      <i> n: The input clock is divided by n to produce the APB peripheral clock
00152 //                      <0-31>
00153 //      </h>
00154 //
00155 //      <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
00156 //          <o11.0..4>  SPIFIDIV: Set the divider for SPIFI clock
00157 //                      <i> 0: The divider is turned off. No clock will be provided to the SPIFI
00158 //                      <i> n: The input clock is divided by n to produce the SPIFI clock
00159 //                      <0-31>
00160 //
00161 //          <o11.8..9>  SPIFISEL: Select the input clock for SPIFI clock divider
00162 //                      <0=>    sysclk clock (the clock input to PLL0)
00163 //                      <1=>    The clock output from PLL0
00164 //                      <2=>    The clock output from PLL1
00165 //      </h>
00166 //
00167 //      <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
00168 //          <o12.0>     PCLCD: LCD controller power/clock enable (bit 0)
00169 //          <o12.1>     PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
00170 //          <o12.2>     PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
00171 //          <o12.3>     PCUART0: UART 0 power/clock enable (bit 3)
00172 //          <o12.4>     PCUART1: UART 1 power/clock enable (bit 4)
00173 //          <o12.5>     PCPWM0: PWM0 power/clock enable (bit 5)
00174 //          <o12.6>     PCPWM1: PWM1 power/clock enable (bit 6)
00175 //          <o12.7>     PCI2C0: I2C 0 interface power/clock enable (bit 7)
00176 //          <o12.8>     PCUART4: UART 4 power/clock enable (bit 8)
00177 //          <o12.9>     PCRTC: RTC and Event Recorder power/clock enable (bit 9)
00178 //          <o12.10>    PCSSP1: SSP 1 interface power/clock enable (bit 10)
00179 //          <o12.11>    PCEMC: External Memory Controller power/clock enable (bit 11)
00180 //          <o12.12>    PCADC: A/D converter power/clock enable (bit 12)
00181 //          <o12.13>    PCCAN1: CAN controller 1 power/clock enable (bit 13)
00182 //          <o12.14>    PCCAN2: CAN controller 2 power/clock enable (bit 14)
00183 //          <o12.15>    PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
00184 //          <o12.17>    PCMCPWM: Motor Control PWM power/clock enable (bit 17)
00185 //          <o12.18>    PCQEI: Quadrature encoder interface power/clock enable (bit 18)
00186 //          <o12.19>    PCI2C1: I2C 1 interface power/clock enable (bit 19)
00187 //          <o12.20>    PCSSP2: SSP 2 interface power/clock enable (bit 20)
00188 //          <o12.21>    PCSSP0: SSP 0 interface power/clock enable (bit 21)
00189 //          <o12.22>    PCTIM2: Timer 2 power/clock enable (bit 22)
00190 //          <o12.23>    PCTIM3: Timer 3 power/clock enable (bit 23)
00191 //          <o12.24>    PCUART2: UART 2 power/clock enable (bit 24)
00192 //          <o12.25>    PCUART3: UART 3 power/clock enable (bit 25)
00193 //          <o12.26>    PCI2C2: I2C 2 interface power/clock enable (bit 26)
00194 //          <o12.27>    PCI2S: I2S interface power/clock enable (bit 27)
00195 //          <o12.28>    PCSDC: SD Card interface power/clock enable (bit 28)
00196 //          <o12.29>    PCGPDMA: GPDMA function power/clock enable (bit 29)
00197 //          <o12.30>    PCENET: Ethernet block power/clock enable (bit 30)
00198 //          <o12.31>    PCUSB: USB interface power/clock enable (bit 31)
00199 //      </h>
00200 //
00201 //      <h> Clock Output Configuration Register (CLKOUTCFG)
00202 //          <o13.0..3>  CLKOUTSEL: Clock Source for CLKOUT Selection
00203 //                      <0=>    CPU clock
00204 //                      <1=>    Main Oscillator
00205 //                      <2=>    Internal RC Oscillator
00206 //                      <3=>    USB clock
00207 //                      <4=>    RTC Oscillator
00208 //                      <5=>    unused
00209 //                      <6=>    Watchdog Oscillator
00210 //
00211 //          <o13.4..7>  CLKOUTDIV: Output Clock Divider
00212 //                      <1-16><#-1>
00213 //
00214 //          <o13.8>     CLKOUT_EN: CLKOUT enable
00215 //      </h>
00216 //
00217 //  </e>
00218 */
00219 
00220 #define CLOCK_SETUP           1
00221 #define SCS_Val               0x00000020
00222 #define CLKSRCSEL_Val         0x00000001
00223 #define PLL0_SETUP            1
00224 #define PLL0CFG_Val           0x00000009
00225 #define PLL1_SETUP            1
00226 #define PLL1CFG_Val           0x00000023
00227 #define CCLKSEL_Val           0x00000101
00228 #define USBCLKSEL_Val         0x00000201
00229 #define EMCCLKSEL_Val         0x00000001
00230 #define PCLKSEL_Val           0x00000002
00231 #define SPIFICLKSEL_Val       0x00000002
00232 #define PCONP_Val             0x042887DE
00233 #define CLKOUTCFG_Val         0x00000100
00234 
00235 #ifdef CORE_M4
00236 #define LPC_CPACR           0xE000ED88
00237 
00238 #define SCB_MVFR0           0xE000EF40
00239 #define SCB_MVFR0_RESET     0x10110021
00240 
00241 #define SCB_MVFR1           0xE000EF44
00242 #define SCB_MVFR1_RESET     0x11000011
00243 #endif
00244 
00245 
00246 /*--------------------- Flash Accelerator Configuration ----------------------
00247 //
00248 //  <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
00249 //      <o1.12..15> FLASHTIM: Flash Access Time
00250 //                  <0=>    1 CPU clock (for CPU clock up to 20 MHz)
00251 //                  <1=>    2 CPU clocks (for CPU clock up to 40 MHz)
00252 //                  <2=>    3 CPU clocks (for CPU clock up to 60 MHz)
00253 //                  <3=>    4 CPU clocks (for CPU clock up to 80 MHz)
00254 //                  <4=>    5 CPU clocks (for CPU clock up to 100 MHz)
00255 //                  <5=>    6 CPU clocks (for any CPU clock)
00256 //  </e>
00257 */
00258 
00259 #define FLASH_SETUP           1
00260 #define FLASHCFG_Val          0x00005000
00261 
00262 /*----------------------------------------------------------------------------
00263   Check the register settings
00264  *----------------------------------------------------------------------------*/
00265 #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
00266 #define CHECK_RSVD(val, mask)                     (val & mask)
00267 
00268 /* Clock Configuration -------------------------------------------------------*/
00269 #if (CHECK_RSVD((SCS_Val),       ~0x0000003F))
00270    #error "SCS: Invalid values of reserved bits!"
00271 #endif
00272 
00273 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
00274    #error "CLKSRCSEL: Value out of range!"
00275 #endif
00276 
00277 #if (CHECK_RSVD((PLL0CFG_Val),   ~0x0000007F))
00278    #error "PLL0CFG: Invalid values of reserved bits!"
00279 #endif
00280 
00281 #if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
00282    #error "PLL1CFG: Invalid values of reserved bits!"
00283 #endif
00284 
00285 #if (CHECK_RSVD((CCLKSEL_Val),   ~0x0000011F))
00286    #error "CCLKSEL: Invalid values of reserved bits!"
00287 #endif
00288 
00289 #if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
00290    #error "USBCLKSEL: Invalid values of reserved bits!"
00291 #endif
00292 
00293 #if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
00294    #error "EMCCLKSEL: Invalid values of reserved bits!"
00295 #endif
00296 
00297 #if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
00298    #error "PCLKSEL: Invalid values of reserved bits!"
00299 #endif
00300 
00301 #if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
00302    #error "PCONP: Invalid values of reserved bits!"
00303 #endif
00304 
00305 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
00306    #error "CLKOUTCFG: Invalid values of reserved bits!"
00307 #endif
00308 
00309 /* Flash Accelerator Configuration -------------------------------------------*/
00310 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
00311    #warning "FLASHCFG: Invalid values of reserved bits!"
00312 #endif
00313 
00314 
00315 /*----------------------------------------------------------------------------
00316   DEFINES
00317  *----------------------------------------------------------------------------*/
00318 /* pll_out_clk = F_cco / (2 � P)
00319    F_cco = pll_in_clk � M � 2 � P */
00320 #define __M                   ((PLL0CFG_Val & 0x1F) + 1)
00321 #define __PLL0_CLK(__F_IN)    (__F_IN * __M)
00322 #define __CCLK_DIV            (CCLKSEL_Val & 0x1F)
00323 #define __PCLK_DIV            (PCLKSEL_Val & 0x1F)
00324 #define __ECLK_DIV            ((EMCCLKSEL_Val & 0x01) + 1)
00325 
00326 /* Determine core clock frequency according to settings */
00327 #if (CLOCK_SETUP)                       /* Clock Setup                        */
00328 
00329   #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
00330    #error "Main Oscillator is selected as clock source but is not enabled!"
00331   #endif
00332 
00333   #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
00334    #error "Main PLL is selected as clock source but is not enabled!"
00335   #endif
00336 
00337   #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */
00338     #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
00339         #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
00340         #define __PER_CLK  (IRC_OSC/  __PCLK_DIV)
00341         #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
00342     #else                               /* sysclk = osc_clk */
00343         #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
00344         #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)
00345         #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
00346     #endif
00347   #else                                 /* cclk = pll_clk */
00348     #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
00349         #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
00350         #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
00351         #define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
00352     #else                               /* sysclk = osc_clk */
00353         #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
00354         #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
00355         #define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
00356     #endif
00357   #endif
00358 
00359 #else
00360         #define __CORE_CLK (IRC_OSC)
00361         #define __PER_CLK  (IRC_OSC)
00362         #define __EMC_CLK  (__CORE_CLK)
00363 #endif
00364 
00365 /*----------------------------------------------------------------------------
00366   Clock Variable definitions
00367  *----------------------------------------------------------------------------*/
00368 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
00369 uint32_t PeripheralClock  = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk)  */
00370 uint32_t EMCClock         = __EMC_CLK; /*!< EMC Clock Frequency                */
00371 uint32_t USBClock         = (48000000UL);          /*!< USB Clock Frequency - this value will
00372                                     be updated after call SystemCoreClockUpdate, should be 48MHz*/
00373 
00374 
00375 /*----------------------------------------------------------------------------
00376   Clock functions
00377  *----------------------------------------------------------------------------*/
00378 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
00379 {
00380   /* Determine clock frequency according to clock register values             */
00381   if ((LPC_SC->CCLKSEL &0x100) == 0) {            /* cclk = sysclk    */
00382     if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
00383           SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
00384           PeripheralClock  = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
00385           EMCClock         = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
00386     }
00387     else {                                        /* sysclk = osc_clk */
00388       if ((LPC_SC->SCS & 0x40) == 0) {
00389           SystemCoreClock = 0;                      /* this should never happen! */
00390           PeripheralClock  = 0;
00391           EMCClock         = 0;
00392       }
00393       else {
00394           SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
00395           PeripheralClock  = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
00396           EMCClock         = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
00397       }
00398     }
00399   }
00400   else {                                          /* cclk = pll_clk */
00401     if ((LPC_SC->PLL0STAT & 0x100) == 0) {        /* PLL0 not enabled */
00402           SystemCoreClock = 0;                      /* this should never happen! */
00403           PeripheralClock  = 0;
00404           EMCClock         = 0;
00405     }
00406     else {
00407       if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
00408           uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
00409           uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
00410           uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
00411           uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
00412           SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
00413           PeripheralClock  = __CLK_DIV(IRC_OSC * mul , per_div);
00414           EMCClock         = SystemCoreClock / emc_div;
00415       }
00416       else {                                        /* sysclk = osc_clk */
00417         if ((LPC_SC->SCS & 0x40) == 0) {
00418           SystemCoreClock = 0;                      /* this should never happen! */
00419           PeripheralClock  = 0;
00420           EMCClock         = 0;
00421         }
00422         else {
00423           uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
00424           uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
00425           uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
00426           uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
00427           SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
00428           PeripheralClock  = __CLK_DIV(OSC_CLK * mul , per_div);
00429           EMCClock         = SystemCoreClock / emc_div;
00430         }
00431       }
00432     }
00433   }
00434   /* ---update USBClock------------------*/
00435   if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
00436   {
00437       switch (LPC_SC->USBCLKSEL & 0x1F)
00438       {
00439       case 0:
00440           USBClock  = 0; //no clock will be provided to the USB subsystem
00441           break;
00442       case 4:
00443       case 6:
00444             {
00445                  uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
00446                  uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
00447           if(LPC_SC->CLKSRCSEL & 0x01)  //pll_clk_in = main_osc
00448               USBClock  = OSC_CLK * mul / usb_div;
00449           else //pll_clk_in = irc_clk
00450               USBClock  = IRC_OSC * mul / usb_div;
00451             }
00452             break;
00453       default:
00454           USBClock  = 0;  /* this should never happen! */
00455       }
00456   }
00457   else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
00458   {
00459       if(LPC_SC->CLKSRCSEL & 0x01)  //pll1_clk_in = main_osc
00460             USBClock  = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
00461       else //pll1_clk_in = irc_clk
00462             USBClock  = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
00463   }
00464   else
00465       USBClock  = 0; /* this should never happen! */
00466 }
00467 
00468   /* Determine clock frequency according to clock register values             */
00469 
00470 #ifdef CORE_M4
00471 
00472 void fpu_init(void)
00473 {
00474  // from arm trm manual:
00475 //                ; CPACR is located at address 0xE000ED88
00476 //                LDR.W R0, =0xE000ED88
00477 //                ; Read CPACR
00478 //                LDR R1, [R0]
00479 //                ; Set bits 20-23 to enable CP10 and CP11 coprocessors
00480 //                ORR R1, R1, #(0xF << 20)
00481 //                ; Write back the modified value to the CPACR
00482 //                STR R1, [R0]
00483 
00484 
00485     volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
00486     volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
00487     volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
00488     volatile uint32_t Cpacr;
00489     volatile uint32_t Mvfr0;
00490     volatile uint32_t Mvfr1;
00491     char vfpPresent = 0;
00492 
00493     Mvfr0 = *regMvfr0;
00494     Mvfr1 = *regMvfr1;
00495 
00496     vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
00497 
00498     if(vfpPresent)
00499     {
00500         Cpacr = *regCpacr;
00501         Cpacr |= (0xF << 20);
00502         *regCpacr = Cpacr;   // enable CP10 and CP11 for full access
00503     }
00504 
00505 }
00506 #endif
00507 
00508 /**
00509  * Initialize the system
00510  *
00511  * @param  none
00512  * @return none
00513  *
00514  * @brief  Setup the microcontroller system.
00515  *         Initialize the System.
00516  */
00517 void SystemInit (void)
00518 {
00519 #ifndef __CODE_RED
00520 #ifdef CORE_M4
00521 fpu_init();
00522 #endif
00523 #endif
00524 
00525 #if (CLOCK_SETUP)                       /* Clock Setup                        */
00526   LPC_SC->SCS       = SCS_Val;
00527   if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
00528     while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
00529   }
00530 
00531   LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/
00532 
00533 #if (PLL0_SETUP)
00534   LPC_SC->PLL0CFG   = PLL0CFG_Val;
00535   LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
00536   LPC_SC->PLL0FEED  = 0xAA;
00537   LPC_SC->PLL0FEED  = 0x55;
00538   while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */
00539 #endif
00540 
00541 #if (PLL1_SETUP)
00542   LPC_SC->PLL1CFG   = PLL1CFG_Val;
00543   LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
00544   LPC_SC->PLL1FEED  = 0xAA;
00545   LPC_SC->PLL1FEED  = 0x55;
00546   while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
00547 #endif
00548 
00549   LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */
00550   LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */
00551   LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */
00552   LPC_SC->SPIFICLKSEL  = SPIFICLKSEL_Val;  /* SPIFI Clock Selection              */
00553   LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */
00554   LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
00555   LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
00556 #endif
00557 
00558   LPC_SC->PBOOST    |= 0x03;            /* Power Boost control              */
00559 
00560 #if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
00561   LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;
00562 #endif
00563 #ifndef __CODE_RED
00564 #ifdef  __RAM_MODE__
00565   SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
00566 #else
00567   SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
00568 #endif
00569 #endif
00570   SystemCoreClockUpdate();
00571 }