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fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088
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system_LPC17xx.c
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00001 /**************************************************************************//** 00002 * @file system_LPC17xx.c 00003 * @brief CMSIS Cortex-M3 Device System Source File for 00004 * NXP LPC17xx Device Series 00005 * @version V1.11 00006 * @date 21. June 2011 00007 * 00008 * @note 00009 * Copyright (C) 2009-2011 ARM Limited. All rights reserved. 00010 * 00011 * @par 00012 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00013 * processor based microcontrollers. This file can be freely distributed 00014 * within development tools that are supporting such ARM based processors. 00015 * 00016 * @par 00017 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00018 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00019 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00020 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00021 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00022 * 00023 ******************************************************************************/ 00024 00025 00026 #include <stdint.h> 00027 #include "LPC17xx.h" 00028 00029 00030 /** @addtogroup LPC17xx_System 00031 * @{ 00032 */ 00033 00034 /* 00035 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 00036 */ 00037 00038 /*--------------------- Clock Configuration ---------------------------------- 00039 // 00040 // <e> Clock Configuration 00041 // <h> System Controls and Status Register (SCS) 00042 // <o1.4> OSCRANGE: Main Oscillator Range Select 00043 // <0=> 1 MHz to 20 MHz 00044 // <1=> 15 MHz to 25 MHz 00045 // <e1.5> OSCEN: Main Oscillator Enable 00046 // </e> 00047 // </h> 00048 // 00049 // <h> Clock Source Select Register (CLKSRCSEL) 00050 // <o2.0..1> CLKSRC: PLL Clock Source Selection 00051 // <0=> Internal RC oscillator 00052 // <1=> Main oscillator 00053 // <2=> RTC oscillator 00054 // </h> 00055 // 00056 // <e3> PLL0 Configuration (Main PLL) 00057 // <h> PLL0 Configuration Register (PLL0CFG) 00058 // <i> F_cco0 = (2 * M * F_in) / N 00059 // <i> F_in must be in the range of 32 kHz to 50 MHz 00060 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz 00061 // <o4.0..14> MSEL: PLL Multiplier Selection 00062 // <6-32768><#-1> 00063 // <i> M Value 00064 // <o4.16..23> NSEL: PLL Divider Selection 00065 // <1-256><#-1> 00066 // <i> N Value 00067 // </h> 00068 // </e> 00069 // 00070 // <e5> PLL1 Configuration (USB PLL) 00071 // <h> PLL1 Configuration Register (PLL1CFG) 00072 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) 00073 // <i> F_cco1 = F_osc * M * 2 * P 00074 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz 00075 // <o6.0..4> MSEL: PLL Multiplier Selection 00076 // <1-32><#-1> 00077 // <i> M Value (for USB maximum value is 4) 00078 // <o6.5..6> PSEL: PLL Divider Selection 00079 // <0=> 1 00080 // <1=> 2 00081 // <2=> 4 00082 // <3=> 8 00083 // <i> P Value 00084 // </h> 00085 // </e> 00086 // 00087 // <h> CPU Clock Configuration Register (CCLKCFG) 00088 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 00089 // <1-256><#-1> 00090 // </h> 00091 // 00092 // <h> USB Clock Configuration Register (USBCLKCFG) 00093 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 00094 // <0-15> 00095 // <i> Divide is USBSEL + 1 00096 // </h> 00097 // 00098 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0) 00099 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT 00100 // <0=> Pclk = Cclk / 4 00101 // <1=> Pclk = Cclk 00102 // <2=> Pclk = Cclk / 2 00103 // <3=> Pclk = Hclk / 8 00104 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 00105 // <0=> Pclk = Cclk / 4 00106 // <1=> Pclk = Cclk 00107 // <2=> Pclk = Cclk / 2 00108 // <3=> Pclk = Hclk / 8 00109 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 00110 // <0=> Pclk = Cclk / 4 00111 // <1=> Pclk = Cclk 00112 // <2=> Pclk = Cclk / 2 00113 // <3=> Pclk = Hclk / 8 00114 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 00115 // <0=> Pclk = Cclk / 4 00116 // <1=> Pclk = Cclk 00117 // <2=> Pclk = Cclk / 2 00118 // <3=> Pclk = Hclk / 8 00119 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 00120 // <0=> Pclk = Cclk / 4 00121 // <1=> Pclk = Cclk 00122 // <2=> Pclk = Cclk / 2 00123 // <3=> Pclk = Hclk / 8 00124 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 00125 // <0=> Pclk = Cclk / 4 00126 // <1=> Pclk = Cclk 00127 // <2=> Pclk = Cclk / 2 00128 // <3=> Pclk = Hclk / 8 00129 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 00130 // <0=> Pclk = Cclk / 4 00131 // <1=> Pclk = Cclk 00132 // <2=> Pclk = Cclk / 2 00133 // <3=> Pclk = Hclk / 8 00134 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI 00135 // <0=> Pclk = Cclk / 4 00136 // <1=> Pclk = Cclk 00137 // <2=> Pclk = Cclk / 2 00138 // <3=> Pclk = Hclk / 8 00139 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 00140 // <0=> Pclk = Cclk / 4 00141 // <1=> Pclk = Cclk 00142 // <2=> Pclk = Cclk / 2 00143 // <3=> Pclk = Hclk / 8 00144 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC 00145 // <0=> Pclk = Cclk / 4 00146 // <1=> Pclk = Cclk 00147 // <2=> Pclk = Cclk / 2 00148 // <3=> Pclk = Hclk / 8 00149 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC 00150 // <0=> Pclk = Cclk / 4 00151 // <1=> Pclk = Cclk 00152 // <2=> Pclk = Cclk / 2 00153 // <3=> Pclk = Hclk / 8 00154 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 00155 // <0=> Pclk = Cclk / 4 00156 // <1=> Pclk = Cclk 00157 // <2=> Pclk = Cclk / 2 00158 // <3=> Pclk = Hclk / 6 00159 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 00160 // <0=> Pclk = Cclk / 4 00161 // <1=> Pclk = Cclk 00162 // <2=> Pclk = Cclk / 2 00163 // <3=> Pclk = Hclk / 6 00164 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF 00165 // <0=> Pclk = Cclk / 4 00166 // <1=> Pclk = Cclk 00167 // <2=> Pclk = Cclk / 2 00168 // <3=> Pclk = Hclk / 6 00169 // </h> 00170 // 00171 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1) 00172 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface 00173 // <0=> Pclk = Cclk / 4 00174 // <1=> Pclk = Cclk 00175 // <2=> Pclk = Cclk / 2 00176 // <3=> Pclk = Hclk / 8 00177 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs 00178 // <0=> Pclk = Cclk / 4 00179 // <1=> Pclk = Cclk 00180 // <2=> Pclk = Cclk / 2 00181 // <3=> Pclk = Hclk / 8 00182 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block 00183 // <0=> Pclk = Cclk / 4 00184 // <1=> Pclk = Cclk 00185 // <2=> Pclk = Cclk / 2 00186 // <3=> Pclk = Hclk / 8 00187 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 00188 // <0=> Pclk = Cclk / 4 00189 // <1=> Pclk = Cclk 00190 // <2=> Pclk = Cclk / 2 00191 // <3=> Pclk = Hclk / 8 00192 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 00193 // <0=> Pclk = Cclk / 4 00194 // <1=> Pclk = Cclk 00195 // <2=> Pclk = Cclk / 2 00196 // <3=> Pclk = Hclk / 8 00197 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 00198 // <0=> Pclk = Cclk / 4 00199 // <1=> Pclk = Cclk 00200 // <2=> Pclk = Cclk / 2 00201 // <3=> Pclk = Hclk / 8 00202 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 00203 // <0=> Pclk = Cclk / 4 00204 // <1=> Pclk = Cclk 00205 // <2=> Pclk = Cclk / 2 00206 // <3=> Pclk = Hclk / 8 00207 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 00208 // <0=> Pclk = Cclk / 4 00209 // <1=> Pclk = Cclk 00210 // <2=> Pclk = Cclk / 2 00211 // <3=> Pclk = Hclk / 8 00212 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 00213 // <0=> Pclk = Cclk / 4 00214 // <1=> Pclk = Cclk 00215 // <2=> Pclk = Cclk / 2 00216 // <3=> Pclk = Hclk / 8 00217 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 00218 // <0=> Pclk = Cclk / 4 00219 // <1=> Pclk = Cclk 00220 // <2=> Pclk = Cclk / 2 00221 // <3=> Pclk = Hclk / 8 00222 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S 00223 // <0=> Pclk = Cclk / 4 00224 // <1=> Pclk = Cclk 00225 // <2=> Pclk = Cclk / 2 00226 // <3=> Pclk = Hclk / 8 00227 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer 00228 // <0=> Pclk = Cclk / 4 00229 // <1=> Pclk = Cclk 00230 // <2=> Pclk = Cclk / 2 00231 // <3=> Pclk = Hclk / 8 00232 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block 00233 // <0=> Pclk = Cclk / 4 00234 // <1=> Pclk = Cclk 00235 // <2=> Pclk = Cclk / 2 00236 // <3=> Pclk = Hclk / 8 00237 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM 00238 // <0=> Pclk = Cclk / 4 00239 // <1=> Pclk = Cclk 00240 // <2=> Pclk = Cclk / 2 00241 // <3=> Pclk = Hclk / 8 00242 // </h> 00243 // 00244 // <h> Power Control for Peripherals Register (PCONP) 00245 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable 00246 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable 00247 // <o11.3> PCUART0: UART 0 power/clock enable 00248 // <o11.4> PCUART1: UART 1 power/clock enable 00249 // <o11.6> PCPWM1: PWM 1 power/clock enable 00250 // <o11.7> PCI2C0: I2C interface 0 power/clock enable 00251 // <o11.8> PCSPI: SPI interface power/clock enable 00252 // <o11.9> PCRTC: RTC power/clock enable 00253 // <o11.10> PCSSP1: SSP interface 1 power/clock enable 00254 // <o11.12> PCAD: A/D converter power/clock enable 00255 // <o11.13> PCCAN1: CAN controller 1 power/clock enable 00256 // <o11.14> PCCAN2: CAN controller 2 power/clock enable 00257 // <o11.15> PCGPIO: GPIOs power/clock enable 00258 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable 00259 // <o11.17> PCMC: Motor control PWM power/clock enable 00260 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable 00261 // <o11.19> PCI2C1: I2C interface 1 power/clock enable 00262 // <o11.21> PCSSP0: SSP interface 0 power/clock enable 00263 // <o11.22> PCTIM2: Timer 2 power/clock enable 00264 // <o11.23> PCTIM3: Timer 3 power/clock enable 00265 // <o11.24> PCUART2: UART 2 power/clock enable 00266 // <o11.25> PCUART3: UART 3 power/clock enable 00267 // <o11.26> PCI2C2: I2C interface 2 power/clock enable 00268 // <o11.27> PCI2S: I2S interface power/clock enable 00269 // <o11.29> PCGPDMA: GP DMA function power/clock enable 00270 // <o11.30> PCENET: Ethernet block power/clock enable 00271 // <o11.31> PCUSB: USB interface power/clock enable 00272 // </h> 00273 // 00274 // <h> Clock Output Configuration Register (CLKOUTCFG) 00275 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT 00276 // <0=> CPU clock 00277 // <1=> Main oscillator 00278 // <2=> Internal RC oscillator 00279 // <3=> USB clock 00280 // <4=> RTC oscillator 00281 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT 00282 // <1-16><#-1> 00283 // <o12.8> CLKOUT_EN: CLKOUT enable control 00284 // </h> 00285 // 00286 // </e> 00287 */ 00288 00289 00290 00291 /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines 00292 @{ 00293 */ 00294 00295 #define CLOCK_SETUP 1 00296 #define SCS_Val 0x00000020 00297 #define CLKSRCSEL_Val 0x00000001 00298 #define PLL0_SETUP 1 00299 00300 #ifdef MCB1700 00301 # define PLL0CFG_Val 0x00050063 00302 # define PLL1_SETUP 1 00303 # define PLL1CFG_Val 0x00000023 00304 # define CCLKCFG_Val 0x00000003 00305 # define USBCLKCFG_Val 0x00000000 00306 #else 00307 # define PLL0CFG_Val 0x0000000B 00308 # define PLL1_SETUP 0 00309 # define PLL1CFG_Val 0x00000000 00310 # define CCLKCFG_Val 0x00000002 00311 # define USBCLKCFG_Val 0x00000005 00312 #endif 00313 00314 #define PCLKSEL0_Val 0x00000000 00315 #define PCLKSEL1_Val 0x00000000 00316 #define PCONP_Val 0x042887DE 00317 #define CLKOUTCFG_Val 0x00000000 00318 00319 00320 /*--------------------- Flash Accelerator Configuration ---------------------- 00321 // 00322 // <e> Flash Accelerator Configuration 00323 // <o1.12..15> FLASHTIM: Flash Access Time 00324 // <0=> 1 CPU clock (for CPU clock up to 20 MHz) 00325 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz) 00326 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz) 00327 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz) 00328 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz) 00329 // <5=> 6 CPU clocks (for any CPU clock) 00330 // </e> 00331 */ 00332 #define FLASH_SETUP 1 00333 #define FLASHCFG_Val 0x0000303A 00334 00335 /* 00336 //-------- <<< end of configuration section >>> ------------------------------ 00337 */ 00338 00339 /*---------------------------------------------------------------------------- 00340 Check the register settings 00341 *----------------------------------------------------------------------------*/ 00342 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) 00343 #define CHECK_RSVD(val, mask) (val & mask) 00344 00345 /* Clock Configuration -------------------------------------------------------*/ 00346 #if (CHECK_RSVD((SCS_Val), ~0x00000030)) 00347 #error "SCS: Invalid values of reserved bits!" 00348 #endif 00349 00350 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) 00351 #error "CLKSRCSEL: Value out of range!" 00352 #endif 00353 00354 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) 00355 #error "PLL0CFG: Invalid values of reserved bits!" 00356 #endif 00357 00358 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) 00359 #error "PLL1CFG: Invalid values of reserved bits!" 00360 #endif 00361 00362 #if (PLL0_SETUP) /* if PLL0 is used */ 00363 #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ 00364 #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" 00365 #endif 00366 #endif 00367 00368 #if (CHECK_RANGE((CCLKCFG_Val), 2, 255)) 00369 #error "CCLKCFG: Value out of range!" 00370 #endif 00371 00372 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) 00373 #error "USBCLKCFG: Invalid values of reserved bits!" 00374 #endif 00375 00376 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) 00377 #error "PCLKSEL0: Invalid values of reserved bits!" 00378 #endif 00379 00380 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) 00381 #error "PCLKSEL1: Invalid values of reserved bits!" 00382 #endif 00383 00384 #if (CHECK_RSVD((PCONP_Val), 0x10100821)) 00385 #error "PCONP: Invalid values of reserved bits!" 00386 #endif 00387 00388 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) 00389 #error "CLKOUTCFG: Invalid values of reserved bits!" 00390 #endif 00391 00392 /* Flash Accelerator Configuration -------------------------------------------*/ 00393 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) 00394 #error "FLASHCFG: Invalid values of reserved bits!" 00395 #endif 00396 00397 00398 /*---------------------------------------------------------------------------- 00399 DEFINES 00400 *----------------------------------------------------------------------------*/ 00401 00402 /*---------------------------------------------------------------------------- 00403 Define clocks 00404 *----------------------------------------------------------------------------*/ 00405 #define XTAL (12000000UL) /* Oscillator frequency */ 00406 #define OSC_CLK ( XTAL) /* Main oscillator frequency */ 00407 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ 00408 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ 00409 00410 00411 /* F_cco0 = (2 * M * F_in) / N */ 00412 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) 00413 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) 00414 #define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) 00415 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) 00416 00417 /* Determine core clock frequency according to settings */ 00418 #if (PLL0_SETUP) 00419 #if ((CLKSRCSEL_Val & 0x03) == 1) 00420 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) 00421 #elif ((CLKSRCSEL_Val & 0x03) == 2) 00422 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) 00423 #else 00424 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) 00425 #endif 00426 #else 00427 #if ((CLKSRCSEL_Val & 0x03) == 1) 00428 #define __CORE_CLK (OSC_CLK / __CCLK_DIV) 00429 #elif ((CLKSRCSEL_Val & 0x03) == 2) 00430 #define __CORE_CLK (RTC_CLK / __CCLK_DIV) 00431 #else 00432 #define __CORE_CLK (IRC_OSC / __CCLK_DIV) 00433 #endif 00434 #endif 00435 00436 /** 00437 * @} 00438 */ 00439 00440 00441 /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables 00442 @{ 00443 */ 00444 /*---------------------------------------------------------------------------- 00445 Clock Variable definitions 00446 *----------------------------------------------------------------------------*/ 00447 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ 00448 00449 /** 00450 * @} 00451 */ 00452 00453 00454 /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions 00455 @{ 00456 */ 00457 00458 /** 00459 * Update SystemCoreClock variable 00460 * 00461 * @param none 00462 * @return none 00463 * 00464 * @brief Updates the SystemCoreClock with current core Clock 00465 * retrieved from cpu registers. 00466 */void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ 00467 { 00468 /* Determine clock frequency according to clock register values */ 00469 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ 00470 switch (LPC_SC->CLKSRCSEL & 0x03) { 00471 case 0: /* Int. RC oscillator => PLL0 */ 00472 case 3: /* Reserved, default to Int. RC */ 00473 SystemCoreClock = (IRC_OSC * 00474 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00475 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 00476 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00477 break; 00478 case 1: /* Main oscillator => PLL0 */ 00479 SystemCoreClock = (OSC_CLK * 00480 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00481 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 00482 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00483 break; 00484 case 2: /* RTC oscillator => PLL0 */ 00485 SystemCoreClock = (RTC_CLK * 00486 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00487 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 00488 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00489 break; 00490 } 00491 } else { 00492 switch (LPC_SC->CLKSRCSEL & 0x03) { 00493 case 0: /* Int. RC oscillator => PLL0 */ 00494 case 3: /* Reserved, default to Int. RC */ 00495 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00496 break; 00497 case 1: /* Main oscillator => PLL0 */ 00498 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00499 break; 00500 case 2: /* RTC oscillator => PLL0 */ 00501 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00502 break; 00503 } 00504 } 00505 00506 } 00507 00508 /** 00509 * Initialize the system 00510 * 00511 * @param none 00512 * @return none 00513 * 00514 * @brief Setup the microcontroller system. 00515 * Initialize the System. 00516 */ 00517 void SystemInit (void) 00518 { 00519 #if (CLOCK_SETUP) /* Clock Setup */ 00520 LPC_SC->SCS = SCS_Val; 00521 if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */ 00522 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ 00523 } 00524 00525 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ 00526 /* Periphral clock must be selected before PLL0 enabling and connecting 00527 * - according errata.lpc1768-16.March.2010 - 00528 */ 00529 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ 00530 LPC_SC->PCLKSEL1 = PCLKSEL1_Val; 00531 00532 #if (PLL0_SETUP) 00533 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ 00534 00535 LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ 00536 LPC_SC->PLL0FEED = 0xAA; 00537 LPC_SC->PLL0FEED = 0x55; 00538 00539 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ 00540 LPC_SC->PLL0FEED = 0xAA; 00541 LPC_SC->PLL0FEED = 0x55; 00542 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ 00543 00544 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ 00545 LPC_SC->PLL0FEED = 0xAA; 00546 LPC_SC->PLL0FEED = 0x55; 00547 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ 00548 #endif 00549 00550 #if (PLL1_SETUP) 00551 LPC_SC->PLL1CFG = PLL1CFG_Val; 00552 LPC_SC->PLL1FEED = 0xAA; 00553 LPC_SC->PLL1FEED = 0x55; 00554 00555 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ 00556 LPC_SC->PLL1FEED = 0xAA; 00557 LPC_SC->PLL1FEED = 0x55; 00558 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ 00559 00560 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ 00561 LPC_SC->PLL1FEED = 0xAA; 00562 LPC_SC->PLL1FEED = 0x55; 00563 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ 00564 #else 00565 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ 00566 #endif 00567 00568 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ 00569 00570 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ 00571 #endif 00572 00573 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ 00574 LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; 00575 #endif 00576 } 00577 00578 /** 00579 * @} 00580 */ 00581 00582 /** 00583 * @} 00584 */
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