fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088
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core_arm7.h
00001 /* mbed Microcontroller Library 00002 * Copyright (C) 2008-2009 ARM Limited. All rights reserved. 00003 * 00004 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! 00005 * based on core_cm3.h, V1.20 00006 */ 00007 00008 #ifndef __ARM7_CORE_H__ 00009 #define __ARM7_CORE_H__ 00010 00011 #ifdef __cplusplus 00012 extern "C" { 00013 #endif 00014 00015 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ 00016 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ 00017 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 00018 00019 #define __CORTEX_M (0x03) /*!< Cortex core */ 00020 00021 /** 00022 * Lint configuration \n 00023 * ----------------------- \n 00024 * 00025 * The following Lint messages will be suppressed and not shown: \n 00026 * \n 00027 * --- Error 10: --- \n 00028 * register uint32_t __regBasePri __asm("basepri"); \n 00029 * Error 10: Expecting ';' \n 00030 * \n 00031 * --- Error 530: --- \n 00032 * return(__regBasePri); \n 00033 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n 00034 * \n 00035 * --- Error 550: --- \n 00036 * __regBasePri = (basePri & 0x1ff); \n 00037 * } \n 00038 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n 00039 * \n 00040 * --- Error 754: --- \n 00041 * uint32_t RESERVED0[24]; \n 00042 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n 00043 * \n 00044 * --- Error 750: --- \n 00045 * #define __CM3_CORE_H__ \n 00046 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n 00047 * \n 00048 * --- Error 528: --- \n 00049 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n 00050 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n 00051 * \n 00052 * --- Error 751: --- \n 00053 * } InterruptType_Type; \n 00054 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n 00055 * \n 00056 * \n 00057 * Note: To re-enable a Message, insert a space before 'lint' * \n 00058 * 00059 */ 00060 00061 /*lint -save */ 00062 /*lint -e10 */ 00063 /*lint -e530 */ 00064 /*lint -e550 */ 00065 /*lint -e754 */ 00066 /*lint -e750 */ 00067 /*lint -e528 */ 00068 /*lint -e751 */ 00069 00070 #include <stdint.h> /* Include standard types */ 00071 00072 #if defined ( __CC_ARM ) 00073 /** 00074 * @brief Return the Main Stack Pointer (current ARM7 stack) 00075 * 00076 * @param none 00077 * @return uint32_t Main Stack Pointer 00078 * 00079 * Return the current value of the MSP (main stack pointer) 00080 * Cortex processor register 00081 */ 00082 extern uint32_t __get_MSP(void); 00083 #endif 00084 00085 00086 #if defined (__ICCARM__) 00087 #include <intrinsics.h> /* IAR Intrinsics */ 00088 #endif 00089 00090 00091 #ifndef __NVIC_PRIO_BITS 00092 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ 00093 #endif 00094 00095 typedef struct 00096 { 00097 uint32_t IRQStatus; 00098 uint32_t FIQStatus; 00099 uint32_t RawIntr; 00100 uint32_t IntSelect; 00101 uint32_t IntEnable; 00102 uint32_t IntEnClr; 00103 uint32_t SoftInt; 00104 uint32_t SoftIntClr; 00105 uint32_t Protection; 00106 uint32_t SWPriorityMask; 00107 uint32_t RESERVED0[54]; 00108 uint32_t VectAddr[32]; 00109 uint32_t RESERVED1[32]; 00110 uint32_t VectPriority[32]; 00111 uint32_t RESERVED2[800]; 00112 uint32_t Address; 00113 } NVIC_TypeDef; 00114 00115 #define NVIC_BASE (0xFFFFF000) 00116 #define NVIC (( NVIC_TypeDef *) NVIC_BASE) 00117 00118 00119 00120 /** 00121 * IO definitions 00122 * 00123 * define access restrictions to peripheral registers 00124 */ 00125 00126 #ifdef __cplusplus 00127 #define __I volatile /*!< defines 'read only' permissions */ 00128 #else 00129 #define __I volatile const /*!< defines 'read only' permissions */ 00130 #endif 00131 #define __O volatile /*!< defines 'write only' permissions */ 00132 #define __IO volatile /*!< defines 'read / write' permissions */ 00133 00134 00135 00136 00137 00138 #if defined ( __CC_ARM ) 00139 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00140 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00141 00142 #elif defined ( __ICCARM__ ) 00143 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00144 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ 00145 00146 #elif defined ( __GNUC__ ) 00147 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00148 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00149 00150 #elif defined ( __TASKING__ ) 00151 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00152 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00153 00154 #endif 00155 00156 00157 /* ################### Compiler specific Intrinsics ########################### */ 00158 00159 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 00160 /* ARM armcc specific functions */ 00161 00162 #define __enable_fault_irq __enable_fiq 00163 #define __disable_fault_irq __disable_fiq 00164 00165 #define __NOP __nop 00166 //#define __WFI __wfi 00167 //#define __WFE __wfe 00168 //#define __SEV __sev 00169 //#define __ISB() __isb(0) 00170 //#define __DSB() __dsb(0) 00171 //#define __DMB() __dmb(0) 00172 //#define __REV __rev 00173 //#define __RBIT __rbit 00174 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) 00175 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) 00176 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) 00177 #define __STREXB(value, ptr) __strex(value, ptr) 00178 #define __STREXH(value, ptr) __strex(value, ptr) 00179 #define __STREXW(value, ptr) __strex(value, ptr) 00180 00181 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \ 00182 LPC_VIC->IntEnClr = 0xffffffff 00183 00184 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable 00185 00186 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ 00187 00188 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ 00189 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ 00190 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ 00191 00192 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ 00193 00194 static __INLINE void __enable_irq() { 00195 unsigned long temp; 00196 __asm__ __volatile__("mrs %0, cpsr\n" 00197 "bic %0, %0, #0x80\n" 00198 "msr cpsr_c, %0" 00199 : "=r" (temp) 00200 : 00201 : "memory"); 00202 } 00203 00204 static __INLINE void __disable_irq() { 00205 unsigned long old,temp; 00206 __asm__ __volatile__("mrs %0, cpsr\n" 00207 "orr %1, %0, #0xc0\n" 00208 "msr cpsr_c, %1" 00209 : "=r" (old), "=r" (temp) 00210 : 00211 : "memory"); 00212 // return (old & 0x80) == 0; 00213 } 00214 00215 static __INLINE void __NOP() { __ASM volatile ("nop"); } 00216 00217 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ 00218 /* TASKING carm specific functions */ 00219 00220 /* 00221 * The CMSIS functions have been implemented as intrinsics in the compiler. 00222 * Please use "carm -?i" to get an up to date list of all instrinsics, 00223 * Including the CMSIS ones. 00224 */ 00225 00226 #endif 00227 00228 00229 /** 00230 * @brief Enable Interrupt in NVIC Interrupt Controller 00231 * 00232 * @param IRQn_Type IRQn specifies the interrupt number 00233 * @return none 00234 * 00235 * Enable a device specific interupt in the NVIC interrupt controller. 00236 * The interrupt number cannot be a negative value. 00237 */ 00238 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00239 { 00240 NVIC->IntEnable = 1 << (uint32_t)IRQn; 00241 } 00242 00243 00244 /** 00245 * @brief Disable the interrupt line for external interrupt specified 00246 * 00247 * @param IRQn_Type IRQn is the positive number of the external interrupt 00248 * @return none 00249 * 00250 * Disable a device specific interupt in the NVIC interrupt controller. 00251 * The interrupt number cannot be a negative value. 00252 */ 00253 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00254 { 00255 NVIC->IntEnClr = 1 << (uint32_t)IRQn; 00256 } 00257 00258 00259 #ifdef __cplusplus 00260 } 00261 #endif 00262 00263 #endif /* __ARM7_CORE_H__ */ 00264 00265 /*lint -restore */
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