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LPC8xx.h
00001 /**************************************************************************** 00002 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $ 00003 * Project: NXP LPC8xx software example 00004 * 00005 * Description: 00006 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for 00007 * NXP LPC800 Device Series 00008 * 00009 **************************************************************************** 00010 * Software that is described herein is for illustrative purposes only 00011 * which provides customers with programming information regarding the 00012 * products. This software is supplied "AS IS" without any warranties. 00013 * NXP Semiconductors assumes no responsibility or liability for the 00014 * use of the software, conveys no license or title under any patent, 00015 * copyright, or mask work right to the product. NXP Semiconductors 00016 * reserves the right to make changes in the software without 00017 * notification. NXP Semiconductors also make no representation or 00018 * warranty that such application will be suitable for the specified 00019 * use without further testing or modification. 00020 00021 * Permission to use, copy, modify, and distribute this software and its 00022 * documentation is hereby granted, under NXP Semiconductors' 00023 * relevant copyright in the software, without fee, provided that it 00024 * is used in conjunction with NXP Semiconductors microcontrollers. This 00025 * copyright, permission, and disclaimer notice must appear in all copies of 00026 * this code. 00027 ****************************************************************************/ 00028 #ifndef __LPC8xx_H__ 00029 #define __LPC8xx_H__ 00030 00031 #ifdef __cplusplus 00032 extern "C" { 00033 #endif 00034 00035 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions 00036 This file defines all structures and symbols for LPC8xx: 00037 - Registers and bitfields 00038 - peripheral base address 00039 - PIO definitions 00040 @{ 00041 */ 00042 00043 00044 /******************************************************************************/ 00045 /* Processor and Core Peripherals */ 00046 /******************************************************************************/ 00047 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions 00048 Configuration of the Cortex-M0+ Processor and Core Peripherals 00049 @{ 00050 */ 00051 00052 /* 00053 * ========================================================================== 00054 * ---------- Interrupt Number Definition ----------------------------------- 00055 * ========================================================================== 00056 */ 00057 typedef enum IRQn 00058 { 00059 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ 00060 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/ 00061 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00062 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ 00063 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ 00064 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ 00065 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ 00066 00067 /****** LPC8xx Specific Interrupt Numbers ********************************************************/ 00068 SPI0_IRQn = 0, /*!< SPI0 */ 00069 SPI1_IRQn = 1, /*!< SPI1 */ 00070 Reserved0_IRQn = 2, /*!< Reserved Interrupt */ 00071 UART0_IRQn = 3, /*!< USART0 */ 00072 UART1_IRQn = 4, /*!< USART1 */ 00073 UART2_IRQn = 5, /*!< USART2 */ 00074 Reserved1_IRQn = 6, /*!< Reserved Interrupt */ 00075 Reserved2_IRQn = 7, /*!< Reserved Interrupt */ 00076 I2C_IRQn = 8, /*!< I2C */ 00077 SCT_IRQn = 9, /*!< SCT */ 00078 MRT_IRQn = 10, /*!< MRT */ 00079 CMP_IRQn = 11, /*!< CMP */ 00080 WDT_IRQn = 12, /*!< WDT */ 00081 BOD_IRQn = 13, /*!< BOD */ 00082 Reserved3_IRQn = 14, /*!< Reserved Interrupt */ 00083 WKT_IRQn = 15, /*!< WKT Interrupt */ 00084 Reserved4_IRQn = 16, /*!< Reserved Interrupt */ 00085 Reserved5_IRQn = 17, /*!< Reserved Interrupt */ 00086 Reserved6_IRQn = 18, /*!< Reserved Interrupt */ 00087 Reserved7_IRQn = 19, /*!< Reserved Interrupt */ 00088 Reserved8_IRQn = 20, /*!< Reserved Interrupt */ 00089 Reserved9_IRQn = 21, /*!< Reserved Interrupt */ 00090 Reserved10_IRQn = 22, /*!< Reserved Interrupt */ 00091 Reserved11_IRQn = 23, /*!< Reserved Interrupt */ 00092 PININT0_IRQn = 24, /*!< External Interrupt 0 */ 00093 PININT1_IRQn = 25, /*!< External Interrupt 1 */ 00094 PININT2_IRQn = 26, /*!< External Interrupt 2 */ 00095 PININT3_IRQn = 27, /*!< External Interrupt 3 */ 00096 PININT4_IRQn = 28, /*!< External Interrupt 4 */ 00097 PININT5_IRQn = 29, /*!< External Interrupt 5 */ 00098 PININT6_IRQn = 30, /*!< External Interrupt 6 */ 00099 PININT7_IRQn = 31, /*!< External Interrupt 7 */ 00100 } IRQn_Type ; 00101 00102 /* 00103 * ========================================================================== 00104 * ----------- Processor and Core Peripheral Section ------------------------ 00105 * ========================================================================== 00106 */ 00107 00108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */ 00109 #define __MPU_PRESENT 0 /*!< MPU present or not */ 00110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */ 00111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 00112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00113 00114 /*@}*/ /* end of group LPC8xx_CMSIS */ 00115 00116 00117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ 00118 #include "system_LPC8xx.h" /* System Header */ 00119 00120 00121 /******************************************************************************/ 00122 /* Device Specific Peripheral Registers structures */ 00123 /******************************************************************************/ 00124 00125 #if defined ( __CC_ARM ) 00126 #pragma anon_unions 00127 #endif 00128 00129 /*------------- System Control (SYSCON) --------------------------------------*/ 00130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block 00131 @{ 00132 */ 00133 typedef struct 00134 { 00135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ 00136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ 00137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ 00138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ 00139 uint32_t RESERVED0[4]; 00140 00141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ 00142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ 00143 uint32_t RESERVED1[2]; 00144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */ 00145 uint32_t RESERVED2[3]; 00146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ 00147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ 00148 uint32_t RESERVED3[10]; 00149 00150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ 00151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ 00152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ 00153 uint32_t RESERVED4[1]; 00154 00155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ 00156 uint32_t RESERVED5[4]; 00157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */ 00158 uint32_t RESERVED6[18]; 00159 00160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ 00161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ 00162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ 00163 uint32_t RESERVED7; 00164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ 00165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */ 00166 uint32_t RESERVED8[1]; 00167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ 00168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ 00169 uint32_t RESERVED9[12]; 00170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */ 00171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ 00172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ 00173 uint32_t RESERVED10[6]; 00174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */ 00175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ 00176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ 00177 uint32_t RESERVED11[27]; 00178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ 00179 uint32_t RESERVED12[3]; 00180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */ 00181 uint32_t RESERVED13[6]; 00182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ 00183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ 00184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ 00185 uint32_t RESERVED14[110]; 00186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ 00187 } LPC_SYSCON_TypeDef; 00188 /*@}*/ /* end of group LPC8xx_SYSCON */ 00189 00190 00191 /** 00192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) 00193 */ 00194 00195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ 00196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ 00197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ 00198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ 00199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */ 00200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ 00201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */ 00202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */ 00203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */ 00204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */ 00205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ 00206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ 00207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */ 00208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */ 00209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */ 00210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */ 00211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ 00212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */ 00213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */ 00214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ 00215 } LPC_IOCON_TypeDef; 00216 /*@}*/ /* end of group LPC8xx_IOCON */ 00217 00218 /** 00219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL) 00220 */ 00221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ 00222 __I uint32_t RESERVED0[4]; 00223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ 00224 __I uint32_t RESERVED1[3]; 00225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ 00226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ 00227 __I uint32_t RESERVED2; 00228 __I uint32_t FMSW0; 00229 } LPC_FLASHCTRL_TypeDef; 00230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */ 00231 00232 00233 /*------------- Power Management Unit (PMU) --------------------------*/ 00234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit 00235 @{ 00236 */ 00237 typedef struct 00238 { 00239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ 00240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ 00241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ 00242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ 00243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ 00244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */ 00245 } LPC_PMU_TypeDef; 00246 /*@}*/ /* end of group LPC8xx_PMU */ 00247 00248 00249 /*------------- Switch Matrix Port --------------------------*/ 00250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port 00251 @{ 00252 */ 00253 typedef struct 00254 { 00255 union { 00256 __IO uint32_t PINASSIGN[9]; 00257 struct { 00258 __IO uint32_t PINASSIGN0; 00259 __IO uint32_t PINASSIGN1; 00260 __IO uint32_t PINASSIGN2; 00261 __IO uint32_t PINASSIGN3; 00262 __IO uint32_t PINASSIGN4; 00263 __IO uint32_t PINASSIGN5; 00264 __IO uint32_t PINASSIGN6; 00265 __IO uint32_t PINASSIGN7; 00266 __IO uint32_t PINASSIGN8; 00267 }; 00268 }; 00269 __I uint32_t RESERVED0[103]; 00270 __IO uint32_t PINENABLE0; 00271 } LPC_SWM_TypeDef; 00272 /*@}*/ /* end of group LPC8xx_SWM */ 00273 00274 00275 // ------------------------------------------------------------------------------------------------ 00276 // ----- GPIO_PORT ----- 00277 // ------------------------------------------------------------------------------------------------ 00278 00279 /** 00280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) 00281 */ 00282 00283 typedef struct { 00284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */ 00285 __I uint16_t RESERVED0[2039]; 00286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */ 00287 uint32_t RESERVED1[1006]; 00288 __IO uint32_t DIR0; /* 0x2000 */ 00289 uint32_t RESERVED2[31]; 00290 __IO uint32_t MASK0; /* 0x2080 */ 00291 uint32_t RESERVED3[31]; 00292 __IO uint32_t PIN0; /* 0x2100 */ 00293 uint32_t RESERVED4[31]; 00294 __IO uint32_t MPIN0; /* 0x2180 */ 00295 uint32_t RESERVED5[31]; 00296 __IO uint32_t SET0; /* 0x2200 */ 00297 uint32_t RESERVED6[31]; 00298 __O uint32_t CLR0; /* 0x2280 */ 00299 uint32_t RESERVED7[31]; 00300 __O uint32_t NOT0; /* 0x2300 */ 00301 00302 } LPC_GPIO_PORT_TypeDef; 00303 00304 00305 // ------------------------------------------------------------------------------------------------ 00306 // ----- PIN_INT ----- 00307 // ------------------------------------------------------------------------------------------------ 00308 00309 /** 00310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT) 00311 */ 00312 00313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ 00314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ 00315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */ 00316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */ 00317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */ 00318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */ 00319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */ 00320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ 00321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */ 00322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */ 00323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */ 00324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ 00325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */ 00326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */ 00327 } LPC_PIN_INT_TypeDef; 00328 00329 00330 /*------------- CRC Engine (CRC) -----------------------------------------*/ 00331 /** @addtogroup LPC8xx_CRC 00332 @{ 00333 */ 00334 typedef struct 00335 { 00336 __IO uint32_t MODE; 00337 __IO uint32_t SEED; 00338 union { 00339 __I uint32_t SUM; 00340 __O uint32_t WR_DATA_DWORD; 00341 __O uint16_t WR_DATA_WORD; 00342 uint16_t RESERVED_WORD; 00343 __O uint8_t WR_DATA_BYTE; 00344 uint8_t RESERVED_BYTE[3]; 00345 }; 00346 } LPC_CRC_TypeDef; 00347 /*@}*/ /* end of group LPC8xx_CRC */ 00348 00349 /*------------- Comparator (CMP) --------------------------------------------------*/ 00350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator 00351 @{ 00352 */ 00353 typedef struct { /*!< (@ 0x40024000) CMP Structure */ 00354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ 00355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ 00356 } LPC_CMP_TypeDef; 00357 /*@}*/ /* end of group LPC8xx_CMP */ 00358 00359 00360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/ 00361 /** @addtogroup LPC8xx_WKT 00362 @{ 00363 */ 00364 typedef struct { /*!< (@ 0x40028000) WKT Structure */ 00365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */ 00366 uint32_t Reserved[2]; 00367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */ 00368 } LPC_WKT_TypeDef; 00369 /*@}*/ /* end of group LPC8xx_WKT */ 00370 00371 00372 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ 00373 typedef struct { 00374 __IO uint32_t INTVAL; 00375 __IO uint32_t TIMER; 00376 __IO uint32_t CTRL; 00377 __IO uint32_t STAT; 00378 } MRT_Channel_cfg_Type; 00379 00380 typedef struct { 00381 MRT_Channel_cfg_Type Channel[4]; 00382 uint32_t Reserved0[1]; 00383 __IO uint32_t IDLE_CH; 00384 __IO uint32_t IRQ_FLAG; 00385 } LPC_MRT_TypeDef; 00386 00387 00388 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ 00389 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter 00390 @{ 00391 */ 00392 /** 00393 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART) 00394 */ 00395 typedef struct 00396 { 00397 __IO uint32_t CFG; /* 0x00 */ 00398 __IO uint32_t CTRL; 00399 __IO uint32_t STAT; 00400 __IO uint32_t INTENSET; 00401 __O uint32_t INTENCLR; /* 0x10 */ 00402 __I uint32_t RXDATA; 00403 __I uint32_t RXDATA_STAT; 00404 __IO uint32_t TXDATA; 00405 __IO uint32_t BRG; /* 0x20 */ 00406 __IO uint32_t INTSTAT; 00407 } LPC_USART_TypeDef; 00408 00409 /*@}*/ /* end of group LPC8xx_USART */ 00410 00411 00412 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/ 00413 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port 00414 @{ 00415 */ 00416 typedef struct 00417 { 00418 __IO uint32_t CFG; /* 0x00 */ 00419 __IO uint32_t DLY; 00420 __IO uint32_t STAT; 00421 __IO uint32_t INTENSET; 00422 __O uint32_t INTENCLR; /* 0x10 */ 00423 __I uint32_t RXDAT; 00424 __IO uint32_t TXDATCTL; 00425 __IO uint32_t TXDAT; 00426 __IO uint32_t TXCTRL; /* 0x20 */ 00427 __IO uint32_t DIV; 00428 __I uint32_t INTSTAT; 00429 } LPC_SPI_TypeDef; 00430 /*@}*/ /* end of group LPC8xx_SPI */ 00431 00432 00433 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00434 /** @addtogroup LPC8xx_I2C I2C-Bus Interface 00435 @{ 00436 */ 00437 typedef struct 00438 { 00439 __IO uint32_t CFG; /* 0x00 */ 00440 __IO uint32_t STAT; 00441 __IO uint32_t INTENSET; 00442 __O uint32_t INTENCLR; 00443 __IO uint32_t TIMEOUT; /* 0x10 */ 00444 __IO uint32_t DIV; 00445 __IO uint32_t INTSTAT; 00446 uint32_t Reserved0[1]; 00447 __IO uint32_t MSTCTL; /* 0x20 */ 00448 __IO uint32_t MSTTIME; 00449 __IO uint32_t MSTDAT; 00450 uint32_t Reserved1[5]; 00451 __IO uint32_t SLVCTL; /* 0x40 */ 00452 __IO uint32_t SLVDAT; 00453 __IO uint32_t SLVADR0; 00454 __IO uint32_t SLVADR1; 00455 __IO uint32_t SLVADR2; /* 0x50 */ 00456 __IO uint32_t SLVADR3; 00457 __IO uint32_t SLVQUAL0; 00458 uint32_t Reserved2[9]; 00459 __I uint32_t MONRXDAT; /* 0x80 */ 00460 } LPC_I2C_TypeDef; 00461 00462 /*@}*/ /* end of group LPC8xx_I2C */ 00463 00464 /** 00465 * @brief State Configurable Timer (SCT) (SCT) 00466 */ 00467 00468 /** 00469 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) 00470 */ 00471 00472 #define CONFIG_SCT_nEV (6) /* Number of events */ 00473 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */ 00474 #define CONFIG_SCT_nOU (4) /* Number of outputs */ 00475 00476 typedef struct 00477 { 00478 __IO uint32_t CONFIG; /* 0x000 Configuration Register */ 00479 union { 00480 __IO uint32_t CTRL_U; /* 0x004 Control Register */ 00481 struct { 00482 __IO uint16_t CTRL_L; /* 0x004 low control register */ 00483 __IO uint16_t CTRL_H; /* 0x006 high control register */ 00484 }; 00485 }; 00486 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ 00487 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ 00488 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ 00489 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ 00490 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ 00491 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ 00492 __IO uint16_t START_L; /* 0x014 start register for counter L */ 00493 __IO uint16_t START_H; /* 0x016 start register for counter H */ 00494 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ 00495 union { 00496 __IO uint32_t COUNT_U; /* 0x040 counter register */ 00497 struct { 00498 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ 00499 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ 00500 }; 00501 }; 00502 __IO uint16_t STATE_L; /* 0x044 state register for counter L */ 00503 __IO uint16_t STATE_H; /* 0x046 state register for counter H */ 00504 __I uint32_t INPUT; /* 0x048 input register */ 00505 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ 00506 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ 00507 __IO uint32_t OUTPUT; /* 0x050 output register */ 00508 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ 00509 __IO uint32_t RES; /* 0x058 conflict resolution register */ 00510 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */ 00511 __IO uint32_t EVEN; /* 0x0F0 event enable register */ 00512 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ 00513 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ 00514 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ 00515 00516 union { 00517 __IO union { /* 0x100-... Match / Capture value */ 00518 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ 00519 struct { 00520 uint16_t L; /* SCTMATCH[i].L Access to L value */ 00521 uint16_t H; /* SCTMATCH[i].H Access to H value */ 00522 }; 00523 } MATCH[CONFIG_SCT_nRG]; 00524 __I union { 00525 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ 00526 struct { 00527 uint16_t L; /* SCTCAP[i].L Access to H value */ 00528 uint16_t H; /* SCTCAP[i].H Access to H value */ 00529 }; 00530 } CAP[CONFIG_SCT_nRG]; 00531 }; 00532 00533 00534 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ 00535 00536 union { 00537 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ 00538 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ 00539 }; 00540 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ 00541 union { 00542 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ 00543 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ 00544 }; 00545 00546 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ 00547 00548 00549 union { 00550 __IO union { /* 0x200-... Match Reload / Capture Control value */ 00551 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ 00552 struct { 00553 uint16_t L; /* SCTMATCHREL[i].L Access to L value */ 00554 uint16_t H; /* SCTMATCHREL[i].H Access to H value */ 00555 }; 00556 } MATCHREL[CONFIG_SCT_nRG]; 00557 __IO union { 00558 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ 00559 struct { 00560 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ 00561 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ 00562 }; 00563 } CAPCTRL[CONFIG_SCT_nRG]; 00564 }; 00565 00566 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ 00567 00568 union { 00569 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ 00570 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ 00571 }; 00572 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ 00573 union { 00574 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ 00575 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ 00576 }; 00577 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ 00578 00579 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ 00580 uint32_t STATE; /* Event State Register */ 00581 uint32_t CTRL; /* Event Control Register */ 00582 } EVENT[CONFIG_SCT_nEV]; 00583 00584 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ 00585 00586 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ 00587 uint32_t SET; /* Output n Set Register */ 00588 uint32_t CLR; /* Output n Clear Register */ 00589 } OUT[CONFIG_SCT_nOU]; 00590 00591 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ 00592 00593 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ 00594 00595 } LPC_SCT_TypeDef; 00596 /*@}*/ /* end of group LPC8xx_SCT */ 00597 00598 00599 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/ 00600 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer 00601 @{ 00602 */ 00603 typedef struct 00604 { 00605 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ 00606 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ 00607 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ 00608 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ 00609 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */ 00610 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ 00611 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ 00612 } LPC_WWDT_TypeDef; 00613 /*@}*/ /* end of group LPC8xx_WDT */ 00614 00615 00616 #if defined ( __CC_ARM ) 00617 #pragma no_anon_unions 00618 #endif 00619 00620 /******************************************************************************/ 00621 /* Peripheral memory map */ 00622 /******************************************************************************/ 00623 /* Base addresses */ 00624 #define LPC_FLASH_BASE (0x00000000UL) 00625 #define LPC_RAM_BASE (0x10000000UL) 00626 #define LPC_ROM_BASE (0x1FFF0000UL) 00627 #define LPC_APB0_BASE (0x40000000UL) 00628 #define LPC_AHB_BASE (0x50000000UL) 00629 00630 /* APB0 peripherals */ 00631 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000) 00632 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000) 00633 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000) 00634 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000) 00635 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000) 00636 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000) 00637 00638 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000) 00639 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) 00640 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) 00641 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000) 00642 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000) 00643 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000) 00644 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000) 00645 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000) 00646 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000) 00647 00648 /* AHB peripherals */ 00649 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000) 00650 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000) 00651 00652 #define LPC_GPIO_PORT_BASE (0xA0000000) 00653 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000) 00654 00655 /******************************************************************************/ 00656 /* Peripheral declaration */ 00657 /******************************************************************************/ 00658 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE ) 00659 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE ) 00660 00661 00662 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE ) 00663 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE ) 00664 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) 00665 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE ) 00666 00667 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE ) 00668 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) 00669 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) 00670 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) 00671 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE ) 00672 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE ) 00673 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE ) 00674 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE ) 00675 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE ) 00676 00677 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) 00678 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE ) 00679 00680 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE ) 00681 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE ) 00682 00683 #ifdef __cplusplus 00684 } 00685 #endif 00686 00687 #endif /* __LPC8xx_H__ */
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