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fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088
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LPC407x_8x_177x_8x.h
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00001 /****************************************************************************************************//** 00002 * $Id$ LPC407x_8x_177x_8x.h 2012-04-25 00003 *//** 00004 * @file LPC407x_8x_177x_8x.h 00005 * 00006 * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for 00007 * NXP LPC407x_8x_177x_8x. 00008 * @version V0.7 00009 * @date 20. June 2012 00010 * @author NXP MCU SW Application Team 00011 * 00012 * Copyright(C) 2012, NXP Semiconductor 00013 * All rights reserved. 00014 * 00015 *********************************************************************** 00016 * Software that is described herein is for illustrative purposes only 00017 * which provides customers with programming information regarding the 00018 * products. This software is supplied "AS IS" without any warranties. 00019 * NXP Semiconductors assumes no responsibility or liability for the 00020 * use of the software, conveys no license or title under any patent, 00021 * copyright, or mask work right to the product. NXP Semiconductors 00022 * reserves the right to make changes in the software without 00023 * notification. NXP Semiconductors also make no representation or 00024 * warranty that such application will be suitable for the specified 00025 * use without further testing or modification. 00026 * Permission to use, copy, modify, and distribute this software and its 00027 * documentation is hereby granted, under NXP Semiconductors' 00028 * relevant copyright in the software, without fee, provided that it 00029 * is used in conjunction with NXP Semiconductors microcontrollers. This 00030 * copyright, permission, and disclaimer notice must appear in all copies of 00031 * this code. 00032 **********************************************************************/ 00033 00034 #ifndef __LPC407x_8x_177x_8x_H__ 00035 #define __LPC407x_8x_177x_8x_H__ 00036 00037 #define CORE_M4 00038 00039 // ################## 00040 // Code Red - excluded extern "C" as unrequired 00041 // ################## 00042 #if 0 00043 #ifdef __cplusplus 00044 extern "C" { 00045 #endif 00046 #endif 00047 00048 00049 /* ------------------------- Interrupt Number Definition ------------------------ */ 00050 00051 typedef enum IRQn 00052 { 00053 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ 00054 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ 00055 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00056 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 00057 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 00058 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 00059 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 00060 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 00061 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 00062 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 00063 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 00064 00065 /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/ 00066 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ 00067 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ 00068 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ 00069 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ 00070 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ 00071 UART0_IRQn = 5, /*!< UART0 Interrupt */ 00072 UART1_IRQn = 6, /*!< UART1 Interrupt */ 00073 UART2_IRQn = 7, /*!< UART2 Interrupt */ 00074 UART3_IRQn = 8, /*!< UART3 Interrupt */ 00075 PWM1_IRQn = 9, /*!< PWM1 Interrupt */ 00076 I2C0_IRQn = 10, /*!< I2C0 Interrupt */ 00077 I2C1_IRQn = 11, /*!< I2C1 Interrupt */ 00078 I2C2_IRQn = 12, /*!< I2C2 Interrupt */ 00079 Reserved0_IRQn = 13, /*!< Reserved */ 00080 SSP0_IRQn = 14, /*!< SSP0 Interrupt */ 00081 SSP1_IRQn = 15, /*!< SSP1 Interrupt */ 00082 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ 00083 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ 00084 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ 00085 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ 00086 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ 00087 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ 00088 ADC_IRQn = 22, /*!< A/D Converter Interrupt */ 00089 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ 00090 USB_IRQn = 24, /*!< USB Interrupt */ 00091 CAN_IRQn = 25, /*!< CAN Interrupt */ 00092 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ 00093 I2S_IRQn = 27, /*!< I2S Interrupt */ 00094 ENET_IRQn = 28, /*!< Ethernet Interrupt */ 00095 MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */ 00096 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ 00097 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ 00098 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ 00099 USBActivity_IRQn = 33, /*!< USB Activity interrupt */ 00100 CANActivity_IRQn = 34, /*!< CAN Activity interrupt */ 00101 UART4_IRQn = 35, /*!< UART4 Interrupt */ 00102 SSP2_IRQn = 36, /*!< SSP2 Interrupt */ 00103 LCD_IRQn = 37, /*!< LCD Interrupt */ 00104 GPIO_IRQn = 38, /*!< GPIO Interrupt */ 00105 PWM0_IRQn = 39, /*!< 39 PWM0 */ 00106 EEPROM_IRQn = 40, /*!< 40 EEPROM */ 00107 CMP0_IRQn = 41, /*!< 41 CMP0 */ 00108 CMP1_IRQn = 42 /*!< 42 CMP1 */ 00109 } IRQn_Type ; 00110 00111 /* ================================================================================ */ 00112 /* ================ Processor and Core Peripheral Section ================ */ 00113 /* ================================================================================ */ 00114 #ifdef CORE_M4 00115 /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */ 00116 #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ 00117 #define __MPU_PRESENT 1 /*!< MPU present or not */ 00118 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ 00119 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00120 #define __FPU_PRESENT 1 /*!< FPU present or not */ 00121 00122 00123 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ 00124 #else 00125 /* Configuration of the Cortex-M3 Processor and Core Peripherals */ 00126 #define __MPU_PRESENT 1 /*!< MPU present or not */ 00127 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ 00128 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00129 00130 00131 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ 00132 00133 #endif 00134 00135 #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */ 00136 00137 00138 00139 00140 00141 00142 /* ================================================================================ */ 00143 /* ================ Device Specific Peripheral Section ================ */ 00144 /* ================================================================================ */ 00145 00146 #if defined ( __CC_ARM ) 00147 #pragma anon_unions 00148 #endif 00149 00150 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ 00151 typedef struct /* Common Registers */ 00152 { 00153 __I uint32_t IntStat; 00154 __I uint32_t IntTCStat; 00155 __O uint32_t IntTCClear; 00156 __I uint32_t IntErrStat; 00157 __O uint32_t IntErrClr; 00158 __I uint32_t RawIntTCStat; 00159 __I uint32_t RawIntErrStat; 00160 __I uint32_t EnbldChns; 00161 __IO uint32_t SoftBReq; 00162 __IO uint32_t SoftSReq; 00163 __IO uint32_t SoftLBReq; 00164 __IO uint32_t SoftLSReq; 00165 __IO uint32_t Config; 00166 __IO uint32_t Sync; 00167 } LPC_GPDMA_TypeDef; 00168 00169 typedef struct /* Channel Registers */ 00170 { 00171 __IO uint32_t CSrcAddr; 00172 __IO uint32_t CDestAddr; 00173 __IO uint32_t CLLI; 00174 __IO uint32_t CControl; 00175 __IO uint32_t CConfig; 00176 } LPC_GPDMACH_TypeDef; 00177 00178 /*------------- System Control (SC) ------------------------------------------*/ 00179 typedef struct 00180 { 00181 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ 00182 uint32_t RESERVED0[31]; 00183 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ 00184 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ 00185 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ 00186 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ 00187 uint32_t RESERVED1[4]; 00188 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ 00189 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ 00190 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ 00191 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ 00192 uint32_t RESERVED2[4]; 00193 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ 00194 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ 00195 __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */ 00196 uint32_t RESERVED3[13]; 00197 __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */ 00198 __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */ 00199 __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */ 00200 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ 00201 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ 00202 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ 00203 uint32_t RESERVED4[10]; 00204 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ 00205 uint32_t RESERVED5[1]; 00206 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ 00207 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ 00208 uint32_t RESERVED6[12]; 00209 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ 00210 uint32_t RESERVED7[7]; 00211 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ 00212 __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */ 00213 __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */ 00214 uint32_t RESERVED8; 00215 __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */ 00216 __IO uint32_t SPIFICLKSEL; 00217 __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */ 00218 uint32_t RESERVED10[1]; 00219 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ 00220 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ 00221 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ 00222 __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */ 00223 __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */ 00224 uint32_t RESERVED11[2]; 00225 __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */ 00226 __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */ 00227 } LPC_SC_TypeDef; 00228 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ 00229 typedef struct 00230 { 00231 __IO uint32_t MAC1; /* MAC Registers */ 00232 __IO uint32_t MAC2; 00233 __IO uint32_t IPGT; 00234 __IO uint32_t IPGR; 00235 __IO uint32_t CLRT; 00236 __IO uint32_t MAXF; 00237 __IO uint32_t SUPP; 00238 __IO uint32_t TEST; 00239 __IO uint32_t MCFG; 00240 __IO uint32_t MCMD; 00241 __IO uint32_t MADR; 00242 __O uint32_t MWTD; 00243 __I uint32_t MRDD; 00244 __I uint32_t MIND; 00245 uint32_t RESERVED0[2]; 00246 __IO uint32_t SA0; 00247 __IO uint32_t SA1; 00248 __IO uint32_t SA2; 00249 uint32_t RESERVED1[45]; 00250 __IO uint32_t Command; /* Control Registers */ 00251 __I uint32_t Status; 00252 __IO uint32_t RxDescriptor; 00253 __IO uint32_t RxStatus; 00254 __IO uint32_t RxDescriptorNumber; 00255 __I uint32_t RxProduceIndex; 00256 __IO uint32_t RxConsumeIndex; 00257 __IO uint32_t TxDescriptor; 00258 __IO uint32_t TxStatus; 00259 __IO uint32_t TxDescriptorNumber; 00260 __IO uint32_t TxProduceIndex; 00261 __I uint32_t TxConsumeIndex; 00262 uint32_t RESERVED2[10]; 00263 __I uint32_t TSV0; 00264 __I uint32_t TSV1; 00265 __I uint32_t RSV; 00266 uint32_t RESERVED3[3]; 00267 __IO uint32_t FlowControlCounter; 00268 __I uint32_t FlowControlStatus; 00269 uint32_t RESERVED4[34]; 00270 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ 00271 __I uint32_t RxFilterWoLStatus; 00272 __O uint32_t RxFilterWoLClear; 00273 uint32_t RESERVED5; 00274 __IO uint32_t HashFilterL; 00275 __IO uint32_t HashFilterH; 00276 uint32_t RESERVED6[882]; 00277 __I uint32_t IntStatus; /* Module Control Registers */ 00278 __IO uint32_t IntEnable; 00279 __O uint32_t IntClear; 00280 __O uint32_t IntSet; 00281 uint32_t RESERVED7; 00282 __IO uint32_t PowerDown; 00283 uint32_t RESERVED8; 00284 __IO uint32_t Module_ID; 00285 } LPC_EMAC_TypeDef; 00286 00287 /*------------- LCD controller (LCD) -----------------------------------------*/ 00288 typedef struct 00289 { 00290 __IO uint32_t TIMH; /* LCD Registers */ 00291 __IO uint32_t TIMV; 00292 __IO uint32_t POL; 00293 __IO uint32_t LE; 00294 __IO uint32_t UPBASE; 00295 __IO uint32_t LPBASE; 00296 __IO uint32_t CTRL; 00297 __IO uint32_t INTMSK; 00298 __I uint32_t INTRAW; 00299 __I uint32_t INTSTAT; 00300 __O uint32_t INTCLR; 00301 __I uint32_t UPCURR; 00302 __I uint32_t LPCURR; 00303 uint32_t RESERVED0[115]; 00304 __IO uint32_t PAL[128]; 00305 uint32_t RESERVED1[256]; 00306 __IO uint32_t CRSR_IMG[256]; 00307 __IO uint32_t CRSR_CTRL; 00308 __IO uint32_t CRSR_CFG; 00309 __IO uint32_t CRSR_PAL0; 00310 __IO uint32_t CRSR_PAL1; 00311 __IO uint32_t CRSR_XY; 00312 __IO uint32_t CRSR_CLIP; 00313 uint32_t RESERVED2[2]; 00314 __IO uint32_t CRSR_INTMSK; 00315 __O uint32_t CRSR_INTCLR; 00316 __I uint32_t CRSR_INTRAW; 00317 __I uint32_t CRSR_INTSTAT; 00318 } LPC_LCD_TypeDef; 00319 00320 /*------------- Universal Serial Bus (USB) -----------------------------------*/ 00321 typedef struct 00322 { 00323 __I uint32_t Revision; /* USB Host Registers */ 00324 __IO uint32_t Control; 00325 __IO uint32_t CommandStatus; 00326 __IO uint32_t InterruptStatus; 00327 __IO uint32_t InterruptEnable; 00328 __IO uint32_t InterruptDisable; 00329 __IO uint32_t HCCA; 00330 __I uint32_t PeriodCurrentED; 00331 __IO uint32_t ControlHeadED; 00332 __IO uint32_t ControlCurrentED; 00333 __IO uint32_t BulkHeadED; 00334 __IO uint32_t BulkCurrentED; 00335 __I uint32_t DoneHead; 00336 __IO uint32_t FmInterval; 00337 __I uint32_t FmRemaining; 00338 __I uint32_t FmNumber; 00339 __IO uint32_t PeriodicStart; 00340 __IO uint32_t LSTreshold; 00341 __IO uint32_t RhDescriptorA; 00342 __IO uint32_t RhDescriptorB; 00343 __IO uint32_t RhStatus; 00344 __IO uint32_t RhPortStatus1; 00345 __IO uint32_t RhPortStatus2; 00346 uint32_t RESERVED0[40]; 00347 __I uint32_t Module_ID; 00348 00349 __I uint32_t IntSt; /* USB On-The-Go Registers */ 00350 __IO uint32_t IntEn; 00351 __O uint32_t IntSet; 00352 __O uint32_t IntClr; 00353 __IO uint32_t StCtrl; 00354 __IO uint32_t Tmr; 00355 uint32_t RESERVED1[58]; 00356 00357 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ 00358 __IO uint32_t DevIntEn; 00359 __O uint32_t DevIntClr; 00360 __O uint32_t DevIntSet; 00361 00362 __O uint32_t CmdCode; /* USB Device SIE Command Registers */ 00363 __I uint32_t CmdData; 00364 00365 __I uint32_t RxData; /* USB Device Transfer Registers */ 00366 __O uint32_t TxData; 00367 __I uint32_t RxPLen; 00368 __O uint32_t TxPLen; 00369 __IO uint32_t Ctrl; 00370 __O uint32_t DevIntPri; 00371 00372 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ 00373 __IO uint32_t EpIntEn; 00374 __O uint32_t EpIntClr; 00375 __O uint32_t EpIntSet; 00376 __O uint32_t EpIntPri; 00377 00378 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ 00379 __O uint32_t EpInd; 00380 __IO uint32_t MaxPSize; 00381 00382 __I uint32_t DMARSt; /* USB Device DMA Registers */ 00383 __O uint32_t DMARClr; 00384 __O uint32_t DMARSet; 00385 uint32_t RESERVED2[9]; 00386 __IO uint32_t UDCAH; 00387 __I uint32_t EpDMASt; 00388 __O uint32_t EpDMAEn; 00389 __O uint32_t EpDMADis; 00390 __I uint32_t DMAIntSt; 00391 __IO uint32_t DMAIntEn; 00392 uint32_t RESERVED3[2]; 00393 __I uint32_t EoTIntSt; 00394 __O uint32_t EoTIntClr; 00395 __O uint32_t EoTIntSet; 00396 __I uint32_t NDDRIntSt; 00397 __O uint32_t NDDRIntClr; 00398 __O uint32_t NDDRIntSet; 00399 __I uint32_t SysErrIntSt; 00400 __O uint32_t SysErrIntClr; 00401 __O uint32_t SysErrIntSet; 00402 uint32_t RESERVED4[15]; 00403 00404 union { 00405 __I uint32_t I2C_RX; /* USB OTG I2C Registers */ 00406 __O uint32_t I2C_TX; 00407 }; 00408 __IO uint32_t I2C_STS; 00409 __IO uint32_t I2C_CTL; 00410 __IO uint32_t I2C_CLKHI; 00411 __O uint32_t I2C_CLKLO; 00412 uint32_t RESERVED5[824]; 00413 00414 union { 00415 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ 00416 __IO uint32_t OTGClkCtrl; 00417 }; 00418 union { 00419 __I uint32_t USBClkSt; 00420 __I uint32_t OTGClkSt; 00421 }; 00422 } LPC_USB_TypeDef; 00423 00424 /*------------- CRC Engine (CRC) -----------------------------------------*/ 00425 typedef struct 00426 { 00427 __IO uint32_t MODE; 00428 __IO uint32_t SEED; 00429 union { 00430 __I uint32_t SUM; 00431 struct { 00432 __O uint32_t DATA; 00433 } WR_DATA_DWORD; 00434 00435 struct { 00436 __O uint16_t DATA; 00437 uint16_t RESERVED; 00438 }WR_DATA_WORD; 00439 00440 struct { 00441 __O uint8_t DATA; 00442 uint8_t RESERVED[3]; 00443 }WR_DATA_BYTE; 00444 }; 00445 } LPC_CRC_TypeDef; 00446 /*------------- General Purpose Input/Output (GPIO) --------------------------*/ 00447 typedef struct 00448 { 00449 __IO uint32_t DIR; 00450 uint32_t RESERVED0[3]; 00451 __IO uint32_t MASK; 00452 __IO uint32_t PIN; 00453 __IO uint32_t SET; 00454 __O uint32_t CLR; 00455 } LPC_GPIO_TypeDef; 00456 00457 typedef struct 00458 { 00459 __I uint32_t IntStatus; 00460 __I uint32_t IO0IntStatR; 00461 __I uint32_t IO0IntStatF; 00462 __O uint32_t IO0IntClr; 00463 __IO uint32_t IO0IntEnR; 00464 __IO uint32_t IO0IntEnF; 00465 uint32_t RESERVED0[3]; 00466 __I uint32_t IO2IntStatR; 00467 __I uint32_t IO2IntStatF; 00468 __O uint32_t IO2IntClr; 00469 __IO uint32_t IO2IntEnR; 00470 __IO uint32_t IO2IntEnF; 00471 } LPC_GPIOINT_TypeDef; 00472 00473 /*------------- External Memory Controller (EMC) -----------------------------*/ 00474 typedef struct 00475 { 00476 __IO uint32_t Control; 00477 __I uint32_t Status; 00478 __IO uint32_t Config; 00479 uint32_t RESERVED0[5]; 00480 __IO uint32_t DynamicControl; 00481 __IO uint32_t DynamicRefresh; 00482 __IO uint32_t DynamicReadConfig; 00483 uint32_t RESERVED1[1]; 00484 __IO uint32_t DynamicRP; 00485 __IO uint32_t DynamicRAS; 00486 __IO uint32_t DynamicSREX; 00487 __IO uint32_t DynamicAPR; 00488 __IO uint32_t DynamicDAL; 00489 __IO uint32_t DynamicWR; 00490 __IO uint32_t DynamicRC; 00491 __IO uint32_t DynamicRFC; 00492 __IO uint32_t DynamicXSR; 00493 __IO uint32_t DynamicRRD; 00494 __IO uint32_t DynamicMRD; 00495 uint32_t RESERVED2[9]; 00496 __IO uint32_t StaticExtendedWait; 00497 uint32_t RESERVED3[31]; 00498 __IO uint32_t DynamicConfig0; 00499 __IO uint32_t DynamicRasCas0; 00500 uint32_t RESERVED4[6]; 00501 __IO uint32_t DynamicConfig1; 00502 __IO uint32_t DynamicRasCas1; 00503 uint32_t RESERVED5[6]; 00504 __IO uint32_t DynamicConfig2; 00505 __IO uint32_t DynamicRasCas2; 00506 uint32_t RESERVED6[6]; 00507 __IO uint32_t DynamicConfig3; 00508 __IO uint32_t DynamicRasCas3; 00509 uint32_t RESERVED7[38]; 00510 __IO uint32_t StaticConfig0; 00511 __IO uint32_t StaticWaitWen0; 00512 __IO uint32_t StaticWaitOen0; 00513 __IO uint32_t StaticWaitRd0; 00514 __IO uint32_t StaticWaitPage0; 00515 __IO uint32_t StaticWaitWr0; 00516 __IO uint32_t StaticWaitTurn0; 00517 uint32_t RESERVED8[1]; 00518 __IO uint32_t StaticConfig1; 00519 __IO uint32_t StaticWaitWen1; 00520 __IO uint32_t StaticWaitOen1; 00521 __IO uint32_t StaticWaitRd1; 00522 __IO uint32_t StaticWaitPage1; 00523 __IO uint32_t StaticWaitWr1; 00524 __IO uint32_t StaticWaitTurn1; 00525 uint32_t RESERVED9[1]; 00526 __IO uint32_t StaticConfig2; 00527 __IO uint32_t StaticWaitWen2; 00528 __IO uint32_t StaticWaitOen2; 00529 __IO uint32_t StaticWaitRd2; 00530 __IO uint32_t StaticWaitPage2; 00531 __IO uint32_t StaticWaitWr2; 00532 __IO uint32_t StaticWaitTurn2; 00533 uint32_t RESERVED10[1]; 00534 __IO uint32_t StaticConfig3; 00535 __IO uint32_t StaticWaitWen3; 00536 __IO uint32_t StaticWaitOen3; 00537 __IO uint32_t StaticWaitRd3; 00538 __IO uint32_t StaticWaitPage3; 00539 __IO uint32_t StaticWaitWr3; 00540 __IO uint32_t StaticWaitTurn3; 00541 } LPC_EMC_TypeDef; 00542 00543 /*------------- Watchdog Timer (WDT) -----------------------------------------*/ 00544 typedef struct 00545 { 00546 __IO uint8_t MOD; 00547 uint8_t RESERVED0[3]; 00548 __IO uint32_t TC; 00549 __O uint8_t FEED; 00550 uint8_t RESERVED1[3]; 00551 __I uint32_t TV; 00552 uint32_t RESERVED2; 00553 __IO uint32_t WARNINT; 00554 __IO uint32_t WINDOW; 00555 } LPC_WDT_TypeDef; 00556 00557 /*------------- Timer (TIM) --------------------------------------------------*/ 00558 typedef struct 00559 { 00560 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ 00561 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ 00562 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ 00563 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ 00564 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ 00565 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ 00566 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ 00567 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ 00568 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ 00569 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ 00570 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ 00571 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ 00572 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ 00573 uint32_t RESERVED0[2]; 00574 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ 00575 uint32_t RESERVED1[12]; 00576 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ 00577 } LPC_TIM_TypeDef; 00578 00579 00580 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ 00581 typedef struct 00582 { 00583 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ 00584 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ 00585 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ 00586 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ 00587 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ 00588 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ 00589 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ 00590 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ 00591 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ 00592 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ 00593 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ 00594 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ 00595 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ 00596 __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */ 00597 __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */ 00598 uint32_t RESERVED0; 00599 __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */ 00600 __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */ 00601 __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */ 00602 __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */ 00603 __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */ 00604 uint32_t RESERVED1[7]; 00605 __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */ 00606 } LPC_PWM_TypeDef; 00607 00608 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ 00609 /* There are three types of UARTs on the chip: 00610 (1) UART0,UART2, and UART3 are the standard UART. 00611 (2) UART1 is the standard with modem capability. 00612 (3) USART(UART4) is the sync/async UART with smart card capability. 00613 More details can be found on the Users Manual. */ 00614 00615 #if 0 00616 typedef struct 00617 { 00618 union { 00619 __I uint8_t RBR; 00620 __O uint8_t THR; 00621 __IO uint8_t DLL; 00622 uint32_t RESERVED0; 00623 }; 00624 union { 00625 __IO uint8_t DLM; 00626 __IO uint32_t IER; 00627 }; 00628 union { 00629 __I uint32_t IIR; 00630 __O uint8_t FCR; 00631 }; 00632 __IO uint8_t LCR; 00633 uint8_t RESERVED1[7]; 00634 __I uint8_t LSR; 00635 uint8_t RESERVED2[7]; 00636 __IO uint8_t SCR; 00637 uint8_t RESERVED3[3]; 00638 __IO uint32_t ACR; 00639 __IO uint8_t ICR; 00640 uint8_t RESERVED4[3]; 00641 __IO uint8_t FDR; 00642 uint8_t RESERVED5[7]; 00643 __IO uint8_t TER; 00644 uint8_t RESERVED6[39]; 00645 __I uint8_t FIFOLVL; 00646 } LPC_UART_TypeDef; 00647 #else 00648 typedef struct 00649 { 00650 union 00651 { 00652 __I uint8_t RBR; 00653 __O uint8_t THR; 00654 __IO uint8_t DLL; 00655 uint32_t RESERVED0; 00656 }; 00657 union 00658 { 00659 __IO uint8_t DLM; 00660 __IO uint32_t IER; 00661 }; 00662 union 00663 { 00664 __I uint32_t IIR; 00665 __O uint8_t FCR; 00666 }; 00667 __IO uint8_t LCR; 00668 uint8_t RESERVED1[7];//Reserved 00669 __I uint8_t LSR; 00670 uint8_t RESERVED2[7];//Reserved 00671 __IO uint8_t SCR; 00672 uint8_t RESERVED3[3];//Reserved 00673 __IO uint32_t ACR; 00674 __IO uint8_t ICR; 00675 uint8_t RESERVED4[3];//Reserved 00676 __IO uint8_t FDR; 00677 uint8_t RESERVED5[7];//Reserved 00678 __IO uint8_t TER; 00679 uint8_t RESERVED8[27];//Reserved 00680 __IO uint8_t RS485CTRL; 00681 uint8_t RESERVED9[3];//Reserved 00682 __IO uint8_t ADRMATCH; 00683 uint8_t RESERVED10[3];//Reserved 00684 __IO uint8_t RS485DLY; 00685 uint8_t RESERVED11[3];//Reserved 00686 __I uint8_t FIFOLVL; 00687 }LPC_UART_TypeDef; 00688 #endif 00689 00690 00691 typedef struct 00692 { 00693 union { 00694 __I uint8_t RBR; 00695 __O uint8_t THR; 00696 __IO uint8_t DLL; 00697 uint32_t RESERVED0; 00698 }; 00699 union { 00700 __IO uint8_t DLM; 00701 __IO uint32_t IER; 00702 }; 00703 union { 00704 __I uint32_t IIR; 00705 __O uint8_t FCR; 00706 }; 00707 __IO uint8_t LCR; 00708 uint8_t RESERVED1[3]; 00709 __IO uint8_t MCR; 00710 uint8_t RESERVED2[3]; 00711 __I uint8_t LSR; 00712 uint8_t RESERVED3[3]; 00713 __I uint8_t MSR; 00714 uint8_t RESERVED4[3]; 00715 __IO uint8_t SCR; 00716 uint8_t RESERVED5[3]; 00717 __IO uint32_t ACR; 00718 uint32_t RESERVED6; 00719 __IO uint32_t FDR; 00720 uint32_t RESERVED7; 00721 __IO uint8_t TER; 00722 uint8_t RESERVED8[27]; 00723 __IO uint8_t RS485CTRL; 00724 uint8_t RESERVED9[3]; 00725 __IO uint8_t ADRMATCH; 00726 uint8_t RESERVED10[3]; 00727 __IO uint8_t RS485DLY; 00728 uint8_t RESERVED11[3]; 00729 __I uint8_t FIFOLVL; 00730 } LPC_UART1_TypeDef; 00731 00732 typedef struct 00733 { 00734 union { 00735 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ 00736 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ 00737 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ 00738 }; 00739 union { 00740 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ 00741 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ 00742 }; 00743 union { 00744 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ 00745 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ 00746 }; 00747 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ 00748 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ 00749 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ 00750 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ 00751 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ 00752 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ 00753 __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */ 00754 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ 00755 __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */ 00756 __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */ 00757 __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */ 00758 uint32_t RESERVED0[2]; 00759 __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */ 00760 uint32_t RESERVED1; 00761 __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */ 00762 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ 00763 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ 00764 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ 00765 __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */ 00766 __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */ 00767 uint32_t RESERVED2[989]; 00768 __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */ 00769 __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */ 00770 __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */ 00771 __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */ 00772 __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */ 00773 __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */ 00774 __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */ 00775 uint32_t RESERVED3[3]; 00776 __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */ 00777 } LPC_UART4_TypeDef; 00778 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00779 typedef struct 00780 { 00781 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ 00782 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ 00783 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ 00784 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ 00785 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ 00786 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ 00787 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ 00788 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ 00789 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ 00790 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ 00791 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ 00792 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ 00793 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ 00794 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ 00795 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ 00796 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ 00797 } LPC_I2C_TypeDef; 00798 00799 /*------------- Real-Time Clock (RTC) ----------------------------------------*/ 00800 typedef struct 00801 { 00802 __IO uint8_t ILR; 00803 uint8_t RESERVED0[7]; 00804 __IO uint8_t CCR; 00805 uint8_t RESERVED1[3]; 00806 __IO uint8_t CIIR; 00807 uint8_t RESERVED2[3]; 00808 __IO uint8_t AMR; 00809 uint8_t RESERVED3[3]; 00810 __I uint32_t CTIME0; 00811 __I uint32_t CTIME1; 00812 __I uint32_t CTIME2; 00813 __IO uint8_t SEC; 00814 uint8_t RESERVED4[3]; 00815 __IO uint8_t MIN; 00816 uint8_t RESERVED5[3]; 00817 __IO uint8_t HOUR; 00818 uint8_t RESERVED6[3]; 00819 __IO uint8_t DOM; 00820 uint8_t RESERVED7[3]; 00821 __IO uint8_t DOW; 00822 uint8_t RESERVED8[3]; 00823 __IO uint16_t DOY; 00824 uint16_t RESERVED9; 00825 __IO uint8_t MONTH; 00826 uint8_t RESERVED10[3]; 00827 __IO uint16_t YEAR; 00828 uint16_t RESERVED11; 00829 __IO uint32_t CALIBRATION; 00830 __IO uint32_t GPREG0; 00831 __IO uint32_t GPREG1; 00832 __IO uint32_t GPREG2; 00833 __IO uint32_t GPREG3; 00834 __IO uint32_t GPREG4; 00835 __IO uint8_t RTC_AUXEN; 00836 uint8_t RESERVED12[3]; 00837 __IO uint8_t RTC_AUX; 00838 uint8_t RESERVED13[3]; 00839 __IO uint8_t ALSEC; 00840 uint8_t RESERVED14[3]; 00841 __IO uint8_t ALMIN; 00842 uint8_t RESERVED15[3]; 00843 __IO uint8_t ALHOUR; 00844 uint8_t RESERVED16[3]; 00845 __IO uint8_t ALDOM; 00846 uint8_t RESERVED17[3]; 00847 __IO uint8_t ALDOW; 00848 uint8_t RESERVED18[3]; 00849 __IO uint16_t ALDOY; 00850 uint16_t RESERVED19; 00851 __IO uint8_t ALMON; 00852 uint8_t RESERVED20[3]; 00853 __IO uint16_t ALYEAR; 00854 uint16_t RESERVED21; 00855 __IO uint32_t ERSTATUS; 00856 __IO uint32_t ERCONTROL; 00857 __IO uint32_t ERCOUNTERS; 00858 uint32_t RESERVED22; 00859 __IO uint32_t ERFIRSTSTAMP0; 00860 __IO uint32_t ERFIRSTSTAMP1; 00861 __IO uint32_t ERFIRSTSTAMP2; 00862 uint32_t RESERVED23; 00863 __IO uint32_t ERLASTSTAMP0; 00864 __IO uint32_t ERLASTSTAMP1; 00865 __IO uint32_t ERLASTSTAMP2; 00866 } LPC_RTC_TypeDef; 00867 00868 00869 00870 /*------------- Pin Connect Block (PINCON) -----------------------------------*/ 00871 typedef struct 00872 { 00873 __IO uint32_t P0_0; /* 0x000 */ 00874 __IO uint32_t P0_1; 00875 __IO uint32_t P0_2; 00876 __IO uint32_t P0_3; 00877 __IO uint32_t P0_4; 00878 __IO uint32_t P0_5; 00879 __IO uint32_t P0_6; 00880 __IO uint32_t P0_7; 00881 00882 __IO uint32_t P0_8; /* 0x020 */ 00883 __IO uint32_t P0_9; 00884 __IO uint32_t P0_10; 00885 __IO uint32_t P0_11; 00886 __IO uint32_t P0_12; 00887 __IO uint32_t P0_13; 00888 __IO uint32_t P0_14; 00889 __IO uint32_t P0_15; 00890 00891 __IO uint32_t P0_16; /* 0x040 */ 00892 __IO uint32_t P0_17; 00893 __IO uint32_t P0_18; 00894 __IO uint32_t P0_19; 00895 __IO uint32_t P0_20; 00896 __IO uint32_t P0_21; 00897 __IO uint32_t P0_22; 00898 __IO uint32_t P0_23; 00899 00900 __IO uint32_t P0_24; /* 0x060 */ 00901 __IO uint32_t P0_25; 00902 __IO uint32_t P0_26; 00903 __IO uint32_t P0_27; 00904 __IO uint32_t P0_28; 00905 __IO uint32_t P0_29; 00906 __IO uint32_t P0_30; 00907 __IO uint32_t P0_31; 00908 00909 __IO uint32_t P1_0; /* 0x080 */ 00910 __IO uint32_t P1_1; 00911 __IO uint32_t P1_2; 00912 __IO uint32_t P1_3; 00913 __IO uint32_t P1_4; 00914 __IO uint32_t P1_5; 00915 __IO uint32_t P1_6; 00916 __IO uint32_t P1_7; 00917 00918 __IO uint32_t P1_8; /* 0x0A0 */ 00919 __IO uint32_t P1_9; 00920 __IO uint32_t P1_10; 00921 __IO uint32_t P1_11; 00922 __IO uint32_t P1_12; 00923 __IO uint32_t P1_13; 00924 __IO uint32_t P1_14; 00925 __IO uint32_t P1_15; 00926 00927 __IO uint32_t P1_16; /* 0x0C0 */ 00928 __IO uint32_t P1_17; 00929 __IO uint32_t P1_18; 00930 __IO uint32_t P1_19; 00931 __IO uint32_t P1_20; 00932 __IO uint32_t P1_21; 00933 __IO uint32_t P1_22; 00934 __IO uint32_t P1_23; 00935 00936 __IO uint32_t P1_24; /* 0x0E0 */ 00937 __IO uint32_t P1_25; 00938 __IO uint32_t P1_26; 00939 __IO uint32_t P1_27; 00940 __IO uint32_t P1_28; 00941 __IO uint32_t P1_29; 00942 __IO uint32_t P1_30; 00943 __IO uint32_t P1_31; 00944 00945 __IO uint32_t P2_0; /* 0x100 */ 00946 __IO uint32_t P2_1; 00947 __IO uint32_t P2_2; 00948 __IO uint32_t P2_3; 00949 __IO uint32_t P2_4; 00950 __IO uint32_t P2_5; 00951 __IO uint32_t P2_6; 00952 __IO uint32_t P2_7; 00953 00954 __IO uint32_t P2_8; /* 0x120 */ 00955 __IO uint32_t P2_9; 00956 __IO uint32_t P2_10; 00957 __IO uint32_t P2_11; 00958 __IO uint32_t P2_12; 00959 __IO uint32_t P2_13; 00960 __IO uint32_t P2_14; 00961 __IO uint32_t P2_15; 00962 00963 __IO uint32_t P2_16; /* 0x140 */ 00964 __IO uint32_t P2_17; 00965 __IO uint32_t P2_18; 00966 __IO uint32_t P2_19; 00967 __IO uint32_t P2_20; 00968 __IO uint32_t P2_21; 00969 __IO uint32_t P2_22; 00970 __IO uint32_t P2_23; 00971 00972 __IO uint32_t P2_24; /* 0x160 */ 00973 __IO uint32_t P2_25; 00974 __IO uint32_t P2_26; 00975 __IO uint32_t P2_27; 00976 __IO uint32_t P2_28; 00977 __IO uint32_t P2_29; 00978 __IO uint32_t P2_30; 00979 __IO uint32_t P2_31; 00980 00981 __IO uint32_t P3_0; /* 0x180 */ 00982 __IO uint32_t P3_1; 00983 __IO uint32_t P3_2; 00984 __IO uint32_t P3_3; 00985 __IO uint32_t P3_4; 00986 __IO uint32_t P3_5; 00987 __IO uint32_t P3_6; 00988 __IO uint32_t P3_7; 00989 00990 __IO uint32_t P3_8; /* 0x1A0 */ 00991 __IO uint32_t P3_9; 00992 __IO uint32_t P3_10; 00993 __IO uint32_t P3_11; 00994 __IO uint32_t P3_12; 00995 __IO uint32_t P3_13; 00996 __IO uint32_t P3_14; 00997 __IO uint32_t P3_15; 00998 00999 __IO uint32_t P3_16; /* 0x1C0 */ 01000 __IO uint32_t P3_17; 01001 __IO uint32_t P3_18; 01002 __IO uint32_t P3_19; 01003 __IO uint32_t P3_20; 01004 __IO uint32_t P3_21; 01005 __IO uint32_t P3_22; 01006 __IO uint32_t P3_23; 01007 01008 __IO uint32_t P3_24; /* 0x1E0 */ 01009 __IO uint32_t P3_25; 01010 __IO uint32_t P3_26; 01011 __IO uint32_t P3_27; 01012 __IO uint32_t P3_28; 01013 __IO uint32_t P3_29; 01014 __IO uint32_t P3_30; 01015 __IO uint32_t P3_31; 01016 01017 __IO uint32_t P4_0; /* 0x200 */ 01018 __IO uint32_t P4_1; 01019 __IO uint32_t P4_2; 01020 __IO uint32_t P4_3; 01021 __IO uint32_t P4_4; 01022 __IO uint32_t P4_5; 01023 __IO uint32_t P4_6; 01024 __IO uint32_t P4_7; 01025 01026 __IO uint32_t P4_8; /* 0x220 */ 01027 __IO uint32_t P4_9; 01028 __IO uint32_t P4_10; 01029 __IO uint32_t P4_11; 01030 __IO uint32_t P4_12; 01031 __IO uint32_t P4_13; 01032 __IO uint32_t P4_14; 01033 __IO uint32_t P4_15; 01034 01035 __IO uint32_t P4_16; /* 0x240 */ 01036 __IO uint32_t P4_17; 01037 __IO uint32_t P4_18; 01038 __IO uint32_t P4_19; 01039 __IO uint32_t P4_20; 01040 __IO uint32_t P4_21; 01041 __IO uint32_t P4_22; 01042 __IO uint32_t P4_23; 01043 01044 __IO uint32_t P4_24; /* 0x260 */ 01045 __IO uint32_t P4_25; 01046 __IO uint32_t P4_26; 01047 __IO uint32_t P4_27; 01048 __IO uint32_t P4_28; 01049 __IO uint32_t P4_29; 01050 __IO uint32_t P4_30; 01051 __IO uint32_t P4_31; 01052 01053 __IO uint32_t P5_0; /* 0x280 */ 01054 __IO uint32_t P5_1; 01055 __IO uint32_t P5_2; 01056 __IO uint32_t P5_3; 01057 __IO uint32_t P5_4; /* 0x290 */ 01058 } LPC_IOCON_TypeDef; 01059 01060 01061 01062 01063 01064 01065 /*------------- Synchronous Serial Communication (SSP) -----------------------*/ 01066 typedef struct 01067 { 01068 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ 01069 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ 01070 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ 01071 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ 01072 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ 01073 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ 01074 __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ 01075 __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ 01076 __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ 01077 __IO uint32_t DMACR; 01078 } LPC_SSP_TypeDef; 01079 01080 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ 01081 typedef struct 01082 { 01083 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ 01084 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ 01085 uint32_t RESERVED0; 01086 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ 01087 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ 01088 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ 01089 __IO uint32_t ADTRM; 01090 } LPC_ADC_TypeDef; 01091 01092 /*------------- Controller Area Network (CAN) --------------------------------*/ 01093 typedef struct 01094 { 01095 __IO uint32_t mask[512]; /* ID Masks */ 01096 } LPC_CANAF_RAM_TypeDef; 01097 01098 typedef struct /* Acceptance Filter Registers */ 01099 { 01100 ///Offset: 0x00000000 - Acceptance Filter Register 01101 __IO uint32_t AFMR; 01102 01103 ///Offset: 0x00000004 - Standard Frame Individual Start Address Register 01104 __IO uint32_t SFF_sa; 01105 01106 ///Offset: 0x00000008 - Standard Frame Group Start Address Register 01107 __IO uint32_t SFF_GRP_sa; 01108 01109 ///Offset: 0x0000000C - Extended Frame Start Address Register 01110 __IO uint32_t EFF_sa; 01111 01112 ///Offset: 0x00000010 - Extended Frame Group Start Address Register 01113 __IO uint32_t EFF_GRP_sa; 01114 01115 ///Offset: 0x00000014 - End of AF Tables register 01116 __IO uint32_t ENDofTable; 01117 01118 ///Offset: 0x00000018 - LUT Error Address register 01119 __I uint32_t LUTerrAd; 01120 01121 ///Offset: 0x0000001C - LUT Error Register 01122 __I uint32_t LUTerr; 01123 01124 ///Offset: 0x00000020 - CAN Central Transmit Status Register 01125 __IO uint32_t FCANIE; 01126 01127 ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0 01128 __IO uint32_t FCANIC0; 01129 01130 ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1 01131 __IO uint32_t FCANIC1; 01132 } LPC_CANAF_TypeDef; 01133 01134 typedef struct /* Central Registers */ 01135 { 01136 __I uint32_t TxSR; 01137 __I uint32_t RxSR; 01138 __I uint32_t MSR; 01139 } LPC_CANCR_TypeDef; 01140 01141 typedef struct /* Controller Registers */ 01142 { 01143 ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller 01144 __IO uint32_t MOD; 01145 01146 ///Offset: 0x00000004 - Command bits that affect the state 01147 __O uint32_t CMR; 01148 01149 ///Offset: 0x00000008 - Global Controller Status and Error Counters 01150 __IO uint32_t GSR; 01151 01152 ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture 01153 __I uint32_t ICR; 01154 01155 ///Offset: 0x00000010 - Interrupt Enable Register 01156 __IO uint32_t IER; 01157 01158 ///Offset: 0x00000014 - Bus Timing Register 01159 __IO uint32_t BTR; 01160 01161 ///Offset: 0x00000018 - Error Warning Limit 01162 __IO uint32_t EWL; 01163 01164 ///Offset: 0x0000001C - Status Register 01165 __I uint32_t SR; 01166 01167 ///Offset: 0x00000020 - Receive frame status 01168 __IO uint32_t RFS; 01169 01170 ///Offset: 0x00000024 - Received Identifier 01171 __IO uint32_t RID; 01172 01173 ///Offset: 0x00000028 - Received data bytes 1-4 01174 __IO uint32_t RDA; 01175 01176 ///Offset: 0x0000002C - Received data bytes 5-8 01177 __IO uint32_t RDB; 01178 01179 ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1) 01180 __IO uint32_t TFI1; 01181 01182 ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1) 01183 __IO uint32_t TID1; 01184 01185 ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1) 01186 __IO uint32_t TDA1; 01187 01188 ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1) 01189 __IO uint32_t TDB1; 01190 01191 ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2) 01192 __IO uint32_t TFI2; 01193 01194 ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2) 01195 __IO uint32_t TID2; 01196 01197 ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2) 01198 __IO uint32_t TDA2; 01199 01200 ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2) 01201 __IO uint32_t TDB2; 01202 01203 ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3) 01204 __IO uint32_t TFI3; 01205 01206 ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3) 01207 __IO uint32_t TID3; 01208 01209 ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3) 01210 __IO uint32_t TDA3; 01211 01212 ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3) 01213 __IO uint32_t TDB3; 01214 } LPC_CAN_TypeDef; 01215 01216 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ 01217 typedef struct 01218 { 01219 __IO uint32_t CR; 01220 __IO uint32_t CTRL; 01221 __IO uint32_t CNTVAL; 01222 } LPC_DAC_TypeDef; 01223 01224 01225 /*------------- Inter IC Sound (I2S) -----------------------------------------*/ 01226 typedef struct 01227 { 01228 __IO uint32_t DAO; 01229 __IO uint32_t DAI; 01230 __O uint32_t TXFIFO; 01231 __I uint32_t RXFIFO; 01232 __I uint32_t STATE; 01233 __IO uint32_t DMA1; 01234 __IO uint32_t DMA2; 01235 __IO uint32_t IRQ; 01236 __IO uint32_t TXRATE; 01237 __IO uint32_t RXRATE; 01238 __IO uint32_t TXBITRATE; 01239 __IO uint32_t RXBITRATE; 01240 __IO uint32_t TXMODE; 01241 __IO uint32_t RXMODE; 01242 } LPC_I2S_TypeDef; 01243 01244 01245 01246 01247 01248 01249 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ 01250 typedef struct 01251 { 01252 __I uint32_t CON; 01253 __O uint32_t CON_SET; 01254 __O uint32_t CON_CLR; 01255 __I uint32_t CAPCON; 01256 __O uint32_t CAPCON_SET; 01257 __O uint32_t CAPCON_CLR; 01258 __IO uint32_t TC0; 01259 __IO uint32_t TC1; 01260 __IO uint32_t TC2; 01261 __IO uint32_t LIM0; 01262 __IO uint32_t LIM1; 01263 __IO uint32_t LIM2; 01264 __IO uint32_t MAT0; 01265 __IO uint32_t MAT1; 01266 __IO uint32_t MAT2; 01267 __IO uint32_t DT; 01268 __IO uint32_t CP; 01269 __IO uint32_t CAP0; 01270 __IO uint32_t CAP1; 01271 __IO uint32_t CAP2; 01272 __I uint32_t INTEN; 01273 __O uint32_t INTEN_SET; 01274 __O uint32_t INTEN_CLR; 01275 __I uint32_t CNTCON; 01276 __O uint32_t CNTCON_SET; 01277 __O uint32_t CNTCON_CLR; 01278 __I uint32_t INTF; 01279 __O uint32_t INTF_SET; 01280 __O uint32_t INTF_CLR; 01281 __O uint32_t CAP_CLR; 01282 } LPC_MCPWM_TypeDef; 01283 01284 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ 01285 typedef struct 01286 { 01287 __O uint32_t CON; 01288 __I uint32_t STAT; 01289 __IO uint32_t CONF; 01290 __I uint32_t POS; 01291 __IO uint32_t MAXPOS; 01292 __IO uint32_t CMPOS0; 01293 __IO uint32_t CMPOS1; 01294 __IO uint32_t CMPOS2; 01295 __I uint32_t INXCNT; 01296 __IO uint32_t INXCMP0; 01297 __IO uint32_t LOAD; 01298 __I uint32_t TIME; 01299 __I uint32_t VEL; 01300 __I uint32_t CAP; 01301 __IO uint32_t VELCOMP; 01302 __IO uint32_t FILTERPHA; 01303 __IO uint32_t FILTERPHB; 01304 __IO uint32_t FILTERINX; 01305 __IO uint32_t WINDOW; 01306 __IO uint32_t INXCMP1; 01307 __IO uint32_t INXCMP2; 01308 uint32_t RESERVED0[993]; 01309 __O uint32_t IEC; 01310 __O uint32_t IES; 01311 __I uint32_t INTSTAT; 01312 __I uint32_t IE; 01313 __O uint32_t CLR; 01314 __O uint32_t SET; 01315 } LPC_QEI_TypeDef; 01316 01317 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/ 01318 typedef struct 01319 { 01320 __IO uint32_t POWER; 01321 __IO uint32_t CLOCK; 01322 __IO uint32_t ARGUMENT; 01323 __IO uint32_t COMMAND; 01324 __I uint32_t RESP_CMD; 01325 __I uint32_t RESP0; 01326 __I uint32_t RESP1; 01327 __I uint32_t RESP2; 01328 __I uint32_t RESP3; 01329 __IO uint32_t DATATMR; 01330 __IO uint32_t DATALEN; 01331 __IO uint32_t DATACTRL; 01332 __I uint32_t DATACNT; 01333 __I uint32_t STATUS; 01334 __O uint32_t CLEAR; 01335 __IO uint32_t MASK0; 01336 uint32_t RESERVED0[2]; 01337 __I uint32_t FIFOCNT; 01338 uint32_t RESERVED1[13]; 01339 __IO uint32_t FIFO[16]; 01340 } LPC_MCI_TypeDef; 01341 01342 01343 01344 01345 01346 01347 01348 01349 01350 01351 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/ 01352 typedef struct 01353 { 01354 __IO uint32_t CMD; /* 0x0080 */ 01355 __IO uint32_t ADDR; 01356 __IO uint32_t WDATA; 01357 __IO uint32_t RDATA; 01358 __IO uint32_t WSTATE; /* 0x0090 */ 01359 __IO uint32_t CLKDIV; 01360 __IO uint32_t PWRDWN; /* 0x0098 */ 01361 uint32_t RESERVED0[975]; 01362 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ 01363 __IO uint32_t INT_SET_ENABLE; 01364 __IO uint32_t INT_STATUS; /* 0x0FE0 */ 01365 __IO uint32_t INT_ENABLE; 01366 __IO uint32_t INT_CLR_STATUS; 01367 __IO uint32_t INT_SET_STATUS; 01368 } LPC_EEPROM_TypeDef; 01369 01370 01371 /*------------- COMPARATOR ----------------------------------------------------*/ 01372 01373 typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */ 01374 __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */ 01375 __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */ 01376 __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */ 01377 } LPC_COMPARATOR_Type; 01378 01379 01380 #if defined ( __CC_ARM ) 01381 #pragma no_anon_unions 01382 #endif 01383 01384 /******************************************************************************/ 01385 /* Peripheral memory map */ 01386 /******************************************************************************/ 01387 /* Base addresses */ 01388 #define LPC_FLASH_BASE (0x00000000UL) 01389 #define LPC_RAM_BASE (0x10000000UL) 01390 #define LPC_PERI_RAM_BASE (0x20000000UL) 01391 #define LPC_APB0_BASE (0x40000000UL) 01392 #define LPC_APB1_BASE (0x40080000UL) 01393 #define LPC_AHBRAM1_BASE (0x20004000UL) 01394 #define LPC_AHB_BASE (0x20080000UL) 01395 #define LPC_CM3_BASE (0xE0000000UL) 01396 01397 /* APB0 peripherals */ 01398 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) 01399 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) 01400 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) 01401 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) 01402 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) 01403 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) 01404 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) 01405 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) 01406 #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000) 01407 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) 01408 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) 01409 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) 01410 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) 01411 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) 01412 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) 01413 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) 01414 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) 01415 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) 01416 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) 01417 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) 01418 01419 /* APB1 peripherals */ 01420 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) 01421 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) 01422 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) 01423 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) 01424 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) 01425 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) 01426 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) 01427 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) 01428 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) 01429 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) 01430 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) 01431 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) 01432 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) 01433 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) 01434 01435 /* AHB peripherals */ 01436 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) 01437 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) 01438 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) 01439 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) 01440 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) 01441 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) 01442 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) 01443 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) 01444 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) 01445 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) 01446 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) 01447 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) 01448 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) 01449 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) 01450 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) 01451 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) 01452 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) 01453 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) 01454 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) 01455 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) 01456 01457 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) 01458 01459 01460 /******************************************************************************/ 01461 /* Peripheral declaration */ 01462 /******************************************************************************/ 01463 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) 01464 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) 01465 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) 01466 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) 01467 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) 01468 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) 01469 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) 01470 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) 01471 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) 01472 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) 01473 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) 01474 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) 01475 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) 01476 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) 01477 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) 01478 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) 01479 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) 01480 #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE) 01481 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) 01482 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) 01483 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) 01484 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) 01485 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) 01486 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) 01487 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) 01488 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) 01489 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) 01490 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) 01491 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) 01492 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) 01493 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) 01494 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) 01495 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) 01496 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) 01497 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) 01498 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) 01499 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) 01500 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) 01501 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) 01502 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) 01503 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) 01504 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) 01505 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) 01506 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) 01507 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) 01508 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) 01509 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) 01510 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) 01511 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) 01512 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) 01513 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) 01514 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) 01515 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) 01516 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) 01517 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) 01518 01519 01520 01521 #endif // __LPC407x_8x_177x_8x_H__
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