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stm_lib/inc/stm32f10x_tim.h@0:9dcf85d9b2f3, 2017-09-04 (annotated)
- Committer:
- Sergunb
- Date:
- Mon Sep 04 12:05:05 2017 +0000
- Revision:
- 0:9dcf85d9b2f3
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Sergunb | 0:9dcf85d9b2f3 | 1 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 2 | ****************************************************************************** |
| Sergunb | 0:9dcf85d9b2f3 | 3 | * @file stm32f10x_tim.h |
| Sergunb | 0:9dcf85d9b2f3 | 4 | * @author MCD Application Team |
| Sergunb | 0:9dcf85d9b2f3 | 5 | * @version V3.4.0 |
| Sergunb | 0:9dcf85d9b2f3 | 6 | * @date 10/15/2010 |
| Sergunb | 0:9dcf85d9b2f3 | 7 | * @brief This file contains all the functions prototypes for the TIM firmware |
| Sergunb | 0:9dcf85d9b2f3 | 8 | * library. |
| Sergunb | 0:9dcf85d9b2f3 | 9 | ****************************************************************************** |
| Sergunb | 0:9dcf85d9b2f3 | 10 | * @copy |
| Sergunb | 0:9dcf85d9b2f3 | 11 | * |
| Sergunb | 0:9dcf85d9b2f3 | 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
| Sergunb | 0:9dcf85d9b2f3 | 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
| Sergunb | 0:9dcf85d9b2f3 | 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
| Sergunb | 0:9dcf85d9b2f3 | 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
| Sergunb | 0:9dcf85d9b2f3 | 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
| Sergunb | 0:9dcf85d9b2f3 | 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
| Sergunb | 0:9dcf85d9b2f3 | 18 | * |
| Sergunb | 0:9dcf85d9b2f3 | 19 | * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
| Sergunb | 0:9dcf85d9b2f3 | 20 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 21 | |
| Sergunb | 0:9dcf85d9b2f3 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Sergunb | 0:9dcf85d9b2f3 | 23 | #ifndef __STM32F10x_TIM_H |
| Sergunb | 0:9dcf85d9b2f3 | 24 | #define __STM32F10x_TIM_H |
| Sergunb | 0:9dcf85d9b2f3 | 25 | |
| Sergunb | 0:9dcf85d9b2f3 | 26 | #ifdef __cplusplus |
| Sergunb | 0:9dcf85d9b2f3 | 27 | extern "C" { |
| Sergunb | 0:9dcf85d9b2f3 | 28 | #endif |
| Sergunb | 0:9dcf85d9b2f3 | 29 | |
| Sergunb | 0:9dcf85d9b2f3 | 30 | /* Includes ------------------------------------------------------------------*/ |
| Sergunb | 0:9dcf85d9b2f3 | 31 | #include "stm32f10x.h" |
| Sergunb | 0:9dcf85d9b2f3 | 32 | |
| Sergunb | 0:9dcf85d9b2f3 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver |
| Sergunb | 0:9dcf85d9b2f3 | 34 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 35 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 36 | |
| Sergunb | 0:9dcf85d9b2f3 | 37 | /** @addtogroup TIM |
| Sergunb | 0:9dcf85d9b2f3 | 38 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 39 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 40 | |
| Sergunb | 0:9dcf85d9b2f3 | 41 | /** @defgroup TIM_Exported_Types |
| Sergunb | 0:9dcf85d9b2f3 | 42 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 43 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 44 | |
| Sergunb | 0:9dcf85d9b2f3 | 45 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 46 | * @brief TIM Time Base Init structure definition |
| Sergunb | 0:9dcf85d9b2f3 | 47 | * @note This sturcture is used with all TIMx except for TIM6 and TIM7. |
| Sergunb | 0:9dcf85d9b2f3 | 48 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 49 | |
| Sergunb | 0:9dcf85d9b2f3 | 50 | typedef struct |
| Sergunb | 0:9dcf85d9b2f3 | 51 | { |
| Sergunb | 0:9dcf85d9b2f3 | 52 | uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
| Sergunb | 0:9dcf85d9b2f3 | 53 | This parameter can be a number between 0x0000 and 0xFFFF */ |
| Sergunb | 0:9dcf85d9b2f3 | 54 | |
| Sergunb | 0:9dcf85d9b2f3 | 55 | uint16_t TIM_CounterMode; /*!< Specifies the counter mode. |
| Sergunb | 0:9dcf85d9b2f3 | 56 | This parameter can be a value of @ref TIM_Counter_Mode */ |
| Sergunb | 0:9dcf85d9b2f3 | 57 | |
| Sergunb | 0:9dcf85d9b2f3 | 58 | uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active |
| Sergunb | 0:9dcf85d9b2f3 | 59 | Auto-Reload Register at the next update event. |
| Sergunb | 0:9dcf85d9b2f3 | 60 | This parameter must be a number between 0x0000 and 0xFFFF. */ |
| Sergunb | 0:9dcf85d9b2f3 | 61 | |
| Sergunb | 0:9dcf85d9b2f3 | 62 | uint16_t TIM_ClockDivision; /*!< Specifies the clock division. |
| Sergunb | 0:9dcf85d9b2f3 | 63 | This parameter can be a value of @ref TIM_Clock_Division_CKD */ |
| Sergunb | 0:9dcf85d9b2f3 | 64 | |
| Sergunb | 0:9dcf85d9b2f3 | 65 | uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
| Sergunb | 0:9dcf85d9b2f3 | 66 | reaches zero, an update event is generated and counting restarts |
| Sergunb | 0:9dcf85d9b2f3 | 67 | from the RCR value (N). |
| Sergunb | 0:9dcf85d9b2f3 | 68 | This means in PWM mode that (N+1) corresponds to: |
| Sergunb | 0:9dcf85d9b2f3 | 69 | - the number of PWM periods in edge-aligned mode |
| Sergunb | 0:9dcf85d9b2f3 | 70 | - the number of half PWM period in center-aligned mode |
| Sergunb | 0:9dcf85d9b2f3 | 71 | This parameter must be a number between 0x00 and 0xFF. |
| Sergunb | 0:9dcf85d9b2f3 | 72 | @note This parameter is valid only for TIM1 and TIM8. */ |
| Sergunb | 0:9dcf85d9b2f3 | 73 | } TIM_TimeBaseInitTypeDef; |
| Sergunb | 0:9dcf85d9b2f3 | 74 | |
| Sergunb | 0:9dcf85d9b2f3 | 75 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 76 | * @brief TIM Output Compare Init structure definition |
| Sergunb | 0:9dcf85d9b2f3 | 77 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 78 | |
| Sergunb | 0:9dcf85d9b2f3 | 79 | typedef struct |
| Sergunb | 0:9dcf85d9b2f3 | 80 | { |
| Sergunb | 0:9dcf85d9b2f3 | 81 | uint16_t TIM_OCMode; /*!< Specifies the TIM mode. |
| Sergunb | 0:9dcf85d9b2f3 | 82 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
| Sergunb | 0:9dcf85d9b2f3 | 83 | |
| Sergunb | 0:9dcf85d9b2f3 | 84 | uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. |
| Sergunb | 0:9dcf85d9b2f3 | 85 | This parameter can be a value of @ref TIM_Output_Compare_state */ |
| Sergunb | 0:9dcf85d9b2f3 | 86 | |
| Sergunb | 0:9dcf85d9b2f3 | 87 | uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. |
| Sergunb | 0:9dcf85d9b2f3 | 88 | This parameter can be a value of @ref TIM_Output_Compare_N_state |
| Sergunb | 0:9dcf85d9b2f3 | 89 | @note This parameter is valid only for TIM1 and TIM8. */ |
| Sergunb | 0:9dcf85d9b2f3 | 90 | |
| Sergunb | 0:9dcf85d9b2f3 | 91 | uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
| Sergunb | 0:9dcf85d9b2f3 | 92 | This parameter can be a number between 0x0000 and 0xFFFF */ |
| Sergunb | 0:9dcf85d9b2f3 | 93 | |
| Sergunb | 0:9dcf85d9b2f3 | 94 | uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. |
| Sergunb | 0:9dcf85d9b2f3 | 95 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
| Sergunb | 0:9dcf85d9b2f3 | 96 | |
| Sergunb | 0:9dcf85d9b2f3 | 97 | uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. |
| Sergunb | 0:9dcf85d9b2f3 | 98 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
| Sergunb | 0:9dcf85d9b2f3 | 99 | @note This parameter is valid only for TIM1 and TIM8. */ |
| Sergunb | 0:9dcf85d9b2f3 | 100 | |
| Sergunb | 0:9dcf85d9b2f3 | 101 | uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| Sergunb | 0:9dcf85d9b2f3 | 102 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
| Sergunb | 0:9dcf85d9b2f3 | 103 | @note This parameter is valid only for TIM1 and TIM8. */ |
| Sergunb | 0:9dcf85d9b2f3 | 104 | |
| Sergunb | 0:9dcf85d9b2f3 | 105 | uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| Sergunb | 0:9dcf85d9b2f3 | 106 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
| Sergunb | 0:9dcf85d9b2f3 | 107 | @note This parameter is valid only for TIM1 and TIM8. */ |
| Sergunb | 0:9dcf85d9b2f3 | 108 | } TIM_OCInitTypeDef; |
| Sergunb | 0:9dcf85d9b2f3 | 109 | |
| Sergunb | 0:9dcf85d9b2f3 | 110 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 111 | * @brief TIM Input Capture Init structure definition |
| Sergunb | 0:9dcf85d9b2f3 | 112 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 113 | |
| Sergunb | 0:9dcf85d9b2f3 | 114 | typedef struct |
| Sergunb | 0:9dcf85d9b2f3 | 115 | { |
| Sergunb | 0:9dcf85d9b2f3 | 116 | |
| Sergunb | 0:9dcf85d9b2f3 | 117 | uint16_t TIM_Channel; /*!< Specifies the TIM channel. |
| Sergunb | 0:9dcf85d9b2f3 | 118 | This parameter can be a value of @ref TIM_Channel */ |
| Sergunb | 0:9dcf85d9b2f3 | 119 | |
| Sergunb | 0:9dcf85d9b2f3 | 120 | uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. |
| Sergunb | 0:9dcf85d9b2f3 | 121 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| Sergunb | 0:9dcf85d9b2f3 | 122 | |
| Sergunb | 0:9dcf85d9b2f3 | 123 | uint16_t TIM_ICSelection; /*!< Specifies the input. |
| Sergunb | 0:9dcf85d9b2f3 | 124 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| Sergunb | 0:9dcf85d9b2f3 | 125 | |
| Sergunb | 0:9dcf85d9b2f3 | 126 | uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
| Sergunb | 0:9dcf85d9b2f3 | 127 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| Sergunb | 0:9dcf85d9b2f3 | 128 | |
| Sergunb | 0:9dcf85d9b2f3 | 129 | uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. |
| Sergunb | 0:9dcf85d9b2f3 | 130 | This parameter can be a number between 0x0 and 0xF */ |
| Sergunb | 0:9dcf85d9b2f3 | 131 | } TIM_ICInitTypeDef; |
| Sergunb | 0:9dcf85d9b2f3 | 132 | |
| Sergunb | 0:9dcf85d9b2f3 | 133 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 134 | * @brief BDTR structure definition |
| Sergunb | 0:9dcf85d9b2f3 | 135 | * @note This sturcture is used only with TIM1 and TIM8. |
| Sergunb | 0:9dcf85d9b2f3 | 136 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 137 | |
| Sergunb | 0:9dcf85d9b2f3 | 138 | typedef struct |
| Sergunb | 0:9dcf85d9b2f3 | 139 | { |
| Sergunb | 0:9dcf85d9b2f3 | 140 | |
| Sergunb | 0:9dcf85d9b2f3 | 141 | uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. |
| Sergunb | 0:9dcf85d9b2f3 | 142 | This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ |
| Sergunb | 0:9dcf85d9b2f3 | 143 | |
| Sergunb | 0:9dcf85d9b2f3 | 144 | uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. |
| Sergunb | 0:9dcf85d9b2f3 | 145 | This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ |
| Sergunb | 0:9dcf85d9b2f3 | 146 | |
| Sergunb | 0:9dcf85d9b2f3 | 147 | uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. |
| Sergunb | 0:9dcf85d9b2f3 | 148 | This parameter can be a value of @ref Lock_level */ |
| Sergunb | 0:9dcf85d9b2f3 | 149 | |
| Sergunb | 0:9dcf85d9b2f3 | 150 | uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the |
| Sergunb | 0:9dcf85d9b2f3 | 151 | switching-on of the outputs. |
| Sergunb | 0:9dcf85d9b2f3 | 152 | This parameter can be a number between 0x00 and 0xFF */ |
| Sergunb | 0:9dcf85d9b2f3 | 153 | |
| Sergunb | 0:9dcf85d9b2f3 | 154 | uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. |
| Sergunb | 0:9dcf85d9b2f3 | 155 | This parameter can be a value of @ref Break_Input_enable_disable */ |
| Sergunb | 0:9dcf85d9b2f3 | 156 | |
| Sergunb | 0:9dcf85d9b2f3 | 157 | uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. |
| Sergunb | 0:9dcf85d9b2f3 | 158 | This parameter can be a value of @ref Break_Polarity */ |
| Sergunb | 0:9dcf85d9b2f3 | 159 | |
| Sergunb | 0:9dcf85d9b2f3 | 160 | uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. |
| Sergunb | 0:9dcf85d9b2f3 | 161 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
| Sergunb | 0:9dcf85d9b2f3 | 162 | } TIM_BDTRInitTypeDef; |
| Sergunb | 0:9dcf85d9b2f3 | 163 | |
| Sergunb | 0:9dcf85d9b2f3 | 164 | /** @defgroup TIM_Exported_constants |
| Sergunb | 0:9dcf85d9b2f3 | 165 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 166 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 167 | |
| Sergunb | 0:9dcf85d9b2f3 | 168 | #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 169 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 170 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 171 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 172 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 173 | ((PERIPH) == TIM6) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 174 | ((PERIPH) == TIM7) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 175 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 176 | ((PERIPH) == TIM9) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 177 | ((PERIPH) == TIM10)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 178 | ((PERIPH) == TIM11)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 179 | ((PERIPH) == TIM12)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 180 | ((PERIPH) == TIM13)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 181 | ((PERIPH) == TIM14)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 182 | ((PERIPH) == TIM15)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 183 | ((PERIPH) == TIM16)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 184 | ((PERIPH) == TIM17)) |
| Sergunb | 0:9dcf85d9b2f3 | 185 | |
| Sergunb | 0:9dcf85d9b2f3 | 186 | /* LIST1: TIM 1 and 8 */ |
| Sergunb | 0:9dcf85d9b2f3 | 187 | #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 188 | ((PERIPH) == TIM8)) |
| Sergunb | 0:9dcf85d9b2f3 | 189 | |
| Sergunb | 0:9dcf85d9b2f3 | 190 | /* LIST2: TIM 1, 8, 15 16 and 17 */ |
| Sergunb | 0:9dcf85d9b2f3 | 191 | #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 192 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 193 | ((PERIPH) == TIM15)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 194 | ((PERIPH) == TIM16)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 195 | ((PERIPH) == TIM17)) |
| Sergunb | 0:9dcf85d9b2f3 | 196 | |
| Sergunb | 0:9dcf85d9b2f3 | 197 | /* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ |
| Sergunb | 0:9dcf85d9b2f3 | 198 | #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 199 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 200 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 201 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 202 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 203 | ((PERIPH) == TIM8)) |
| Sergunb | 0:9dcf85d9b2f3 | 204 | |
| Sergunb | 0:9dcf85d9b2f3 | 205 | /* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ |
| Sergunb | 0:9dcf85d9b2f3 | 206 | #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 207 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 208 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 209 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 210 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 211 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 212 | ((PERIPH) == TIM15)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 213 | ((PERIPH) == TIM16)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 214 | ((PERIPH) == TIM17)) |
| Sergunb | 0:9dcf85d9b2f3 | 215 | |
| Sergunb | 0:9dcf85d9b2f3 | 216 | /* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ |
| Sergunb | 0:9dcf85d9b2f3 | 217 | #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 218 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 219 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 220 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 221 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 222 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 223 | ((PERIPH) == TIM15)) |
| Sergunb | 0:9dcf85d9b2f3 | 224 | |
| Sergunb | 0:9dcf85d9b2f3 | 225 | /* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ |
| Sergunb | 0:9dcf85d9b2f3 | 226 | #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 227 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 228 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 229 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 230 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 231 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 232 | ((PERIPH) == TIM9) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 233 | ((PERIPH) == TIM12)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 234 | ((PERIPH) == TIM15)) |
| Sergunb | 0:9dcf85d9b2f3 | 235 | |
| Sergunb | 0:9dcf85d9b2f3 | 236 | /* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ |
| Sergunb | 0:9dcf85d9b2f3 | 237 | #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 238 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 239 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 240 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 241 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 242 | ((PERIPH) == TIM6) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 243 | ((PERIPH) == TIM7) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 244 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 245 | ((PERIPH) == TIM9) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 246 | ((PERIPH) == TIM12)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 247 | ((PERIPH) == TIM15)) |
| Sergunb | 0:9dcf85d9b2f3 | 248 | |
| Sergunb | 0:9dcf85d9b2f3 | 249 | /* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ |
| Sergunb | 0:9dcf85d9b2f3 | 250 | #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 251 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 252 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 253 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 254 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 255 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 256 | ((PERIPH) == TIM9) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 257 | ((PERIPH) == TIM10)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 258 | ((PERIPH) == TIM11)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 259 | ((PERIPH) == TIM12)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 260 | ((PERIPH) == TIM13)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 261 | ((PERIPH) == TIM14)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 262 | ((PERIPH) == TIM15)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 263 | ((PERIPH) == TIM16)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 264 | ((PERIPH) == TIM17)) |
| Sergunb | 0:9dcf85d9b2f3 | 265 | |
| Sergunb | 0:9dcf85d9b2f3 | 266 | /* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ |
| Sergunb | 0:9dcf85d9b2f3 | 267 | #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 268 | ((PERIPH) == TIM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 269 | ((PERIPH) == TIM3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 270 | ((PERIPH) == TIM4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 271 | ((PERIPH) == TIM5) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 272 | ((PERIPH) == TIM6) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 273 | ((PERIPH) == TIM7) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 274 | ((PERIPH) == TIM8) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 275 | ((PERIPH) == TIM15)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 276 | ((PERIPH) == TIM16)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 277 | ((PERIPH) == TIM17)) |
| Sergunb | 0:9dcf85d9b2f3 | 278 | |
| Sergunb | 0:9dcf85d9b2f3 | 279 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 280 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 281 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 282 | |
| Sergunb | 0:9dcf85d9b2f3 | 283 | /** @defgroup TIM_Output_Compare_and_PWM_modes |
| Sergunb | 0:9dcf85d9b2f3 | 284 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 285 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 286 | |
| Sergunb | 0:9dcf85d9b2f3 | 287 | #define TIM_OCMode_Timing ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 288 | #define TIM_OCMode_Active ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 289 | #define TIM_OCMode_Inactive ((uint16_t)0x0020) |
| Sergunb | 0:9dcf85d9b2f3 | 290 | #define TIM_OCMode_Toggle ((uint16_t)0x0030) |
| Sergunb | 0:9dcf85d9b2f3 | 291 | #define TIM_OCMode_PWM1 ((uint16_t)0x0060) |
| Sergunb | 0:9dcf85d9b2f3 | 292 | #define TIM_OCMode_PWM2 ((uint16_t)0x0070) |
| Sergunb | 0:9dcf85d9b2f3 | 293 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 294 | ((MODE) == TIM_OCMode_Active) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 295 | ((MODE) == TIM_OCMode_Inactive) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 296 | ((MODE) == TIM_OCMode_Toggle)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 297 | ((MODE) == TIM_OCMode_PWM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 298 | ((MODE) == TIM_OCMode_PWM2)) |
| Sergunb | 0:9dcf85d9b2f3 | 299 | #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 300 | ((MODE) == TIM_OCMode_Active) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 301 | ((MODE) == TIM_OCMode_Inactive) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 302 | ((MODE) == TIM_OCMode_Toggle)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 303 | ((MODE) == TIM_OCMode_PWM1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 304 | ((MODE) == TIM_OCMode_PWM2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 305 | ((MODE) == TIM_ForcedAction_Active) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 306 | ((MODE) == TIM_ForcedAction_InActive)) |
| Sergunb | 0:9dcf85d9b2f3 | 307 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 308 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 309 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 310 | |
| Sergunb | 0:9dcf85d9b2f3 | 311 | /** @defgroup TIM_One_Pulse_Mode |
| Sergunb | 0:9dcf85d9b2f3 | 312 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 313 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 314 | |
| Sergunb | 0:9dcf85d9b2f3 | 315 | #define TIM_OPMode_Single ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 316 | #define TIM_OPMode_Repetitive ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 317 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 318 | ((MODE) == TIM_OPMode_Repetitive)) |
| Sergunb | 0:9dcf85d9b2f3 | 319 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 320 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 321 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 322 | |
| Sergunb | 0:9dcf85d9b2f3 | 323 | /** @defgroup TIM_Channel |
| Sergunb | 0:9dcf85d9b2f3 | 324 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 325 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 326 | |
| Sergunb | 0:9dcf85d9b2f3 | 327 | #define TIM_Channel_1 ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 328 | #define TIM_Channel_2 ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 329 | #define TIM_Channel_3 ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 330 | #define TIM_Channel_4 ((uint16_t)0x000C) |
| Sergunb | 0:9dcf85d9b2f3 | 331 | #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 332 | ((CHANNEL) == TIM_Channel_2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 333 | ((CHANNEL) == TIM_Channel_3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 334 | ((CHANNEL) == TIM_Channel_4)) |
| Sergunb | 0:9dcf85d9b2f3 | 335 | #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 336 | ((CHANNEL) == TIM_Channel_2)) |
| Sergunb | 0:9dcf85d9b2f3 | 337 | #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 338 | ((CHANNEL) == TIM_Channel_2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 339 | ((CHANNEL) == TIM_Channel_3)) |
| Sergunb | 0:9dcf85d9b2f3 | 340 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 341 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 342 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 343 | |
| Sergunb | 0:9dcf85d9b2f3 | 344 | /** @defgroup TIM_Clock_Division_CKD |
| Sergunb | 0:9dcf85d9b2f3 | 345 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 346 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 347 | |
| Sergunb | 0:9dcf85d9b2f3 | 348 | #define TIM_CKD_DIV1 ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 349 | #define TIM_CKD_DIV2 ((uint16_t)0x0100) |
| Sergunb | 0:9dcf85d9b2f3 | 350 | #define TIM_CKD_DIV4 ((uint16_t)0x0200) |
| Sergunb | 0:9dcf85d9b2f3 | 351 | #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 352 | ((DIV) == TIM_CKD_DIV2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 353 | ((DIV) == TIM_CKD_DIV4)) |
| Sergunb | 0:9dcf85d9b2f3 | 354 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 355 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 356 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 357 | |
| Sergunb | 0:9dcf85d9b2f3 | 358 | /** @defgroup TIM_Counter_Mode |
| Sergunb | 0:9dcf85d9b2f3 | 359 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 360 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 361 | |
| Sergunb | 0:9dcf85d9b2f3 | 362 | #define TIM_CounterMode_Up ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 363 | #define TIM_CounterMode_Down ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 364 | #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) |
| Sergunb | 0:9dcf85d9b2f3 | 365 | #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 366 | #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) |
| Sergunb | 0:9dcf85d9b2f3 | 367 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 368 | ((MODE) == TIM_CounterMode_Down) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 369 | ((MODE) == TIM_CounterMode_CenterAligned1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 370 | ((MODE) == TIM_CounterMode_CenterAligned2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 371 | ((MODE) == TIM_CounterMode_CenterAligned3)) |
| Sergunb | 0:9dcf85d9b2f3 | 372 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 373 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 374 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 375 | |
| Sergunb | 0:9dcf85d9b2f3 | 376 | /** @defgroup TIM_Output_Compare_Polarity |
| Sergunb | 0:9dcf85d9b2f3 | 377 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 378 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 379 | |
| Sergunb | 0:9dcf85d9b2f3 | 380 | #define TIM_OCPolarity_High ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 381 | #define TIM_OCPolarity_Low ((uint16_t)0x0002) |
| Sergunb | 0:9dcf85d9b2f3 | 382 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 383 | ((POLARITY) == TIM_OCPolarity_Low)) |
| Sergunb | 0:9dcf85d9b2f3 | 384 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 385 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 386 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 387 | |
| Sergunb | 0:9dcf85d9b2f3 | 388 | /** @defgroup TIM_Output_Compare_N_Polarity |
| Sergunb | 0:9dcf85d9b2f3 | 389 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 390 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 391 | |
| Sergunb | 0:9dcf85d9b2f3 | 392 | #define TIM_OCNPolarity_High ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 393 | #define TIM_OCNPolarity_Low ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 394 | #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 395 | ((POLARITY) == TIM_OCNPolarity_Low)) |
| Sergunb | 0:9dcf85d9b2f3 | 396 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 397 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 398 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 399 | |
| Sergunb | 0:9dcf85d9b2f3 | 400 | /** @defgroup TIM_Output_Compare_state |
| Sergunb | 0:9dcf85d9b2f3 | 401 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 402 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 403 | |
| Sergunb | 0:9dcf85d9b2f3 | 404 | #define TIM_OutputState_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 405 | #define TIM_OutputState_Enable ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 406 | #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 407 | ((STATE) == TIM_OutputState_Enable)) |
| Sergunb | 0:9dcf85d9b2f3 | 408 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 409 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 410 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 411 | |
| Sergunb | 0:9dcf85d9b2f3 | 412 | /** @defgroup TIM_Output_Compare_N_state |
| Sergunb | 0:9dcf85d9b2f3 | 413 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 414 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 415 | |
| Sergunb | 0:9dcf85d9b2f3 | 416 | #define TIM_OutputNState_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 417 | #define TIM_OutputNState_Enable ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 418 | #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 419 | ((STATE) == TIM_OutputNState_Enable)) |
| Sergunb | 0:9dcf85d9b2f3 | 420 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 421 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 422 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 423 | |
| Sergunb | 0:9dcf85d9b2f3 | 424 | /** @defgroup TIM_Capture_Compare_state |
| Sergunb | 0:9dcf85d9b2f3 | 425 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 426 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 427 | |
| Sergunb | 0:9dcf85d9b2f3 | 428 | #define TIM_CCx_Enable ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 429 | #define TIM_CCx_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 430 | #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 431 | ((CCX) == TIM_CCx_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 432 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 433 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 434 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 435 | |
| Sergunb | 0:9dcf85d9b2f3 | 436 | /** @defgroup TIM_Capture_Compare_N_state |
| Sergunb | 0:9dcf85d9b2f3 | 437 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 438 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 439 | |
| Sergunb | 0:9dcf85d9b2f3 | 440 | #define TIM_CCxN_Enable ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 441 | #define TIM_CCxN_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 442 | #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 443 | ((CCXN) == TIM_CCxN_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 444 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 445 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 446 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 447 | |
| Sergunb | 0:9dcf85d9b2f3 | 448 | /** @defgroup Break_Input_enable_disable |
| Sergunb | 0:9dcf85d9b2f3 | 449 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 450 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 451 | |
| Sergunb | 0:9dcf85d9b2f3 | 452 | #define TIM_Break_Enable ((uint16_t)0x1000) |
| Sergunb | 0:9dcf85d9b2f3 | 453 | #define TIM_Break_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 454 | #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 455 | ((STATE) == TIM_Break_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 456 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 457 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 458 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 459 | |
| Sergunb | 0:9dcf85d9b2f3 | 460 | /** @defgroup Break_Polarity |
| Sergunb | 0:9dcf85d9b2f3 | 461 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 462 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 463 | |
| Sergunb | 0:9dcf85d9b2f3 | 464 | #define TIM_BreakPolarity_Low ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 465 | #define TIM_BreakPolarity_High ((uint16_t)0x2000) |
| Sergunb | 0:9dcf85d9b2f3 | 466 | #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 467 | ((POLARITY) == TIM_BreakPolarity_High)) |
| Sergunb | 0:9dcf85d9b2f3 | 468 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 469 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 470 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 471 | |
| Sergunb | 0:9dcf85d9b2f3 | 472 | /** @defgroup TIM_AOE_Bit_Set_Reset |
| Sergunb | 0:9dcf85d9b2f3 | 473 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 474 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 475 | |
| Sergunb | 0:9dcf85d9b2f3 | 476 | #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) |
| Sergunb | 0:9dcf85d9b2f3 | 477 | #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 478 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 479 | ((STATE) == TIM_AutomaticOutput_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 480 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 481 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 482 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 483 | |
| Sergunb | 0:9dcf85d9b2f3 | 484 | /** @defgroup Lock_level |
| Sergunb | 0:9dcf85d9b2f3 | 485 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 486 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 487 | |
| Sergunb | 0:9dcf85d9b2f3 | 488 | #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 489 | #define TIM_LOCKLevel_1 ((uint16_t)0x0100) |
| Sergunb | 0:9dcf85d9b2f3 | 490 | #define TIM_LOCKLevel_2 ((uint16_t)0x0200) |
| Sergunb | 0:9dcf85d9b2f3 | 491 | #define TIM_LOCKLevel_3 ((uint16_t)0x0300) |
| Sergunb | 0:9dcf85d9b2f3 | 492 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 493 | ((LEVEL) == TIM_LOCKLevel_1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 494 | ((LEVEL) == TIM_LOCKLevel_2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 495 | ((LEVEL) == TIM_LOCKLevel_3)) |
| Sergunb | 0:9dcf85d9b2f3 | 496 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 497 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 498 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 499 | |
| Sergunb | 0:9dcf85d9b2f3 | 500 | /** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state |
| Sergunb | 0:9dcf85d9b2f3 | 501 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 502 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 503 | |
| Sergunb | 0:9dcf85d9b2f3 | 504 | #define TIM_OSSIState_Enable ((uint16_t)0x0400) |
| Sergunb | 0:9dcf85d9b2f3 | 505 | #define TIM_OSSIState_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 506 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 507 | ((STATE) == TIM_OSSIState_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 508 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 509 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 510 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 511 | |
| Sergunb | 0:9dcf85d9b2f3 | 512 | /** @defgroup OSSR_Off_State_Selection_for_Run_mode_state |
| Sergunb | 0:9dcf85d9b2f3 | 513 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 514 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 515 | |
| Sergunb | 0:9dcf85d9b2f3 | 516 | #define TIM_OSSRState_Enable ((uint16_t)0x0800) |
| Sergunb | 0:9dcf85d9b2f3 | 517 | #define TIM_OSSRState_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 518 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 519 | ((STATE) == TIM_OSSRState_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 520 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 521 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 522 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 523 | |
| Sergunb | 0:9dcf85d9b2f3 | 524 | /** @defgroup TIM_Output_Compare_Idle_State |
| Sergunb | 0:9dcf85d9b2f3 | 525 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 526 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 527 | |
| Sergunb | 0:9dcf85d9b2f3 | 528 | #define TIM_OCIdleState_Set ((uint16_t)0x0100) |
| Sergunb | 0:9dcf85d9b2f3 | 529 | #define TIM_OCIdleState_Reset ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 530 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 531 | ((STATE) == TIM_OCIdleState_Reset)) |
| Sergunb | 0:9dcf85d9b2f3 | 532 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 533 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 534 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 535 | |
| Sergunb | 0:9dcf85d9b2f3 | 536 | /** @defgroup TIM_Output_Compare_N_Idle_State |
| Sergunb | 0:9dcf85d9b2f3 | 537 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 538 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 539 | |
| Sergunb | 0:9dcf85d9b2f3 | 540 | #define TIM_OCNIdleState_Set ((uint16_t)0x0200) |
| Sergunb | 0:9dcf85d9b2f3 | 541 | #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 542 | #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 543 | ((STATE) == TIM_OCNIdleState_Reset)) |
| Sergunb | 0:9dcf85d9b2f3 | 544 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 545 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 546 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 547 | |
| Sergunb | 0:9dcf85d9b2f3 | 548 | /** @defgroup TIM_Input_Capture_Polarity |
| Sergunb | 0:9dcf85d9b2f3 | 549 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 550 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 551 | |
| Sergunb | 0:9dcf85d9b2f3 | 552 | #define TIM_ICPolarity_Rising ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 553 | #define TIM_ICPolarity_Falling ((uint16_t)0x0002) |
| Sergunb | 0:9dcf85d9b2f3 | 554 | #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) |
| Sergunb | 0:9dcf85d9b2f3 | 555 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 556 | ((POLARITY) == TIM_ICPolarity_Falling)) |
| Sergunb | 0:9dcf85d9b2f3 | 557 | #define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 558 | ((POLARITY) == TIM_ICPolarity_Falling)|| \ |
| Sergunb | 0:9dcf85d9b2f3 | 559 | ((POLARITY) == TIM_ICPolarity_BothEdge)) |
| Sergunb | 0:9dcf85d9b2f3 | 560 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 561 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 562 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 563 | |
| Sergunb | 0:9dcf85d9b2f3 | 564 | /** @defgroup TIM_Input_Capture_Selection |
| Sergunb | 0:9dcf85d9b2f3 | 565 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 566 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 567 | |
| Sergunb | 0:9dcf85d9b2f3 | 568 | #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
| Sergunb | 0:9dcf85d9b2f3 | 569 | connected to IC1, IC2, IC3 or IC4, respectively */ |
| Sergunb | 0:9dcf85d9b2f3 | 570 | #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
| Sergunb | 0:9dcf85d9b2f3 | 571 | connected to IC2, IC1, IC4 or IC3, respectively. */ |
| Sergunb | 0:9dcf85d9b2f3 | 572 | #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ |
| Sergunb | 0:9dcf85d9b2f3 | 573 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 574 | ((SELECTION) == TIM_ICSelection_IndirectTI) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 575 | ((SELECTION) == TIM_ICSelection_TRC)) |
| Sergunb | 0:9dcf85d9b2f3 | 576 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 577 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 578 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 579 | |
| Sergunb | 0:9dcf85d9b2f3 | 580 | /** @defgroup TIM_Input_Capture_Prescaler |
| Sergunb | 0:9dcf85d9b2f3 | 581 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 582 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 583 | |
| Sergunb | 0:9dcf85d9b2f3 | 584 | #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ |
| Sergunb | 0:9dcf85d9b2f3 | 585 | #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ |
| Sergunb | 0:9dcf85d9b2f3 | 586 | #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ |
| Sergunb | 0:9dcf85d9b2f3 | 587 | #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ |
| Sergunb | 0:9dcf85d9b2f3 | 588 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 589 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 590 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 591 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
| Sergunb | 0:9dcf85d9b2f3 | 592 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 593 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 594 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 595 | |
| Sergunb | 0:9dcf85d9b2f3 | 596 | /** @defgroup TIM_interrupt_sources |
| Sergunb | 0:9dcf85d9b2f3 | 597 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 598 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 599 | |
| Sergunb | 0:9dcf85d9b2f3 | 600 | #define TIM_IT_Update ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 601 | #define TIM_IT_CC1 ((uint16_t)0x0002) |
| Sergunb | 0:9dcf85d9b2f3 | 602 | #define TIM_IT_CC2 ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 603 | #define TIM_IT_CC3 ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 604 | #define TIM_IT_CC4 ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 605 | #define TIM_IT_COM ((uint16_t)0x0020) |
| Sergunb | 0:9dcf85d9b2f3 | 606 | #define TIM_IT_Trigger ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 607 | #define TIM_IT_Break ((uint16_t)0x0080) |
| Sergunb | 0:9dcf85d9b2f3 | 608 | #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) |
| Sergunb | 0:9dcf85d9b2f3 | 609 | |
| Sergunb | 0:9dcf85d9b2f3 | 610 | #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 611 | ((IT) == TIM_IT_CC1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 612 | ((IT) == TIM_IT_CC2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 613 | ((IT) == TIM_IT_CC3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 614 | ((IT) == TIM_IT_CC4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 615 | ((IT) == TIM_IT_COM) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 616 | ((IT) == TIM_IT_Trigger) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 617 | ((IT) == TIM_IT_Break)) |
| Sergunb | 0:9dcf85d9b2f3 | 618 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 619 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 620 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 621 | |
| Sergunb | 0:9dcf85d9b2f3 | 622 | /** @defgroup TIM_DMA_Base_address |
| Sergunb | 0:9dcf85d9b2f3 | 623 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 624 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 625 | |
| Sergunb | 0:9dcf85d9b2f3 | 626 | #define TIM_DMABase_CR1 ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 627 | #define TIM_DMABase_CR2 ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 628 | #define TIM_DMABase_SMCR ((uint16_t)0x0002) |
| Sergunb | 0:9dcf85d9b2f3 | 629 | #define TIM_DMABase_DIER ((uint16_t)0x0003) |
| Sergunb | 0:9dcf85d9b2f3 | 630 | #define TIM_DMABase_SR ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 631 | #define TIM_DMABase_EGR ((uint16_t)0x0005) |
| Sergunb | 0:9dcf85d9b2f3 | 632 | #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) |
| Sergunb | 0:9dcf85d9b2f3 | 633 | #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) |
| Sergunb | 0:9dcf85d9b2f3 | 634 | #define TIM_DMABase_CCER ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 635 | #define TIM_DMABase_CNT ((uint16_t)0x0009) |
| Sergunb | 0:9dcf85d9b2f3 | 636 | #define TIM_DMABase_PSC ((uint16_t)0x000A) |
| Sergunb | 0:9dcf85d9b2f3 | 637 | #define TIM_DMABase_ARR ((uint16_t)0x000B) |
| Sergunb | 0:9dcf85d9b2f3 | 638 | #define TIM_DMABase_RCR ((uint16_t)0x000C) |
| Sergunb | 0:9dcf85d9b2f3 | 639 | #define TIM_DMABase_CCR1 ((uint16_t)0x000D) |
| Sergunb | 0:9dcf85d9b2f3 | 640 | #define TIM_DMABase_CCR2 ((uint16_t)0x000E) |
| Sergunb | 0:9dcf85d9b2f3 | 641 | #define TIM_DMABase_CCR3 ((uint16_t)0x000F) |
| Sergunb | 0:9dcf85d9b2f3 | 642 | #define TIM_DMABase_CCR4 ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 643 | #define TIM_DMABase_BDTR ((uint16_t)0x0011) |
| Sergunb | 0:9dcf85d9b2f3 | 644 | #define TIM_DMABase_DCR ((uint16_t)0x0012) |
| Sergunb | 0:9dcf85d9b2f3 | 645 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 646 | ((BASE) == TIM_DMABase_CR2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 647 | ((BASE) == TIM_DMABase_SMCR) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 648 | ((BASE) == TIM_DMABase_DIER) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 649 | ((BASE) == TIM_DMABase_SR) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 650 | ((BASE) == TIM_DMABase_EGR) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 651 | ((BASE) == TIM_DMABase_CCMR1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 652 | ((BASE) == TIM_DMABase_CCMR2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 653 | ((BASE) == TIM_DMABase_CCER) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 654 | ((BASE) == TIM_DMABase_CNT) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 655 | ((BASE) == TIM_DMABase_PSC) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 656 | ((BASE) == TIM_DMABase_ARR) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 657 | ((BASE) == TIM_DMABase_RCR) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 658 | ((BASE) == TIM_DMABase_CCR1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 659 | ((BASE) == TIM_DMABase_CCR2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 660 | ((BASE) == TIM_DMABase_CCR3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 661 | ((BASE) == TIM_DMABase_CCR4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 662 | ((BASE) == TIM_DMABase_BDTR) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 663 | ((BASE) == TIM_DMABase_DCR)) |
| Sergunb | 0:9dcf85d9b2f3 | 664 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 665 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 666 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 667 | |
| Sergunb | 0:9dcf85d9b2f3 | 668 | /** @defgroup TIM_DMA_Burst_Length |
| Sergunb | 0:9dcf85d9b2f3 | 669 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 670 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 671 | |
| Sergunb | 0:9dcf85d9b2f3 | 672 | #define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 673 | #define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) |
| Sergunb | 0:9dcf85d9b2f3 | 674 | #define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) |
| Sergunb | 0:9dcf85d9b2f3 | 675 | #define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) |
| Sergunb | 0:9dcf85d9b2f3 | 676 | #define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) |
| Sergunb | 0:9dcf85d9b2f3 | 677 | #define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) |
| Sergunb | 0:9dcf85d9b2f3 | 678 | #define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) |
| Sergunb | 0:9dcf85d9b2f3 | 679 | #define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) |
| Sergunb | 0:9dcf85d9b2f3 | 680 | #define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) |
| Sergunb | 0:9dcf85d9b2f3 | 681 | #define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) |
| Sergunb | 0:9dcf85d9b2f3 | 682 | #define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) |
| Sergunb | 0:9dcf85d9b2f3 | 683 | #define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) |
| Sergunb | 0:9dcf85d9b2f3 | 684 | #define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) |
| Sergunb | 0:9dcf85d9b2f3 | 685 | #define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) |
| Sergunb | 0:9dcf85d9b2f3 | 686 | #define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) |
| Sergunb | 0:9dcf85d9b2f3 | 687 | #define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) |
| Sergunb | 0:9dcf85d9b2f3 | 688 | #define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) |
| Sergunb | 0:9dcf85d9b2f3 | 689 | #define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) |
| Sergunb | 0:9dcf85d9b2f3 | 690 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 691 | ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 692 | ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 693 | ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 694 | ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 695 | ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 696 | ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 697 | ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 698 | ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 699 | ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 700 | ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 701 | ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 702 | ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 703 | ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 704 | ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 705 | ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 706 | ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 707 | ((LENGTH) == TIM_DMABurstLength_18Bytes)) |
| Sergunb | 0:9dcf85d9b2f3 | 708 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 709 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 710 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 711 | |
| Sergunb | 0:9dcf85d9b2f3 | 712 | /** @defgroup TIM_DMA_sources |
| Sergunb | 0:9dcf85d9b2f3 | 713 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 714 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 715 | |
| Sergunb | 0:9dcf85d9b2f3 | 716 | #define TIM_DMA_Update ((uint16_t)0x0100) |
| Sergunb | 0:9dcf85d9b2f3 | 717 | #define TIM_DMA_CC1 ((uint16_t)0x0200) |
| Sergunb | 0:9dcf85d9b2f3 | 718 | #define TIM_DMA_CC2 ((uint16_t)0x0400) |
| Sergunb | 0:9dcf85d9b2f3 | 719 | #define TIM_DMA_CC3 ((uint16_t)0x0800) |
| Sergunb | 0:9dcf85d9b2f3 | 720 | #define TIM_DMA_CC4 ((uint16_t)0x1000) |
| Sergunb | 0:9dcf85d9b2f3 | 721 | #define TIM_DMA_COM ((uint16_t)0x2000) |
| Sergunb | 0:9dcf85d9b2f3 | 722 | #define TIM_DMA_Trigger ((uint16_t)0x4000) |
| Sergunb | 0:9dcf85d9b2f3 | 723 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) |
| Sergunb | 0:9dcf85d9b2f3 | 724 | |
| Sergunb | 0:9dcf85d9b2f3 | 725 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 726 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 727 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 728 | |
| Sergunb | 0:9dcf85d9b2f3 | 729 | /** @defgroup TIM_External_Trigger_Prescaler |
| Sergunb | 0:9dcf85d9b2f3 | 730 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 731 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 732 | |
| Sergunb | 0:9dcf85d9b2f3 | 733 | #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 734 | #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) |
| Sergunb | 0:9dcf85d9b2f3 | 735 | #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) |
| Sergunb | 0:9dcf85d9b2f3 | 736 | #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) |
| Sergunb | 0:9dcf85d9b2f3 | 737 | #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 738 | ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 739 | ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 740 | ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) |
| Sergunb | 0:9dcf85d9b2f3 | 741 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 742 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 743 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 744 | |
| Sergunb | 0:9dcf85d9b2f3 | 745 | /** @defgroup TIM_Internal_Trigger_Selection |
| Sergunb | 0:9dcf85d9b2f3 | 746 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 747 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 748 | |
| Sergunb | 0:9dcf85d9b2f3 | 749 | #define TIM_TS_ITR0 ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 750 | #define TIM_TS_ITR1 ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 751 | #define TIM_TS_ITR2 ((uint16_t)0x0020) |
| Sergunb | 0:9dcf85d9b2f3 | 752 | #define TIM_TS_ITR3 ((uint16_t)0x0030) |
| Sergunb | 0:9dcf85d9b2f3 | 753 | #define TIM_TS_TI1F_ED ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 754 | #define TIM_TS_TI1FP1 ((uint16_t)0x0050) |
| Sergunb | 0:9dcf85d9b2f3 | 755 | #define TIM_TS_TI2FP2 ((uint16_t)0x0060) |
| Sergunb | 0:9dcf85d9b2f3 | 756 | #define TIM_TS_ETRF ((uint16_t)0x0070) |
| Sergunb | 0:9dcf85d9b2f3 | 757 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 758 | ((SELECTION) == TIM_TS_ITR1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 759 | ((SELECTION) == TIM_TS_ITR2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 760 | ((SELECTION) == TIM_TS_ITR3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 761 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 762 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 763 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 764 | ((SELECTION) == TIM_TS_ETRF)) |
| Sergunb | 0:9dcf85d9b2f3 | 765 | #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 766 | ((SELECTION) == TIM_TS_ITR1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 767 | ((SELECTION) == TIM_TS_ITR2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 768 | ((SELECTION) == TIM_TS_ITR3)) |
| Sergunb | 0:9dcf85d9b2f3 | 769 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 770 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 771 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 772 | |
| Sergunb | 0:9dcf85d9b2f3 | 773 | /** @defgroup TIM_TIx_External_Clock_Source |
| Sergunb | 0:9dcf85d9b2f3 | 774 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 775 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 776 | |
| Sergunb | 0:9dcf85d9b2f3 | 777 | #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) |
| Sergunb | 0:9dcf85d9b2f3 | 778 | #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) |
| Sergunb | 0:9dcf85d9b2f3 | 779 | #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 780 | #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 781 | ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 782 | ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) |
| Sergunb | 0:9dcf85d9b2f3 | 783 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 784 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 785 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 786 | |
| Sergunb | 0:9dcf85d9b2f3 | 787 | /** @defgroup TIM_External_Trigger_Polarity |
| Sergunb | 0:9dcf85d9b2f3 | 788 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 789 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 790 | #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) |
| Sergunb | 0:9dcf85d9b2f3 | 791 | #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 792 | #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 793 | ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) |
| Sergunb | 0:9dcf85d9b2f3 | 794 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 795 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 796 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 797 | |
| Sergunb | 0:9dcf85d9b2f3 | 798 | /** @defgroup TIM_Prescaler_Reload_Mode |
| Sergunb | 0:9dcf85d9b2f3 | 799 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 800 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 801 | |
| Sergunb | 0:9dcf85d9b2f3 | 802 | #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 803 | #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 804 | #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 805 | ((RELOAD) == TIM_PSCReloadMode_Immediate)) |
| Sergunb | 0:9dcf85d9b2f3 | 806 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 807 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 808 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 809 | |
| Sergunb | 0:9dcf85d9b2f3 | 810 | /** @defgroup TIM_Forced_Action |
| Sergunb | 0:9dcf85d9b2f3 | 811 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 812 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 813 | |
| Sergunb | 0:9dcf85d9b2f3 | 814 | #define TIM_ForcedAction_Active ((uint16_t)0x0050) |
| Sergunb | 0:9dcf85d9b2f3 | 815 | #define TIM_ForcedAction_InActive ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 816 | #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 817 | ((ACTION) == TIM_ForcedAction_InActive)) |
| Sergunb | 0:9dcf85d9b2f3 | 818 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 819 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 820 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 821 | |
| Sergunb | 0:9dcf85d9b2f3 | 822 | /** @defgroup TIM_Encoder_Mode |
| Sergunb | 0:9dcf85d9b2f3 | 823 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 824 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 825 | |
| Sergunb | 0:9dcf85d9b2f3 | 826 | #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 827 | #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) |
| Sergunb | 0:9dcf85d9b2f3 | 828 | #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) |
| Sergunb | 0:9dcf85d9b2f3 | 829 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 830 | ((MODE) == TIM_EncoderMode_TI2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 831 | ((MODE) == TIM_EncoderMode_TI12)) |
| Sergunb | 0:9dcf85d9b2f3 | 832 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 833 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 834 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 835 | |
| Sergunb | 0:9dcf85d9b2f3 | 836 | |
| Sergunb | 0:9dcf85d9b2f3 | 837 | /** @defgroup TIM_Event_Source |
| Sergunb | 0:9dcf85d9b2f3 | 838 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 839 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 840 | |
| Sergunb | 0:9dcf85d9b2f3 | 841 | #define TIM_EventSource_Update ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 842 | #define TIM_EventSource_CC1 ((uint16_t)0x0002) |
| Sergunb | 0:9dcf85d9b2f3 | 843 | #define TIM_EventSource_CC2 ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 844 | #define TIM_EventSource_CC3 ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 845 | #define TIM_EventSource_CC4 ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 846 | #define TIM_EventSource_COM ((uint16_t)0x0020) |
| Sergunb | 0:9dcf85d9b2f3 | 847 | #define TIM_EventSource_Trigger ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 848 | #define TIM_EventSource_Break ((uint16_t)0x0080) |
| Sergunb | 0:9dcf85d9b2f3 | 849 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) |
| Sergunb | 0:9dcf85d9b2f3 | 850 | |
| Sergunb | 0:9dcf85d9b2f3 | 851 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 852 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 853 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 854 | |
| Sergunb | 0:9dcf85d9b2f3 | 855 | /** @defgroup TIM_Update_Source |
| Sergunb | 0:9dcf85d9b2f3 | 856 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 857 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 858 | |
| Sergunb | 0:9dcf85d9b2f3 | 859 | #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow |
| Sergunb | 0:9dcf85d9b2f3 | 860 | or the setting of UG bit, or an update generation |
| Sergunb | 0:9dcf85d9b2f3 | 861 | through the slave mode controller. */ |
| Sergunb | 0:9dcf85d9b2f3 | 862 | #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ |
| Sergunb | 0:9dcf85d9b2f3 | 863 | #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 864 | ((SOURCE) == TIM_UpdateSource_Regular)) |
| Sergunb | 0:9dcf85d9b2f3 | 865 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 866 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 867 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 868 | |
| Sergunb | 0:9dcf85d9b2f3 | 869 | /** @defgroup TIM_Ouput_Compare_Preload_State |
| Sergunb | 0:9dcf85d9b2f3 | 870 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 871 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 872 | |
| Sergunb | 0:9dcf85d9b2f3 | 873 | #define TIM_OCPreload_Enable ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 874 | #define TIM_OCPreload_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 875 | #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 876 | ((STATE) == TIM_OCPreload_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 877 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 878 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 879 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 880 | |
| Sergunb | 0:9dcf85d9b2f3 | 881 | /** @defgroup TIM_Ouput_Compare_Fast_State |
| Sergunb | 0:9dcf85d9b2f3 | 882 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 883 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 884 | |
| Sergunb | 0:9dcf85d9b2f3 | 885 | #define TIM_OCFast_Enable ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 886 | #define TIM_OCFast_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 887 | #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 888 | ((STATE) == TIM_OCFast_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 889 | |
| Sergunb | 0:9dcf85d9b2f3 | 890 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 891 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 892 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 893 | |
| Sergunb | 0:9dcf85d9b2f3 | 894 | /** @defgroup TIM_Ouput_Compare_Clear_State |
| Sergunb | 0:9dcf85d9b2f3 | 895 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 896 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 897 | |
| Sergunb | 0:9dcf85d9b2f3 | 898 | #define TIM_OCClear_Enable ((uint16_t)0x0080) |
| Sergunb | 0:9dcf85d9b2f3 | 899 | #define TIM_OCClear_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 900 | #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 901 | ((STATE) == TIM_OCClear_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 902 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 903 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 904 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 905 | |
| Sergunb | 0:9dcf85d9b2f3 | 906 | /** @defgroup TIM_Trigger_Output_Source |
| Sergunb | 0:9dcf85d9b2f3 | 907 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 908 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 909 | |
| Sergunb | 0:9dcf85d9b2f3 | 910 | #define TIM_TRGOSource_Reset ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 911 | #define TIM_TRGOSource_Enable ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 912 | #define TIM_TRGOSource_Update ((uint16_t)0x0020) |
| Sergunb | 0:9dcf85d9b2f3 | 913 | #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) |
| Sergunb | 0:9dcf85d9b2f3 | 914 | #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 915 | #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) |
| Sergunb | 0:9dcf85d9b2f3 | 916 | #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) |
| Sergunb | 0:9dcf85d9b2f3 | 917 | #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) |
| Sergunb | 0:9dcf85d9b2f3 | 918 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 919 | ((SOURCE) == TIM_TRGOSource_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 920 | ((SOURCE) == TIM_TRGOSource_Update) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 921 | ((SOURCE) == TIM_TRGOSource_OC1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 922 | ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 923 | ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 924 | ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 925 | ((SOURCE) == TIM_TRGOSource_OC4Ref)) |
| Sergunb | 0:9dcf85d9b2f3 | 926 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 927 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 928 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 929 | |
| Sergunb | 0:9dcf85d9b2f3 | 930 | /** @defgroup TIM_Slave_Mode |
| Sergunb | 0:9dcf85d9b2f3 | 931 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 932 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 933 | |
| Sergunb | 0:9dcf85d9b2f3 | 934 | #define TIM_SlaveMode_Reset ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 935 | #define TIM_SlaveMode_Gated ((uint16_t)0x0005) |
| Sergunb | 0:9dcf85d9b2f3 | 936 | #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) |
| Sergunb | 0:9dcf85d9b2f3 | 937 | #define TIM_SlaveMode_External1 ((uint16_t)0x0007) |
| Sergunb | 0:9dcf85d9b2f3 | 938 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 939 | ((MODE) == TIM_SlaveMode_Gated) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 940 | ((MODE) == TIM_SlaveMode_Trigger) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 941 | ((MODE) == TIM_SlaveMode_External1)) |
| Sergunb | 0:9dcf85d9b2f3 | 942 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 943 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 944 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 945 | |
| Sergunb | 0:9dcf85d9b2f3 | 946 | /** @defgroup TIM_Master_Slave_Mode |
| Sergunb | 0:9dcf85d9b2f3 | 947 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 948 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 949 | |
| Sergunb | 0:9dcf85d9b2f3 | 950 | #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) |
| Sergunb | 0:9dcf85d9b2f3 | 951 | #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) |
| Sergunb | 0:9dcf85d9b2f3 | 952 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 953 | ((STATE) == TIM_MasterSlaveMode_Disable)) |
| Sergunb | 0:9dcf85d9b2f3 | 954 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 955 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 956 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 957 | |
| Sergunb | 0:9dcf85d9b2f3 | 958 | /** @defgroup TIM_Flags |
| Sergunb | 0:9dcf85d9b2f3 | 959 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 960 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 961 | |
| Sergunb | 0:9dcf85d9b2f3 | 962 | #define TIM_FLAG_Update ((uint16_t)0x0001) |
| Sergunb | 0:9dcf85d9b2f3 | 963 | #define TIM_FLAG_CC1 ((uint16_t)0x0002) |
| Sergunb | 0:9dcf85d9b2f3 | 964 | #define TIM_FLAG_CC2 ((uint16_t)0x0004) |
| Sergunb | 0:9dcf85d9b2f3 | 965 | #define TIM_FLAG_CC3 ((uint16_t)0x0008) |
| Sergunb | 0:9dcf85d9b2f3 | 966 | #define TIM_FLAG_CC4 ((uint16_t)0x0010) |
| Sergunb | 0:9dcf85d9b2f3 | 967 | #define TIM_FLAG_COM ((uint16_t)0x0020) |
| Sergunb | 0:9dcf85d9b2f3 | 968 | #define TIM_FLAG_Trigger ((uint16_t)0x0040) |
| Sergunb | 0:9dcf85d9b2f3 | 969 | #define TIM_FLAG_Break ((uint16_t)0x0080) |
| Sergunb | 0:9dcf85d9b2f3 | 970 | #define TIM_FLAG_CC1OF ((uint16_t)0x0200) |
| Sergunb | 0:9dcf85d9b2f3 | 971 | #define TIM_FLAG_CC2OF ((uint16_t)0x0400) |
| Sergunb | 0:9dcf85d9b2f3 | 972 | #define TIM_FLAG_CC3OF ((uint16_t)0x0800) |
| Sergunb | 0:9dcf85d9b2f3 | 973 | #define TIM_FLAG_CC4OF ((uint16_t)0x1000) |
| Sergunb | 0:9dcf85d9b2f3 | 974 | #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 975 | ((FLAG) == TIM_FLAG_CC1) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 976 | ((FLAG) == TIM_FLAG_CC2) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 977 | ((FLAG) == TIM_FLAG_CC3) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 978 | ((FLAG) == TIM_FLAG_CC4) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 979 | ((FLAG) == TIM_FLAG_COM) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 980 | ((FLAG) == TIM_FLAG_Trigger) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 981 | ((FLAG) == TIM_FLAG_Break) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 982 | ((FLAG) == TIM_FLAG_CC1OF) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 983 | ((FLAG) == TIM_FLAG_CC2OF) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 984 | ((FLAG) == TIM_FLAG_CC3OF) || \ |
| Sergunb | 0:9dcf85d9b2f3 | 985 | ((FLAG) == TIM_FLAG_CC4OF)) |
| Sergunb | 0:9dcf85d9b2f3 | 986 | |
| Sergunb | 0:9dcf85d9b2f3 | 987 | |
| Sergunb | 0:9dcf85d9b2f3 | 988 | #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) |
| Sergunb | 0:9dcf85d9b2f3 | 989 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 990 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 991 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 992 | |
| Sergunb | 0:9dcf85d9b2f3 | 993 | /** @defgroup TIM_Input_Capture_Filer_Value |
| Sergunb | 0:9dcf85d9b2f3 | 994 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 995 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 996 | |
| Sergunb | 0:9dcf85d9b2f3 | 997 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
| Sergunb | 0:9dcf85d9b2f3 | 998 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 999 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 1000 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1001 | |
| Sergunb | 0:9dcf85d9b2f3 | 1002 | /** @defgroup TIM_External_Trigger_Filter |
| Sergunb | 0:9dcf85d9b2f3 | 1003 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 1004 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1005 | |
| Sergunb | 0:9dcf85d9b2f3 | 1006 | #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) |
| Sergunb | 0:9dcf85d9b2f3 | 1007 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 1008 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 1009 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1010 | |
| Sergunb | 0:9dcf85d9b2f3 | 1011 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 1012 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 1013 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1014 | |
| Sergunb | 0:9dcf85d9b2f3 | 1015 | /** @defgroup TIM_Exported_Macros |
| Sergunb | 0:9dcf85d9b2f3 | 1016 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 1017 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1018 | |
| Sergunb | 0:9dcf85d9b2f3 | 1019 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 1020 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 1021 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1022 | |
| Sergunb | 0:9dcf85d9b2f3 | 1023 | /** @defgroup TIM_Exported_Functions |
| Sergunb | 0:9dcf85d9b2f3 | 1024 | * @{ |
| Sergunb | 0:9dcf85d9b2f3 | 1025 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1026 | |
| Sergunb | 0:9dcf85d9b2f3 | 1027 | void TIM_DeInit(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1028 | void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1029 | void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1030 | void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1031 | void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1032 | void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1033 | void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1034 | void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1035 | void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1036 | void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1037 | void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1038 | void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1039 | void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); |
| Sergunb | 0:9dcf85d9b2f3 | 1040 | void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1041 | void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1042 | void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1043 | void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); |
| Sergunb | 0:9dcf85d9b2f3 | 1044 | void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); |
| Sergunb | 0:9dcf85d9b2f3 | 1045 | void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1046 | void TIM_InternalClockConfig(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1047 | void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
| Sergunb | 0:9dcf85d9b2f3 | 1048 | void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, |
| Sergunb | 0:9dcf85d9b2f3 | 1049 | uint16_t TIM_ICPolarity, uint16_t ICFilter); |
| Sergunb | 0:9dcf85d9b2f3 | 1050 | void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
| Sergunb | 0:9dcf85d9b2f3 | 1051 | uint16_t ExtTRGFilter); |
| Sergunb | 0:9dcf85d9b2f3 | 1052 | void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
| Sergunb | 0:9dcf85d9b2f3 | 1053 | uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); |
| Sergunb | 0:9dcf85d9b2f3 | 1054 | void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
| Sergunb | 0:9dcf85d9b2f3 | 1055 | uint16_t ExtTRGFilter); |
| Sergunb | 0:9dcf85d9b2f3 | 1056 | void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); |
| Sergunb | 0:9dcf85d9b2f3 | 1057 | void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); |
| Sergunb | 0:9dcf85d9b2f3 | 1058 | void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
| Sergunb | 0:9dcf85d9b2f3 | 1059 | void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, |
| Sergunb | 0:9dcf85d9b2f3 | 1060 | uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1061 | void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
| Sergunb | 0:9dcf85d9b2f3 | 1062 | void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
| Sergunb | 0:9dcf85d9b2f3 | 1063 | void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
| Sergunb | 0:9dcf85d9b2f3 | 1064 | void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
| Sergunb | 0:9dcf85d9b2f3 | 1065 | void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1066 | void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1067 | void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1068 | void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1069 | void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
| Sergunb | 0:9dcf85d9b2f3 | 1070 | void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
| Sergunb | 0:9dcf85d9b2f3 | 1071 | void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
| Sergunb | 0:9dcf85d9b2f3 | 1072 | void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
| Sergunb | 0:9dcf85d9b2f3 | 1073 | void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
| Sergunb | 0:9dcf85d9b2f3 | 1074 | void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
| Sergunb | 0:9dcf85d9b2f3 | 1075 | void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
| Sergunb | 0:9dcf85d9b2f3 | 1076 | void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
| Sergunb | 0:9dcf85d9b2f3 | 1077 | void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
| Sergunb | 0:9dcf85d9b2f3 | 1078 | void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
| Sergunb | 0:9dcf85d9b2f3 | 1079 | void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
| Sergunb | 0:9dcf85d9b2f3 | 1080 | void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
| Sergunb | 0:9dcf85d9b2f3 | 1081 | void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1082 | void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1083 | void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1084 | void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1085 | void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1086 | void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1087 | void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
| Sergunb | 0:9dcf85d9b2f3 | 1088 | void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); |
| Sergunb | 0:9dcf85d9b2f3 | 1089 | void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); |
| Sergunb | 0:9dcf85d9b2f3 | 1090 | void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); |
| Sergunb | 0:9dcf85d9b2f3 | 1091 | void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1092 | void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); |
| Sergunb | 0:9dcf85d9b2f3 | 1093 | void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); |
| Sergunb | 0:9dcf85d9b2f3 | 1094 | void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); |
| Sergunb | 0:9dcf85d9b2f3 | 1095 | void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); |
| Sergunb | 0:9dcf85d9b2f3 | 1096 | void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); |
| Sergunb | 0:9dcf85d9b2f3 | 1097 | void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); |
| Sergunb | 0:9dcf85d9b2f3 | 1098 | void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); |
| Sergunb | 0:9dcf85d9b2f3 | 1099 | void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); |
| Sergunb | 0:9dcf85d9b2f3 | 1100 | void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); |
| Sergunb | 0:9dcf85d9b2f3 | 1101 | void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); |
| Sergunb | 0:9dcf85d9b2f3 | 1102 | void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); |
| Sergunb | 0:9dcf85d9b2f3 | 1103 | void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); |
| Sergunb | 0:9dcf85d9b2f3 | 1104 | void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
| Sergunb | 0:9dcf85d9b2f3 | 1105 | void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
| Sergunb | 0:9dcf85d9b2f3 | 1106 | void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
| Sergunb | 0:9dcf85d9b2f3 | 1107 | void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
| Sergunb | 0:9dcf85d9b2f3 | 1108 | void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); |
| Sergunb | 0:9dcf85d9b2f3 | 1109 | uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1110 | uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1111 | uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1112 | uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1113 | uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1114 | uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); |
| Sergunb | 0:9dcf85d9b2f3 | 1115 | FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); |
| Sergunb | 0:9dcf85d9b2f3 | 1116 | void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); |
| Sergunb | 0:9dcf85d9b2f3 | 1117 | ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); |
| Sergunb | 0:9dcf85d9b2f3 | 1118 | void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); |
| Sergunb | 0:9dcf85d9b2f3 | 1119 | |
| Sergunb | 0:9dcf85d9b2f3 | 1120 | #ifdef __cplusplus |
| Sergunb | 0:9dcf85d9b2f3 | 1121 | } |
| Sergunb | 0:9dcf85d9b2f3 | 1122 | #endif |
| Sergunb | 0:9dcf85d9b2f3 | 1123 | |
| Sergunb | 0:9dcf85d9b2f3 | 1124 | #endif /*__STM32F10x_TIM_H */ |
| Sergunb | 0:9dcf85d9b2f3 | 1125 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 1126 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 1127 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1128 | |
| Sergunb | 0:9dcf85d9b2f3 | 1129 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 1130 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 1131 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1132 | |
| Sergunb | 0:9dcf85d9b2f3 | 1133 | /** |
| Sergunb | 0:9dcf85d9b2f3 | 1134 | * @} |
| Sergunb | 0:9dcf85d9b2f3 | 1135 | */ |
| Sergunb | 0:9dcf85d9b2f3 | 1136 | |
| Sergunb | 0:9dcf85d9b2f3 | 1137 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |