Sergey Pastor
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usb_regs.h
00001 /******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** 00002 * File Name : usb_regs.h 00003 * Author : MCD Application Team 00004 * Version : V3.2.1 00005 * Date : 07/05/2010 00006 * Description : Interface prototype functions to USB cell registers 00007 ******************************************************************************** 00008 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00009 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 00010 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 00011 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 00012 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 00013 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00014 *******************************************************************************/ 00015 00016 /* Define to prevent recursive inclusion -------------------------------------*/ 00017 #ifndef __USB_REGS_H 00018 #define __USB_REGS_H 00019 00020 #ifndef STM32F10X_CL 00021 00022 /* Includes ------------------------------------------------------------------*/ 00023 /* Exported types ------------------------------------------------------------*/ 00024 typedef enum _EP_DBUF_DIR 00025 { 00026 /* double buffered endpoint direction */ 00027 EP_DBUF_ERR, 00028 EP_DBUF_OUT, 00029 EP_DBUF_IN 00030 }EP_DBUF_DIR; 00031 00032 /* endpoint buffer number */ 00033 enum EP_BUF_NUM 00034 { 00035 EP_NOBUF, 00036 EP_BUF0, 00037 EP_BUF1 00038 }; 00039 00040 /* Exported constants --------------------------------------------------------*/ 00041 #define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */ 00042 #define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */ 00043 00044 /******************************************************************************/ 00045 /* General registers */ 00046 /******************************************************************************/ 00047 00048 /* Control register */ 00049 #define CNTR ((__IO unsigned *)(RegBase + 0x40)) 00050 /* Interrupt status register */ 00051 #define ISTR ((__IO unsigned *)(RegBase + 0x44)) 00052 /* Frame number register */ 00053 #define FNR ((__IO unsigned *)(RegBase + 0x48)) 00054 /* Device address register */ 00055 #define DADDR ((__IO unsigned *)(RegBase + 0x4C)) 00056 /* Buffer Table address register */ 00057 #define BTABLE ((__IO unsigned *)(RegBase + 0x50)) 00058 /******************************************************************************/ 00059 /* Endpoint registers */ 00060 /******************************************************************************/ 00061 #define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */ 00062 00063 /* Endpoint Addresses (w/direction) */ 00064 #define EP0_OUT ((uint8_t)0x00) 00065 #define EP0_IN ((uint8_t)0x80) 00066 #define EP1_OUT ((uint8_t)0x01) 00067 #define EP1_IN ((uint8_t)0x81) 00068 #define EP2_OUT ((uint8_t)0x02) 00069 #define EP2_IN ((uint8_t)0x82) 00070 #define EP3_OUT ((uint8_t)0x03) 00071 #define EP3_IN ((uint8_t)0x83) 00072 #define EP4_OUT ((uint8_t)0x04) 00073 #define EP4_IN ((uint8_t)0x84) 00074 #define EP5_OUT ((uint8_t)0x05) 00075 #define EP5_IN ((uint8_t)0x85) 00076 #define EP6_OUT ((uint8_t)0x06) 00077 #define EP6_IN ((uint8_t)0x86) 00078 #define EP7_OUT ((uint8_t)0x07) 00079 #define EP7_IN ((uint8_t)0x87) 00080 00081 /* endpoints enumeration */ 00082 #define ENDP0 ((uint8_t)0) 00083 #define ENDP1 ((uint8_t)1) 00084 #define ENDP2 ((uint8_t)2) 00085 #define ENDP3 ((uint8_t)3) 00086 #define ENDP4 ((uint8_t)4) 00087 #define ENDP5 ((uint8_t)5) 00088 #define ENDP6 ((uint8_t)6) 00089 #define ENDP7 ((uint8_t)7) 00090 00091 /******************************************************************************/ 00092 /* ISTR interrupt events */ 00093 /******************************************************************************/ 00094 #define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ 00095 #define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ 00096 #define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ 00097 #define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ 00098 #define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ 00099 #define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ 00100 #define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ 00101 #define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ 00102 00103 00104 #define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ 00105 #define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ 00106 00107 #define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ 00108 #define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ 00109 #define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ 00110 #define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ 00111 #define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ 00112 #define CLR_RESET (~ISTR_RESET) /* clear RESET bit */ 00113 #define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ 00114 #define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ 00115 00116 /******************************************************************************/ 00117 /* CNTR control register bits definitions */ 00118 /******************************************************************************/ 00119 #define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ 00120 #define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ 00121 #define CNTR_ERRM (0x2000) /* ERRor Mask */ 00122 #define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ 00123 #define CNTR_SUSPM (0x0800) /* SUSPend Mask */ 00124 #define CNTR_RESETM (0x0400) /* RESET Mask */ 00125 #define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ 00126 #define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ 00127 00128 00129 #define CNTR_RESUME (0x0010) /* RESUME request */ 00130 #define CNTR_FSUSP (0x0008) /* Force SUSPend */ 00131 #define CNTR_LPMODE (0x0004) /* Low-power MODE */ 00132 #define CNTR_PDWN (0x0002) /* Power DoWN */ 00133 #define CNTR_FRES (0x0001) /* Force USB RESet */ 00134 00135 /******************************************************************************/ 00136 /* FNR Frame Number Register bit definitions */ 00137 /******************************************************************************/ 00138 #define FNR_RXDP (0x8000) /* status of D+ data line */ 00139 #define FNR_RXDM (0x4000) /* status of D- data line */ 00140 #define FNR_LCK (0x2000) /* LoCKed */ 00141 #define FNR_LSOF (0x1800) /* Lost SOF */ 00142 #define FNR_FN (0x07FF) /* Frame Number */ 00143 /******************************************************************************/ 00144 /* DADDR Device ADDRess bit definitions */ 00145 /******************************************************************************/ 00146 #define DADDR_EF (0x80) 00147 #define DADDR_ADD (0x7F) 00148 /******************************************************************************/ 00149 /* Endpoint register */ 00150 /******************************************************************************/ 00151 /* bit positions */ 00152 #define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ 00153 #define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ 00154 #define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ 00155 #define EP_SETUP (0x0800) /* EndPoint SETUP */ 00156 #define EP_T_FIELD (0x0600) /* EndPoint TYPE */ 00157 #define EP_KIND (0x0100) /* EndPoint KIND */ 00158 #define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ 00159 #define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ 00160 #define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ 00161 #define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ 00162 00163 /* EndPoint REGister MASK (no toggle fields) */ 00164 #define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD) 00165 00166 /* EP_TYPE[1:0] EndPoint TYPE */ 00167 #define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ 00168 #define EP_BULK (0x0000) /* EndPoint BULK */ 00169 #define EP_CONTROL (0x0200) /* EndPoint CONTROL */ 00170 #define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ 00171 #define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ 00172 #define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) 00173 00174 00175 /* EP_KIND EndPoint KIND */ 00176 #define EPKIND_MASK (~EP_KIND & EPREG_MASK) 00177 00178 /* STAT_TX[1:0] STATus for TX transfer */ 00179 #define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ 00180 #define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ 00181 #define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ 00182 #define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ 00183 #define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ 00184 #define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ 00185 #define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) 00186 00187 /* STAT_RX[1:0] STATus for RX transfer */ 00188 #define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ 00189 #define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ 00190 #define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ 00191 #define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ 00192 #define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ 00193 #define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ 00194 #define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) 00195 /* Exported macro ------------------------------------------------------------*/ 00196 /* SetCNTR */ 00197 #define _SetCNTR(wRegValue) (*CNTR = (uint16_t)wRegValue) 00198 00199 /* SetISTR */ 00200 #define _SetISTR(wRegValue) (*ISTR = (uint16_t)wRegValue) 00201 00202 /* SetDADDR */ 00203 #define _SetDADDR(wRegValue) (*DADDR = (uint16_t)wRegValue) 00204 00205 /* SetBTABLE */ 00206 #define _SetBTABLE(wRegValue)(*BTABLE = (uint16_t)(wRegValue & 0xFFF8)) 00207 00208 /* GetCNTR */ 00209 #define _GetCNTR() ((uint16_t) *CNTR) 00210 00211 /* GetISTR */ 00212 #define _GetISTR() ((uint16_t) *ISTR) 00213 00214 /* GetFNR */ 00215 #define _GetFNR() ((uint16_t) *FNR) 00216 00217 /* GetDADDR */ 00218 #define _GetDADDR() ((uint16_t) *DADDR) 00219 00220 /* GetBTABLE */ 00221 #define _GetBTABLE() ((uint16_t) *BTABLE) 00222 00223 /* SetENDPOINT */ 00224 #define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ 00225 (uint16_t)wRegValue) 00226 00227 /* GetENDPOINT */ 00228 #define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum))) 00229 00230 /******************************************************************************* 00231 * Macro Name : SetEPType 00232 * Description : sets the type in the endpoint register(bits EP_TYPE[1:0]) 00233 * Input : bEpNum: Endpoint Number. 00234 * wType 00235 * Output : None. 00236 * Return : None. 00237 *******************************************************************************/ 00238 #define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ 00239 ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType ))) 00240 00241 /******************************************************************************* 00242 * Macro Name : GetEPType 00243 * Description : gets the type in the endpoint register(bits EP_TYPE[1:0]) 00244 * Input : bEpNum: Endpoint Number. 00245 * Output : None. 00246 * Return : Endpoint Type 00247 *******************************************************************************/ 00248 #define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) 00249 00250 /******************************************************************************* 00251 * Macro Name : SetEPTxStatus 00252 * Description : sets the status for tx transfer (bits STAT_TX[1:0]). 00253 * Input : bEpNum: Endpoint Number. 00254 * wState: new state 00255 * Output : None. 00256 * Return : None. 00257 *******************************************************************************/ 00258 #define _SetEPTxStatus(bEpNum,wState) {\ 00259 register uint16_t _wRegVal; \ 00260 _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\ 00261 /* toggle first bit ? */ \ 00262 if((EPTX_DTOG1 & wState)!= 0) \ 00263 _wRegVal ^= EPTX_DTOG1; \ 00264 /* toggle second bit ? */ \ 00265 if((EPTX_DTOG2 & wState)!= 0) \ 00266 _wRegVal ^= EPTX_DTOG2; \ 00267 _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \ 00268 } /* _SetEPTxStatus */ 00269 00270 /******************************************************************************* 00271 * Macro Name : SetEPRxStatus 00272 * Description : sets the status for rx transfer (bits STAT_TX[1:0]) 00273 * Input : bEpNum: Endpoint Number. 00274 * wState: new state. 00275 * Output : None. 00276 * Return : None. 00277 *******************************************************************************/ 00278 #define _SetEPRxStatus(bEpNum,wState) {\ 00279 register uint16_t _wRegVal; \ 00280 \ 00281 _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ 00282 /* toggle first bit ? */ \ 00283 if((EPRX_DTOG1 & wState)!= 0) \ 00284 _wRegVal ^= EPRX_DTOG1; \ 00285 /* toggle second bit ? */ \ 00286 if((EPRX_DTOG2 & wState)!= 0) \ 00287 _wRegVal ^= EPRX_DTOG2; \ 00288 _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \ 00289 } /* _SetEPRxStatus */ 00290 00291 /******************************************************************************* 00292 * Macro Name : SetEPRxTxStatus 00293 * Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) 00294 * Input : bEpNum: Endpoint Number. 00295 * wStaterx: new state. 00296 * wStatetx: new state. 00297 * Output : None. 00298 * Return : None. 00299 *******************************************************************************/ 00300 #define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\ 00301 register uint32_t _wRegVal; \ 00302 \ 00303 _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\ 00304 /* toggle first bit ? */ \ 00305 if((EPRX_DTOG1 & wStaterx)!= 0) \ 00306 _wRegVal ^= EPRX_DTOG1; \ 00307 /* toggle second bit ? */ \ 00308 if((EPRX_DTOG2 & wStaterx)!= 0) \ 00309 _wRegVal ^= EPRX_DTOG2; \ 00310 /* toggle first bit ? */ \ 00311 if((EPTX_DTOG1 & wStatetx)!= 0) \ 00312 _wRegVal ^= EPTX_DTOG1; \ 00313 /* toggle second bit ? */ \ 00314 if((EPTX_DTOG2 & wStatetx)!= 0) \ 00315 _wRegVal ^= EPTX_DTOG2; \ 00316 _SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX); \ 00317 } /* _SetEPRxTxStatus */ 00318 /******************************************************************************* 00319 * Macro Name : GetEPTxStatus / GetEPRxStatus 00320 * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0] 00321 * /STAT_RX[1:0]) 00322 * Input : bEpNum: Endpoint Number. 00323 * Output : None. 00324 * Return : status . 00325 *******************************************************************************/ 00326 #define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STAT) 00327 00328 #define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STAT) 00329 00330 /******************************************************************************* 00331 * Macro Name : SetEPTxValid / SetEPRxValid 00332 * Description : sets directly the VALID tx/rx-status into the enpoint register 00333 * Input : bEpNum: Endpoint Number. 00334 * Output : None. 00335 * Return : None. 00336 *******************************************************************************/ 00337 #define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) 00338 00339 #define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) 00340 00341 /******************************************************************************* 00342 * Macro Name : GetTxStallStatus / GetRxStallStatus. 00343 * Description : checks stall condition in an endpoint. 00344 * Input : bEpNum: Endpoint Number. 00345 * Output : None. 00346 * Return : TRUE = endpoint in stall condition. 00347 *******************************************************************************/ 00348 #define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ 00349 == EP_TX_STALL) 00350 #define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ 00351 == EP_RX_STALL) 00352 00353 /******************************************************************************* 00354 * Macro Name : SetEP_KIND / ClearEP_KIND. 00355 * Description : set & clear EP_KIND bit. 00356 * Input : bEpNum: Endpoint Number. 00357 * Output : None. 00358 * Return : None. 00359 *******************************************************************************/ 00360 #define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ 00361 (EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)))) 00362 #define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ 00363 (EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK)))) 00364 00365 /******************************************************************************* 00366 * Macro Name : Set_Status_Out / Clear_Status_Out. 00367 * Description : Sets/clears directly STATUS_OUT bit in the endpoint register. 00368 * Input : bEpNum: Endpoint Number. 00369 * Output : None. 00370 * Return : None. 00371 *******************************************************************************/ 00372 #define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) 00373 #define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) 00374 00375 /******************************************************************************* 00376 * Macro Name : SetEPDoubleBuff / ClearEPDoubleBuff. 00377 * Description : Sets/clears directly EP_KIND bit in the endpoint register. 00378 * Input : bEpNum: Endpoint Number. 00379 * Output : None. 00380 * Return : None. 00381 *******************************************************************************/ 00382 #define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) 00383 #define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) 00384 00385 /******************************************************************************* 00386 * Macro Name : ClearEP_CTR_RX / ClearEP_CTR_TX. 00387 * Description : Clears bit CTR_RX / CTR_TX in the endpoint register. 00388 * Input : bEpNum: Endpoint Number. 00389 * Output : None. 00390 * Return : None. 00391 *******************************************************************************/ 00392 #define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ 00393 _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) 00394 #define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ 00395 _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) 00396 00397 /******************************************************************************* 00398 * Macro Name : ToggleDTOG_RX / ToggleDTOG_TX . 00399 * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register. 00400 * Input : bEpNum: Endpoint Number. 00401 * Output : None. 00402 * Return : None. 00403 *******************************************************************************/ 00404 #define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ 00405 EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) 00406 #define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ 00407 EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) 00408 00409 /******************************************************************************* 00410 * Macro Name : ClearDTOG_RX / ClearDTOG_TX. 00411 * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register. 00412 * Input : bEpNum: Endpoint Number. 00413 * Output : None. 00414 * Return : None. 00415 *******************************************************************************/ 00416 #define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ 00417 _ToggleDTOG_RX(bEpNum) 00418 #define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ 00419 _ToggleDTOG_TX(bEpNum) 00420 /******************************************************************************* 00421 * Macro Name : SetEPAddress. 00422 * Description : Sets address in an endpoint register. 00423 * Input : bEpNum: Endpoint Number. 00424 * bAddr: Address. 00425 * Output : None. 00426 * Return : None. 00427 *******************************************************************************/ 00428 #define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ 00429 EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr) 00430 00431 /******************************************************************************* 00432 * Macro Name : GetEPAddress. 00433 * Description : Gets address in an endpoint register. 00434 * Input : bEpNum: Endpoint Number. 00435 * Output : None. 00436 * Return : None. 00437 *******************************************************************************/ 00438 #define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) 00439 00440 #define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr)) 00441 #define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr)) 00442 #define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr)) 00443 #define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr)) 00444 00445 /******************************************************************************* 00446 * Macro Name : SetEPTxAddr / SetEPRxAddr. 00447 * Description : sets address of the tx/rx buffer. 00448 * Input : bEpNum: Endpoint Number. 00449 * wAddr: address to be set (must be word aligned). 00450 * Output : None. 00451 * Return : None. 00452 *******************************************************************************/ 00453 #define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) 00454 #define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) 00455 00456 /******************************************************************************* 00457 * Macro Name : GetEPTxAddr / GetEPRxAddr. 00458 * Description : Gets address of the tx/rx buffer. 00459 * Input : bEpNum: Endpoint Number. 00460 * Output : None. 00461 * Return : address of the buffer. 00462 *******************************************************************************/ 00463 #define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum)) 00464 #define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum)) 00465 00466 /******************************************************************************* 00467 * Macro Name : SetEPCountRxReg. 00468 * Description : Sets counter of rx buffer with no. of blocks. 00469 * Input : pdwReg: pointer to counter. 00470 * wCount: Counter. 00471 * Output : None. 00472 * Return : None. 00473 *******************************************************************************/ 00474 #define _BlocksOf32(dwReg,wCount,wNBlocks) {\ 00475 wNBlocks = wCount >> 5;\ 00476 if((wCount & 0x1f) == 0)\ 00477 wNBlocks--;\ 00478 *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\ 00479 }/* _BlocksOf32 */ 00480 00481 #define _BlocksOf2(dwReg,wCount,wNBlocks) {\ 00482 wNBlocks = wCount >> 1;\ 00483 if((wCount & 0x1) != 0)\ 00484 wNBlocks++;\ 00485 *pdwReg = (uint32_t)(wNBlocks << 10);\ 00486 }/* _BlocksOf2 */ 00487 00488 #define _SetEPCountRxReg(dwReg,wCount) {\ 00489 uint16_t wNBlocks;\ 00490 if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\ 00491 else {_BlocksOf2(dwReg,wCount,wNBlocks);}\ 00492 }/* _SetEPCountRxReg */ 00493 00494 00495 00496 #define _SetEPRxDblBuf0Count(bEpNum,wCount) {\ 00497 uint32_t *pdwReg = _pEPTxCount(bEpNum); \ 00498 _SetEPCountRxReg(pdwReg, wCount);\ 00499 } 00500 /******************************************************************************* 00501 * Macro Name : SetEPTxCount / SetEPRxCount. 00502 * Description : sets counter for the tx/rx buffer. 00503 * Input : bEpNum: endpoint number. 00504 * wCount: Counter value. 00505 * Output : None. 00506 * Return : None. 00507 *******************************************************************************/ 00508 #define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount) 00509 #define _SetEPRxCount(bEpNum,wCount) {\ 00510 uint32_t *pdwReg = _pEPRxCount(bEpNum); \ 00511 _SetEPCountRxReg(pdwReg, wCount);\ 00512 } 00513 /******************************************************************************* 00514 * Macro Name : GetEPTxCount / GetEPRxCount. 00515 * Description : gets counter of the tx buffer. 00516 * Input : bEpNum: endpoint number. 00517 * Output : None. 00518 * Return : Counter value. 00519 *******************************************************************************/ 00520 #define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff) 00521 #define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff) 00522 00523 /******************************************************************************* 00524 * Macro Name : SetEPDblBuf0Addr / SetEPDblBuf1Addr. 00525 * Description : Sets buffer 0/1 address in a double buffer endpoint. 00526 * Input : bEpNum: endpoint number. 00527 * : wBuf0Addr: buffer 0 address. 00528 * Output : None. 00529 * Return : None. 00530 *******************************************************************************/ 00531 #define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} 00532 #define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} 00533 00534 /******************************************************************************* 00535 * Macro Name : SetEPDblBuffAddr. 00536 * Description : Sets addresses in a double buffer endpoint. 00537 * Input : bEpNum: endpoint number. 00538 * : wBuf0Addr: buffer 0 address. 00539 * : wBuf1Addr = buffer 1 address. 00540 * Output : None. 00541 * Return : None. 00542 *******************************************************************************/ 00543 #define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ 00544 _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\ 00545 _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\ 00546 } /* _SetEPDblBuffAddr */ 00547 00548 /******************************************************************************* 00549 * Macro Name : GetEPDblBuf0Addr / GetEPDblBuf1Addr. 00550 * Description : Gets buffer 0/1 address of a double buffer endpoint. 00551 * Input : bEpNum: endpoint number. 00552 * Output : None. 00553 * Return : None. 00554 *******************************************************************************/ 00555 #define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) 00556 #define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) 00557 00558 /******************************************************************************* 00559 * Macro Name : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count. 00560 * Description : Gets buffer 0/1 address of a double buffer endpoint. 00561 * Input : bEpNum: endpoint number. 00562 * : bDir: endpoint dir EP_DBUF_OUT = OUT 00563 * EP_DBUF_IN = IN 00564 * : wCount: Counter value 00565 * Output : None. 00566 * Return : None. 00567 *******************************************************************************/ 00568 #define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \ 00569 if(bDir == EP_DBUF_OUT)\ 00570 /* OUT endpoint */ \ 00571 {_SetEPRxDblBuf0Count(bEpNum,wCount);} \ 00572 else if(bDir == EP_DBUF_IN)\ 00573 /* IN endpoint */ \ 00574 *_pEPTxCount(bEpNum) = (uint32_t)wCount; \ 00575 } /* SetEPDblBuf0Count*/ 00576 00577 #define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \ 00578 if(bDir == EP_DBUF_OUT)\ 00579 /* OUT endpoint */ \ 00580 {_SetEPRxCount(bEpNum,wCount);}\ 00581 else if(bDir == EP_DBUF_IN)\ 00582 /* IN endpoint */\ 00583 *_pEPRxCount(bEpNum) = (uint32_t)wCount; \ 00584 } /* SetEPDblBuf1Count */ 00585 00586 #define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\ 00587 _SetEPDblBuf0Count(bEpNum, bDir, wCount); \ 00588 _SetEPDblBuf1Count(bEpNum, bDir, wCount); \ 00589 } /* _SetEPDblBuffCount */ 00590 00591 /******************************************************************************* 00592 * Macro Name : GetEPDblBuf0Count / GetEPDblBuf1Count. 00593 * Description : Gets buffer 0/1 rx/tx counter for double buffering. 00594 * Input : bEpNum: endpoint number. 00595 * Output : None. 00596 * Return : None. 00597 *******************************************************************************/ 00598 #define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum)) 00599 #define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum)) 00600 00601 00602 /* External variables --------------------------------------------------------*/ 00603 extern __IO uint16_t wIstr; /* ISTR register last read value */ 00604 00605 /* Exported functions ------------------------------------------------------- */ 00606 void SetCNTR(uint16_t /*wRegValue*/); 00607 void SetISTR(uint16_t /*wRegValue*/); 00608 void SetDADDR(uint16_t /*wRegValue*/); 00609 void SetBTABLE(uint16_t /*wRegValue*/); 00610 void SetBTABLE(uint16_t /*wRegValue*/); 00611 uint16_t GetCNTR(void); 00612 uint16_t GetISTR(void); 00613 uint16_t GetFNR(void); 00614 uint16_t GetDADDR(void); 00615 uint16_t GetBTABLE(void); 00616 void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/); 00617 uint16_t GetENDPOINT(uint8_t /*bEpNum*/); 00618 void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/); 00619 uint16_t GetEPType(uint8_t /*bEpNum*/); 00620 void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); 00621 void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); 00622 void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir); 00623 uint16_t GetEPTxStatus(uint8_t /*bEpNum*/); 00624 uint16_t GetEPRxStatus(uint8_t /*bEpNum*/); 00625 void SetEPTxValid(uint8_t /*bEpNum*/); 00626 void SetEPRxValid(uint8_t /*bEpNum*/); 00627 uint16_t GetTxStallStatus(uint8_t /*bEpNum*/); 00628 uint16_t GetRxStallStatus(uint8_t /*bEpNum*/); 00629 void SetEP_KIND(uint8_t /*bEpNum*/); 00630 void ClearEP_KIND(uint8_t /*bEpNum*/); 00631 void Set_Status_Out(uint8_t /*bEpNum*/); 00632 void Clear_Status_Out(uint8_t /*bEpNum*/); 00633 void SetEPDoubleBuff(uint8_t /*bEpNum*/); 00634 void ClearEPDoubleBuff(uint8_t /*bEpNum*/); 00635 void ClearEP_CTR_RX(uint8_t /*bEpNum*/); 00636 void ClearEP_CTR_TX(uint8_t /*bEpNum*/); 00637 void ToggleDTOG_RX(uint8_t /*bEpNum*/); 00638 void ToggleDTOG_TX(uint8_t /*bEpNum*/); 00639 void ClearDTOG_RX(uint8_t /*bEpNum*/); 00640 void ClearDTOG_TX(uint8_t /*bEpNum*/); 00641 void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/); 00642 uint8_t GetEPAddress(uint8_t /*bEpNum*/); 00643 void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); 00644 void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); 00645 uint16_t GetEPTxAddr(uint8_t /*bEpNum*/); 00646 uint16_t GetEPRxAddr(uint8_t /*bEpNum*/); 00647 void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/); 00648 void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/); 00649 void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/); 00650 uint16_t GetEPTxCount(uint8_t /*bEpNum*/); 00651 uint16_t GetEPRxCount(uint8_t /*bEpNum*/); 00652 void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/); 00653 void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/); 00654 void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/); 00655 uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/); 00656 uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/); 00657 void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); 00658 void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); 00659 void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); 00660 uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/); 00661 uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/); 00662 EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/); 00663 void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir); 00664 uint16_t ToWord(uint8_t, uint8_t); 00665 uint16_t ByteSwap(uint16_t); 00666 00667 #endif /* STM32F10X_CL */ 00668 00669 #endif /* __USB_REGS_H */ 00670 00671 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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