usb_istr.c

00001 /******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
00002 * File Name          : usb_istr.c
00003 * Author             : MCD Application Team
00004 * Version            : V3.3.0
00005 * Date               : 21-March-2011
00006 * Description        : ISTR events interrupt service routines
00007 ********************************************************************************
00008 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00009 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
00010 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
00011 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
00012 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
00013 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00014 *******************************************************************************/
00015 
00016 /* Includes ------------------------------------------------------------------*/
00017 #include "usb_lib.h"
00018 #include "usb_prop.h"
00019 #include "usb_pwr.h"
00020 #include "usb_istr.h"
00021 
00022 /* Private typedef -----------------------------------------------------------*/
00023 /* Private define ------------------------------------------------------------*/
00024 /* Private macro -------------------------------------------------------------*/
00025 /* Private variables ---------------------------------------------------------*/
00026 __IO uint16_t wIstr;  /* ISTR register last read value */
00027 __IO uint8_t bIntPackSOF = 0;  /* SOFs received between 2 consecutive packets */
00028 
00029 /* Extern variables ----------------------------------------------------------*/
00030 /* Private function prototypes -----------------------------------------------*/
00031 /* Private functions ---------------------------------------------------------*/
00032 /* function pointers to non-control endpoints service routines */
00033 void (*pEpInt_IN[7])(void) =
00034   {
00035     EP1_IN_Callback,
00036     EP2_IN_Callback,
00037     EP3_IN_Callback,
00038     EP4_IN_Callback,
00039     EP5_IN_Callback,
00040     EP6_IN_Callback,
00041     EP7_IN_Callback,
00042   };
00043 
00044 void (*pEpInt_OUT[7])(void) =
00045   {
00046     EP1_OUT_Callback,
00047     EP2_OUT_Callback,
00048     EP3_OUT_Callback,
00049     EP4_OUT_Callback,
00050     EP5_OUT_Callback,
00051     EP6_OUT_Callback,
00052     EP7_OUT_Callback,
00053   };
00054 
00055 #ifndef STM32F10X_CL
00056 
00057 /*******************************************************************************
00058 * Function Name  : USB_Istr
00059 * Description    : STR events interrupt service routine
00060 * Input          :
00061 * Output         :
00062 * Return         :
00063 *******************************************************************************/
00064 void USB_Istr(void)
00065 {
00066 
00067   wIstr = _GetISTR();
00068 
00069 #if (IMR_MSK & ISTR_SOF)
00070   if (wIstr & ISTR_SOF & wInterrupt_Mask)
00071   {
00072     _SetISTR((uint16_t)CLR_SOF);
00073     bIntPackSOF++;
00074 
00075 #ifdef SOF_CALLBACK
00076     SOF_Callback();
00077 #endif
00078   }
00079 #endif
00080   /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/  
00081   
00082 #if (IMR_MSK & ISTR_CTR)
00083   if (wIstr & ISTR_CTR & wInterrupt_Mask)
00084   {
00085     /* servicing of the endpoint correct transfer interrupt */
00086     /* clear of the CTR flag into the sub */
00087     CTR_LP();
00088 #ifdef CTR_CALLBACK
00089     CTR_Callback();
00090 #endif
00091   }
00092 #endif
00093   /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/  
00094 #if (IMR_MSK & ISTR_RESET)
00095   if (wIstr & ISTR_RESET & wInterrupt_Mask)
00096   {
00097     _SetISTR((uint16_t)CLR_RESET);
00098     Device_Property.Reset();
00099 #ifdef RESET_CALLBACK
00100     RESET_Callback();
00101 #endif
00102   }
00103 #endif
00104   /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00105 #if (IMR_MSK & ISTR_DOVR)
00106   if (wIstr & ISTR_DOVR & wInterrupt_Mask)
00107   {
00108     _SetISTR((uint16_t)CLR_DOVR);
00109 #ifdef DOVR_CALLBACK
00110     DOVR_Callback();
00111 #endif
00112   }
00113 #endif
00114   /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00115 #if (IMR_MSK & ISTR_ERR)
00116   if (wIstr & ISTR_ERR & wInterrupt_Mask)
00117   {
00118     _SetISTR((uint16_t)CLR_ERR);
00119 #ifdef ERR_CALLBACK
00120     ERR_Callback();
00121 #endif
00122   }
00123 #endif
00124   /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00125 #if (IMR_MSK & ISTR_WKUP)
00126   if (wIstr & ISTR_WKUP & wInterrupt_Mask)
00127   {
00128     _SetISTR((uint16_t)CLR_WKUP);
00129     Resume(RESUME_EXTERNAL);
00130 #ifdef WKUP_CALLBACK
00131     WKUP_Callback();
00132 #endif
00133   }
00134 #endif
00135   /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00136 #if (IMR_MSK & ISTR_SUSP)
00137   if (wIstr & ISTR_SUSP & wInterrupt_Mask)
00138   {
00139 
00140     /* check if SUSPEND is possible */
00141     if (fSuspendEnabled)
00142     {
00143       Suspend();
00144     }
00145     else
00146     {
00147       /* if not possible then resume after xx ms */
00148       Resume(RESUME_LATER);
00149     }
00150     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
00151     _SetISTR((uint16_t)CLR_SUSP);
00152 #ifdef SUSP_CALLBACK
00153     SUSP_Callback();
00154 #endif
00155   }
00156 #endif
00157   /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00158 
00159 #if (IMR_MSK & ISTR_ESOF)
00160   if (wIstr & ISTR_ESOF & wInterrupt_Mask)
00161   {
00162     _SetISTR((uint16_t)CLR_ESOF);
00163     /* resume handling timing is made with ESOFs */
00164     Resume(RESUME_ESOF); /* request without change of the machine state */
00165 
00166 #ifdef ESOF_CALLBACK
00167     ESOF_Callback();
00168 #endif
00169   }
00170 #endif
00171 } /* USB_Istr */
00172 
00173 /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00174 #else /* STM32F10X_CL */
00175 
00176 
00177 /*******************************************************************************
00178 * Function Name  : STM32_PCD_OTG_ISR_Handler
00179 * Description    : Handles all USB Device Interrupts
00180 * Input          : None
00181 * Output         : None
00182 * Return         : status
00183 *******************************************************************************/
00184 u32 STM32_PCD_OTG_ISR_Handler (void)
00185 {
00186   USB_OTG_GINTSTS_TypeDef gintr_status;
00187   u32 retval = 0;
00188 
00189   if (USBD_FS_IsDeviceMode()) /* ensure that we are in device mode */
00190   {
00191     gintr_status.d32 = OTGD_FS_ReadCoreItr();
00192 
00193    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00194     
00195     /* If there is no interrupt pending exit the interrupt routine */
00196     if (!gintr_status.d32)
00197     {
00198       return 0;
00199     }
00200 
00201    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00202     /* Early Suspend interrupt */ 
00203 #ifdef INTR_ERLYSUSPEND
00204     if (gintr_status.b.erlysuspend)
00205     {
00206       retval |= OTGD_FS_Handle_EarlySuspend_ISR();
00207     }
00208 #endif /* INTR_ERLYSUSPEND */
00209     
00210    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00211     /* End of Periodic Frame interrupt */
00212 #ifdef INTR_EOPFRAME    
00213     if (gintr_status.b.eopframe)
00214     {
00215       retval |= OTGD_FS_Handle_EOPF_ISR();
00216     }
00217 #endif /* INTR_EOPFRAME */
00218     
00219    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00220     /* Non Periodic Tx FIFO Empty interrupt */
00221 #ifdef INTR_NPTXFEMPTY    
00222     if (gintr_status.b.nptxfempty)
00223     {
00224       retval |= OTGD_FS_Handle_NPTxFE_ISR();
00225     }
00226 #endif /* INTR_NPTXFEMPTY */
00227     
00228    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00229     /* Wakeup or RemoteWakeup interrupt */
00230 #ifdef INTR_WKUPINTR    
00231     if (gintr_status.b.wkupintr)
00232     {   
00233       retval |= OTGD_FS_Handle_Wakeup_ISR();
00234     }
00235 #endif /* INTR_WKUPINTR */   
00236     
00237    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00238     /* Suspend interrupt */
00239 #ifdef INTR_USBSUSPEND
00240     if (gintr_status.b.usbsuspend)
00241     { 
00242       /* check if SUSPEND is possible */
00243       if (fSuspendEnabled)
00244       {
00245         Suspend();
00246       }
00247       else
00248       {
00249         /* if not possible then resume after xx ms */
00250         Resume(RESUME_LATER); /* This case shouldn't happen in OTG Device mode because 
00251         there's no ESOF interrupt to increment the ResumeS.bESOFcnt in the Resume state machine */
00252       }
00253             
00254       retval |= OTGD_FS_Handle_USBSuspend_ISR();
00255     }
00256 #endif /* INTR_USBSUSPEND */
00257 
00258    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00259     /* Start of Frame interrupt */
00260 #ifdef INTR_SOFINTR    
00261     if (gintr_status.b.sofintr)
00262     {
00263       /* Update the frame number variable */
00264       bIntPackSOF++;
00265       
00266       retval |= OTGD_FS_Handle_Sof_ISR();
00267     }
00268 #endif /* INTR_SOFINTR */
00269     
00270    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00271     /* Receive FIFO Queue Status Level interrupt */
00272 #ifdef INTR_RXSTSQLVL
00273     if (gintr_status.b.rxstsqlvl)
00274     {
00275       retval |= OTGD_FS_Handle_RxStatusQueueLevel_ISR();
00276     }
00277 #endif /* INTR_RXSTSQLVL */
00278     
00279    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00280     /* Enumeration Done interrupt */
00281 #ifdef INTR_ENUMDONE
00282     if (gintr_status.b.enumdone)
00283     {
00284       retval |= OTGD_FS_Handle_EnumDone_ISR();
00285     }
00286 #endif /* INTR_ENUMDONE */
00287     
00288    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00289     /* Reset interrupt */
00290 #ifdef INTR_USBRESET
00291     if (gintr_status.b.usbreset)
00292     {
00293       retval |= OTGD_FS_Handle_UsbReset_ISR();
00294     }    
00295 #endif /* INTR_USBRESET */
00296     
00297    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
00298     /* IN Endpoint interrupt */
00299 #ifdef INTR_INEPINTR
00300     if (gintr_status.b.inepint)
00301     {
00302       retval |= OTGD_FS_Handle_InEP_ISR();
00303     }
00304 #endif /* INTR_INEPINTR */
00305     
00306    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00307     /* OUT Endpoint interrupt */
00308 #ifdef INTR_OUTEPINTR
00309     if (gintr_status.b.outepintr)
00310     {
00311       retval |= OTGD_FS_Handle_OutEP_ISR();
00312     }
00313 #endif /* INTR_OUTEPINTR */    
00314  
00315    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00316     /* Mode Mismatch interrupt */
00317 #ifdef INTR_MODEMISMATCH
00318     if (gintr_status.b.modemismatch)
00319     {
00320       retval |= OTGD_FS_Handle_ModeMismatch_ISR();
00321     }
00322 #endif /* INTR_MODEMISMATCH */  
00323 
00324    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00325     /* Global IN Endpoints NAK Effective interrupt */
00326 #ifdef INTR_GINNAKEFF
00327     if (gintr_status.b.ginnakeff)
00328     {
00329       retval |= OTGD_FS_Handle_GInNakEff_ISR();
00330     }
00331 #endif /* INTR_GINNAKEFF */  
00332 
00333    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00334     /* Global OUT Endpoints NAK effective interrupt */
00335 #ifdef INTR_GOUTNAKEFF
00336     if (gintr_status.b.goutnakeff)
00337     {
00338       retval |= OTGD_FS_Handle_GOutNakEff_ISR();
00339     }
00340 #endif /* INTR_GOUTNAKEFF */  
00341 
00342    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00343     /* Isochronous Out packet Dropped interrupt */
00344 #ifdef INTR_ISOOUTDROP
00345     if (gintr_status.b.isooutdrop)
00346     {
00347       retval |= OTGD_FS_Handle_IsoOutDrop_ISR();
00348     }
00349 #endif /* INTR_ISOOUTDROP */  
00350 
00351    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00352     /* Endpoint Mismatch error interrupt */
00353 #ifdef INTR_EPMISMATCH
00354     if (gintr_status.b.epmismatch)
00355     {
00356       retval |= OTGD_FS_Handle_EPMismatch_ISR();
00357     }
00358 #endif /* INTR_EPMISMATCH */  
00359 
00360    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00361     /* Incomplete Isochronous IN transfer error interrupt */
00362 #ifdef INTR_INCOMPLISOIN
00363     if (gintr_status.b.incomplisoin)
00364     {
00365       retval |= OTGD_FS_Handle_IncomplIsoIn_ISR();
00366     }
00367 #endif /* INTR_INCOMPLISOIN */  
00368 
00369    /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/    
00370     /* Incomplete Isochronous OUT transfer error interrupt */
00371 #ifdef INTR_INCOMPLISOOUT
00372     if (gintr_status.b.outepintr)
00373     {
00374       retval |= OTGD_FS_Handle_IncomplIsoOut_ISR();
00375     }
00376 #endif /* INTR_INCOMPLISOOUT */  
00377   
00378   }
00379   return retval;
00380 }
00381 
00382 #endif /* STM32F10X_CL */
00383 
00384 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/