system_stm32f10x.c

00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   * 
00009   * 1.  This file provides two functions and one global variable to be called from 
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings). 
00013   *                      This function is called at startup just after reset and 
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick 
00019   *                                  timer or configure other parameters.
00020   *                                     
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can 
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *        
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052 
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056 
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */  
00060   
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064 
00065 #include "stm32f10x.h"
00066 
00067 /**
00068   * @}
00069   */
00070 
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074 
00075 /**
00076   * @}
00077   */
00078 
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082 
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085    
00086    IMPORTANT NOTE:
00087    ============== 
00088    1. After each device reset the HSI is used as System clock source.
00089 
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092       
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095 
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz 
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105     
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */ 
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117 
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124 
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */ 
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
00129                                   This value must be a multiple of 0x200. */
00130 
00131 
00132 /**
00133   * @}
00134   */
00135 
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139 
00140 /**
00141   * @}
00142   */
00143 
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147 
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock          = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock          = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock          = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock          = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock          = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock          = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock          = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166 
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171 
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175 
00176 static void SetSysClock(void);
00177 
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);  
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191 
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void); 
00194 #endif /* DATA_IN_ExtSRAM */
00195 
00196 /**
00197   * @}
00198   */
00199 
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203 
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the 
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217 
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */   
00224   
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227 
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230 
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233 
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237 
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240 
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246 
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;      
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253     
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl(); 
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif 
00259 
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263 
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif 
00269 }
00270 
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *           
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.         
00280   *     
00281   * @note   - The system frequency computed by this function is not the real 
00282   *           frequency in the chip. It is calculated based on the predefined 
00283   *           constant and the selected clock source:
00284   *             
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *                                              
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *                          
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *         
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.   
00295   *    
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *                
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309 
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313 
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317     
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320   
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock  = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock  = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330 
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334       
00335 #ifndef STM32F10X_CL      
00336       pllmull = ( pllmull >> 18) + 2;
00337       
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock  = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock  = (HSE_VALUE / prediv1factor) * pllmull; 
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock  = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock  = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363       
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2; 
00371       }
00372             
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock  = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380         
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384         
00385         if (prediv1source == 0)
00386         { 
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock  = (HSE_VALUE / prediv1factor) * pllmull;          
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392           
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
00396           SystemCoreClock  = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
00397         }
00398       }
00399 #endif /* STM32F10X_CL */ 
00400       break;
00401 
00402     default:
00403       SystemCoreClock  = HSI_VALUE;
00404       break;
00405   }
00406   
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock  >>= tmp;  
00412 }
00413 
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();  
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434  
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */ 
00437 }
00438 
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */ 
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller. 
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */ 
00455 void SystemInit_ExtMemCtl(void) 
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
00458   required, then adjust the Register Addresses */
00459 
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462   
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
00464   RCC->APB2ENR = 0x000001E0;
00465   
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/  
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471   
00472   GPIOD->CRL = 0x44BB44BB;  
00473   GPIOD->CRH = 0xBBBBBBBB;
00474 
00475   GPIOE->CRL = 0xB44444BB;  
00476   GPIOE->CRH = 0xBBBBBBBB;
00477 
00478   GPIOF->CRL = 0x44BBBBBB;  
00479   GPIOF->CRH = 0xBBBB4444;
00480 
00481   GPIOG->CRL = 0x44BBBBBB;  
00482   GPIOG->CRH = 0x44444B44;
00483    
00484 /*----------------  FSMC Configuration ---------------------------------------*/  
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486   
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491 
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *         and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503   
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00505   /* Enable HSE */    
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507  
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;  
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514 
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }  
00523 
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526 
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530 
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533 
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538     {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540     }
00541     else
00542     {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544     }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547  
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550       
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553     
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556     
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
00560 
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock 
00568          configuration. User can add here some code to deal with this error */
00569   }  
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
00574   *         and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582   
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00584   /* Enable HSE */    
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586  
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;  
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593 
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }  
00602 
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608 
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
00612 #endif
00613  
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616       
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619     
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622     
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00628                             RCC_CFGR_PLLMULL6); 
00629 
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636   
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }   
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else    
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652 
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655 
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660 
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00664 
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock 
00672          configuration. User can add here some code to deal with this error */
00673   } 
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
00678   *         and PCLK1 prescalers. 
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686   
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00688   /* Enable HSE */    
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690  
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;  
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697 
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }  
00706 
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711 
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
00715  
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718       
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721     
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724     
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727     
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00731                             RCC_CFGR_PLLMULL9); 
00732 
00733     /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735         
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740   
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747     
00748 #else    
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753 
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756 
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761 
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00765 
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock 
00773          configuration. User can add here some code to deal with this error */
00774   } 
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
00779   *         and PCLK1 prescalers. 
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787   
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00789   /* Enable HSE */    
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791  
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;  
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798 
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }  
00807 
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812 
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
00816  
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819       
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822     
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825     
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830         
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835   
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842     
00843    
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00847                             RCC_CFGR_PLLMULL6); 
00848 #else    
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853 
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856 
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861 
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00865 
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock 
00873          configuration. User can add here some code to deal with this error */
00874   } 
00875 }
00876 
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
00880   *         and PCLK1 prescalers. 
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888   
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
00890   /* Enable HSE */    
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892  
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;  
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899 
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }  
00908 
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913 
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
00917  
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920       
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923     
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926 
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931         
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936   
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943     
00944    
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
00948                             RCC_CFGR_PLLMULL7); 
00949 #else     
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953 
00954 #endif /* STM32F10X_CL */
00955 
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958 
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963 
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00967 
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock 
00975          configuration. User can add here some code to deal with this error */
00976   } 
00977 }
00978 
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
00982   *         and PCLK1 prescalers. 
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990   
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
00992   /* Enable HSE */    
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994  
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;  
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001 
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }  
01010 
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015 
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
01019 
01020  
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023       
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026     
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029 
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034         
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039   
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046     
01047    
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
01051                             RCC_CFGR_PLLMULL9); 
01052 #else    
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058 
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061 
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066     
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
01070 
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock 
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082 
01083 /**
01084   * @}
01085   */
01086 
01087 /**
01088   * @}
01089   */
01090   
01091 /**
01092   * @}
01093   */    
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/