zynq7000_eth.h

00001 /**
00002  * @file zynq7000_eth.h
00003  * @brief Zynq-7000 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _ZYNQ7000_ETH_H
00030 #define _ZYNQ7000_ETH_H
00031 
00032 //Number of TX buffers
00033 #ifndef ZYNQ7000_ETH_TX_BUFFER_COUNT
00034    #define ZYNQ7000_ETH_TX_BUFFER_COUNT 16
00035 #elif (ZYNQ7000_ETH_TX_BUFFER_COUNT < 1)
00036    #error ZYNQ7000_ETH_TX_BUFFER_COUNT parameter is not valid
00037 #endif
00038 
00039 //TX buffer size
00040 #ifndef ZYNQ7000_ETH_TX_BUFFER_SIZE
00041    #define ZYNQ7000_ETH_TX_BUFFER_SIZE 1536
00042 #elif (ZYNQ7000_ETH_TX_BUFFER_SIZE != 1536)
00043    #error ZYNQ7000_ETH_TX_BUFFER_SIZE parameter is not valid
00044 #endif
00045 
00046 //Number of RX buffers
00047 #ifndef ZYNQ7000_ETH_RX_BUFFER_COUNT
00048    #define ZYNQ7000_ETH_RX_BUFFER_COUNT 16
00049 #elif (ZYNQ7000_ETH_RX_BUFFER_COUNT < 1)
00050    #error ZYNQ7000_ETH_RX_BUFFER_COUNT parameter is not valid
00051 #endif
00052 
00053 //RX buffer size
00054 #ifndef ZYNQ7000_ETH_RX_BUFFER_SIZE
00055    #define ZYNQ7000_ETH_RX_BUFFER_SIZE 1536
00056 #elif (ZYNQ7000_ETH_RX_BUFFER_SIZE != 1536)
00057    #error ZYNQ7000_ETH_RX_BUFFER_SIZE parameter is not valid
00058 #endif
00059 
00060 //Ethernet interrupt priority
00061 #ifndef ZYNQ7000_ETH_IRQ_PRIORITY
00062    #define ZYNQ7000_ETH_IRQ_PRIORITY 160
00063 #elif (ZYNQ7000_ETH_IRQ_PRIORITY < 0)
00064    #error ZYNQ7000_ETH_IRQ_PRIORITY parameter is not valid
00065 #endif
00066 
00067 //Macro for hardware access
00068 #define _HW_REG(address) *((volatile uint32_t *) (address))
00069 
00070 //XEMACPS registers
00071 #define XSLCR_LOCK             _HW_REG(XSLCR_UNLOCK_ADDR - 4)
00072 #define XSLCR_UNLOCK           _HW_REG(XSLCR_UNLOCK_ADDR)
00073 #define XSLCR_GEM0_RCLK_CTRL   _HW_REG(XSLCR_GEM0_RCLK_CTRL_ADDR)
00074 #define XSLCR_GEM0_CLK_CTRL    _HW_REG(XSLCR_GEM0_CLK_CTRL_ADDR)
00075 #define XEMACPS_NWCTRL         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCTRL_OFFSET)
00076 #define XEMACPS_NWCFG          _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWCFG_OFFSET)
00077 #define XEMACPS_NWSR           _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_NWSR_OFFSET)
00078 #define XEMACPS_DMACR          _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_DMACR_OFFSET)
00079 #define XEMACPS_TXSR           _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXSR_OFFSET)
00080 #define XEMACPS_RXQBASE        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQBASE_OFFSET)
00081 #define XEMACPS_TXQBASE        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQBASE_OFFSET)
00082 #define XEMACPS_RXSR           _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSR_OFFSET)
00083 #define XEMACPS_ISR            _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_ISR_OFFSET)
00084 #define XEMACPS_IER            _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IER_OFFSET)
00085 #define XEMACPS_IDR            _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IDR_OFFSET)
00086 #define XEMACPS_IMR            _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_IMR_OFFSET)
00087 #define XEMACPS_PHYMNTNC       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PHYMNTNC_OFFSET)
00088 #define XEMACPS_RXPAUSE        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSE_OFFSET)
00089 #define XEMACPS_TXPAUSE        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSE_OFFSET)
00090 #define XEMACPS_JUMBOMAXLEN    _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_JUMBOMAXLEN_OFFSET)
00091 #define XEMACPS_HASHL          _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHL_OFFSET)
00092 #define XEMACPS_HASHH          _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_HASHH_OFFSET)
00093 #define XEMACPS_LADDR1L        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1L_OFFSET)
00094 #define XEMACPS_LADDR1H        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR1H_OFFSET)
00095 #define XEMACPS_LADDR2L        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2L_OFFSET)
00096 #define XEMACPS_LADDR2H        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR2H_OFFSET)
00097 #define XEMACPS_LADDR3L        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3L_OFFSET)
00098 #define XEMACPS_LADDR3H        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR3H_OFFSET)
00099 #define XEMACPS_LADDR4L        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4L_OFFSET)
00100 #define XEMACPS_LADDR4H        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LADDR4H_OFFSET)
00101 #define XEMACPS_MATCH1         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH1_OFFSET)
00102 #define XEMACPS_MATCH2         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH2_OFFSET)
00103 #define XEMACPS_MATCH3         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH3_OFFSET)
00104 #define XEMACPS_MATCH4         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MATCH4_OFFSET)
00105 #define XEMACPS_STRETCH        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_STRETCH_OFFSET)
00106 #define XEMACPS_OCTTXL         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXL_OFFSET)
00107 #define XEMACPS_OCTTXH         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTTXH_OFFSET)
00108 #define XEMACPS_TXCNT          _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCNT_OFFSET)
00109 #define XEMACPS_TXBCCNT        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXBCCNT_OFFSET)
00110 #define XEMACPS_TXMCCNT        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXMCCNT_OFFSET)
00111 #define XEMACPS_TXPAUSECNT     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXPAUSECNT_OFFSET)
00112 #define XEMACPS_TX64CNT        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX64CNT_OFFSET)
00113 #define XEMACPS_TX65CNT        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX65CNT_OFFSET)
00114 #define XEMACPS_TX128CNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX128CNT_OFFSET)
00115 #define XEMACPS_TX256CNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX256CNT_OFFSET)
00116 #define XEMACPS_TX512CNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX512CNT_OFFSET)
00117 #define XEMACPS_TX1024CNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1024CNT_OFFSET)
00118 #define XEMACPS_TX1519CNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TX1519CNT_OFFSET)
00119 #define XEMACPS_TXURUNCNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXURUNCNT_OFFSET)
00120 #define XEMACPS_SNGLCOLLCNT    _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_SNGLCOLLCNT_OFFSET)
00121 #define XEMACPS_MULTICOLLCNT   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MULTICOLLCNT_OFFSET)
00122 #define XEMACPS_EXCESSCOLLCNT  _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_EXCESSCOLLCNT_OFFSET)
00123 #define XEMACPS_LATECOLLCNT    _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LATECOLLCNT_OFFSET)
00124 #define XEMACPS_TXDEFERCNT     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXDEFERCNT_OFFSET)
00125 #define XEMACPS_TXCSENSECNT    _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXCSENSECNT_OFFSET)
00126 #define XEMACPS_OCTRXL         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXL_OFFSET)
00127 #define XEMACPS_OCTRXH         _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_OCTRXH_OFFSET)
00128 #define XEMACPS_RXCNT          _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXCNT_OFFSET)
00129 #define XEMACPS_RXBROADCNT     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXBROADCNT_OFFSET)
00130 #define XEMACPS_RXMULTICNT     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXMULTICNT_OFFSET)
00131 #define XEMACPS_RXPAUSECNT     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXPAUSECNT_OFFSET)
00132 #define XEMACPS_RX64CNT        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX64CNT_OFFSET)
00133 #define XEMACPS_RX65CNT        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX65CNT_OFFSET)
00134 #define XEMACPS_RX128CNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX128CNT_OFFSET)
00135 #define XEMACPS_RX256CNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX256CNT_OFFSET)
00136 #define XEMACPS_RX512CNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX512CNT_OFFSET)
00137 #define XEMACPS_RX1024CNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1024CNT_OFFSET)
00138 #define XEMACPS_RX1519CNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RX1519CNT_OFFSET)
00139 #define XEMACPS_RXUNDRCNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUNDRCNT_OFFSET)
00140 #define XEMACPS_RXOVRCNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXOVRCNT_OFFSET)
00141 #define XEMACPS_RXJABCNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXJABCNT_OFFSET)
00142 #define XEMACPS_RXFCSCNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXFCSCNT_OFFSET)
00143 #define XEMACPS_RXLENGTHCNT    _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXLENGTHCNT_OFFSET)
00144 #define XEMACPS_RXSYMBCNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXSYMBCNT_OFFSET)
00145 #define XEMACPS_RXALIGNCNT     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXALIGNCNT_OFFSET)
00146 #define XEMACPS_RXRESERRCNT    _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXRESERRCNT_OFFSET)
00147 #define XEMACPS_RXORCNT        _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXORCNT_OFFSET)
00148 #define XEMACPS_RXIPCCNT       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXIPCCNT_OFFSET)
00149 #define XEMACPS_RXTCPCCNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXTCPCCNT_OFFSET)
00150 #define XEMACPS_RXUDPCCNT      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXUDPCCNT_OFFSET)
00151 #define XEMACPS_LAST           _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_LAST_OFFSET)
00152 #define XEMACPS_1588_SEC       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_SEC_OFFSET)
00153 #define XEMACPS_1588_NANOSEC   _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_NANOSEC_OFFSET)
00154 #define XEMACPS_1588_ADJ       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_ADJ_OFFSET)
00155 #define XEMACPS_1588_INC       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_1588_INC_OFFSET)
00156 #define XEMACPS_PTP_TXSEC      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXSEC_OFFSET)
00157 #define XEMACPS_PTP_TXNANOSEC  _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_TXNANOSEC_OFFSET)
00158 #define XEMACPS_PTP_RXSEC      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXSEC_OFFSET)
00159 #define XEMACPS_PTP_RXNANOSEC  _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTP_RXNANOSEC_OFFSET)
00160 #define XEMACPS_PTPP_TXSEC     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXSEC_OFFSET)
00161 #define XEMACPS_PTPP_TXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_TXNANOSEC_OFFSET)
00162 #define XEMACPS_PTPP_RXSEC     _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXSEC_OFFSET)
00163 #define XEMACPS_PTPP_RXNANOSEC _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_PTPP_RXNANOSEC_OFFSET)
00164 #define XEMACPS_INTQ1_STS      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_STS_OFFSET)
00165 #define XEMACPS_TXQ1BASE       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_TXQ1BASE_OFFSET)
00166 #define XEMACPS_RXQ1BASE       _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_RXQ1BASE_OFFSET)
00167 #define XEMACPS_MSBBUF_TXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_TXQBASE_OFFSET)
00168 #define XEMACPS_MSBBUF_RXQBASE _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_MSBBUF_RXQBASE_OFFSET)
00169 #define XEMACPS_INTQ1_IER      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IER_OFFSET)
00170 #define XEMACPS_INTQ1_IDR      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IDR_OFFSET)
00171 #define XEMACPS_INTQ1_IMR      _HW_REG(XPAR_XEMACPS_0_BASEADDR + XEMACPS_INTQ1_IMR_OFFSET)
00172 
00173 //SLCR_LOCK register
00174 #define XSLCR_LOCK_KEY_VALUE             0x0000767B;
00175 
00176 //SLCR_UNLOCK register
00177 #define XSLCR_UNLOCK_KEY_VALUE           0x0000DF0D;
00178 
00179 //SLCR_GEM0_RCLK_CTRL register
00180 #define XSLCR_GEM0_RCLK_CTRL_SRCSEL_MASK 0x00000010
00181 #define XSLCR_GEM0_RCLK_CTRL_CLKACT_MASK 0x00000001
00182 
00183 //SLCR_GEM0_CLK_CTRL register
00184 #define XSLCR_GEM0_CLK_CTRL_DIV1_MASK    0x03F00000
00185 #define XSLCR_GEM0_CLK_CTRL_DIV0_MASK    0x00003F00
00186 #define XSLCR_GEM0_CLK_CTRL_SRCSEL_MASK  0x00000070
00187 #define XSLCR_GEM0_CLK_CTRL_CLKACT_MASK  0x00000001
00188 
00189 //PHYMNTNC register
00190 #ifdef XEMACPS_PHYMNTNC_DATA_MASK
00191    #undef XEMACPS_PHYMNTNC_DATA_MASK
00192    #define XEMACPS_PHYMNTNC_DATA_MASK    0x0000FFFF
00193 #endif
00194 
00195 //TX buffer descriptor flags
00196 #define XEMACPS_TX_USED                  0x80000000
00197 #define XEMACPS_TX_WRAP                  0x40000000
00198 #define XEMACPS_TX_RLE_ERROR             0x20000000
00199 #define XEMACPS_TX_UNDERRUN_ERROR        0x10000000
00200 #define XEMACPS_TX_AHB_ERROR             0x08000000
00201 #define XEMACPS_TX_LATE_COL_ERROR        0x04000000
00202 #define XEMACPS_TX_CHECKSUM_ERROR        0x00700000
00203 #define XEMACPS_TX_NO_CRC                0x00010000
00204 #define XEMACPS_TX_LAST                  0x00008000
00205 #define XEMACPS_TX_LENGTH                0x00003FFF
00206 
00207 //RX buffer descriptor flags
00208 #define XEMACPS_RX_ADDRESS               0xFFFFFFFC
00209 #define XEMACPS_RX_WRAP                  0x00000002
00210 #define XEMACPS_RX_OWNERSHIP             0x00000001
00211 #define XEMACPS_RX_BROADCAST             0x80000000
00212 #define XEMACPS_RX_MULTICAST_HASH        0x40000000
00213 #define XEMACPS_RX_UNICAST_HASH          0x20000000
00214 #define XEMACPS_RX_SAR                   0x08000000
00215 #define XEMACPS_RX_SAR_MASK              0x06000000
00216 #define XEMACPS_RX_TYPE_ID               0x01000000
00217 #define XEMACPS_RX_SNAP                  0x01000000
00218 #define XEMACPS_RX_TYPE_ID_MASK          0x00C00000
00219 #define XEMACPS_RX_CHECKSUM_VALID        0x00C00000
00220 #define XEMACPS_RX_VLAN_TAG              0x00200000
00221 #define XEMACPS_RX_PRIORITY_TAG          0x00100000
00222 #define XEMACPS_RX_VLAN_PRIORITY         0x000E0000
00223 #define XEMACPS_RX_CFI                   0x00010000
00224 #define XEMACPS_RX_EOF                   0x00008000
00225 #define XEMACPS_RX_SOF                   0x00004000
00226 #define XEMACPS_RX_LENGTH_MSB            0x00002000
00227 #define XEMACPS_RX_BAD_FCS               0x00002000
00228 #define XEMACPS_RX_LENGTH                0x00001FFF
00229 
00230 
00231 /**
00232  * @brief Transmit buffer descriptor
00233  **/
00234 
00235 typedef struct
00236 {
00237    uint32_t address;
00238    uint32_t status;
00239 } Zynq7000TxBufferDesc;
00240 
00241 
00242 /**
00243  * @brief Receive buffer descriptor
00244  **/
00245 
00246 typedef struct
00247 {
00248    uint32_t address;
00249    uint32_t status;
00250 } Zynq7000RxBufferDesc;
00251 
00252 
00253 //Zynq-7000 Ethernet MAC driver
00254 extern const NicDriver zynq7000EthDriver;
00255 
00256 //Zynq-7000 Ethernet MAC related functions
00257 error_t zynq7000EthInit(NetInterface *interface);
00258 void zynq7000EthInitBufferDesc(NetInterface *interface);
00259 
00260 void zynq7000EthTick(NetInterface *interface);
00261 
00262 void zynq7000EthEnableIrq(NetInterface *interface);
00263 void zynq7000EthDisableIrq(NetInterface *interface);
00264 void zynq7000EthIrqHandler(NetInterface *interface);
00265 void zynq7000EthEventHandler(NetInterface *interface);
00266 
00267 error_t zynq7000EthSendPacket(NetInterface *interface,
00268    const NetBuffer *buffer, size_t offset);
00269 
00270 error_t zynq7000EthReceivePacket(NetInterface *interface);
00271 
00272 error_t zynq7000EthSetMulticastFilter(NetInterface *interface);
00273 error_t zynq7000EthUpdateMacConfig(NetInterface *interface);
00274 
00275 void zynq7000EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00276 uint16_t zynq7000EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00277 
00278 #endif
00279