xmc4800_eth.h

00001 /**
00002  * @file xmc4800_eth.h
00003  * @brief Infineon XMC4800 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _XMC4800_ETH_H
00030 #define _XMC4800_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef XMC4800_ETH_TX_BUFFER_COUNT
00037    #define XMC4800_ETH_TX_BUFFER_COUNT 3
00038 #elif (XMC4800_ETH_TX_BUFFER_COUNT < 1)
00039    #error XMC4800_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef XMC4800_ETH_TX_BUFFER_SIZE
00044    #define XMC4800_ETH_TX_BUFFER_SIZE 1536
00045 #elif (XMC4800_ETH_TX_BUFFER_SIZE != 1536)
00046    #error XMC4800_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef XMC4800_ETH_RX_BUFFER_COUNT
00051    #define XMC4800_ETH_RX_BUFFER_COUNT 6
00052 #elif (XMC4800_ETH_RX_BUFFER_COUNT < 1)
00053    #error XMC4800_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef XMC4800_ETH_RX_BUFFER_SIZE
00058    #define XMC4800_ETH_RX_BUFFER_SIZE 1536
00059 #elif (XMC4800_ETH_RX_BUFFER_SIZE != 1536)
00060    #error XMC4800_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Interrupt priority grouping
00064 #ifndef XMC4800_ETH_IRQ_PRIORITY_GROUPING
00065    #define XMC4800_ETH_IRQ_PRIORITY_GROUPING 1
00066 #elif (XMC4800_ETH_IRQ_PRIORITY_GROUPING < 0)
00067    #error XMC4800_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
00068 #endif
00069 
00070 //Ethernet interrupt group priority
00071 #ifndef XMC4800_ETH_IRQ_GROUP_PRIORITY
00072    #define XMC4800_ETH_IRQ_GROUP_PRIORITY 48
00073 #elif (XMC4800_ETH_IRQ_GROUP_PRIORITY < 0)
00074    #error XMC4800_ETH_IRQ_GROUP_PRIORITY parameter is not valid
00075 #endif
00076 
00077 //Ethernet interrupt subpriority
00078 #ifndef XMC4800_ETH_IRQ_SUB_PRIORITY
00079    #define XMC4800_ETH_IRQ_SUB_PRIORITY 0
00080 #elif (XMC4800_ETH_IRQ_SUB_PRIORITY < 0)
00081    #error XMC4800_ETH_IRQ_SUB_PRIORITY parameter is not valid
00082 #endif
00083 
00084 //ETH0_CON
00085 #define ETH_CON_MDIO_A     (0 << ETH_CON_MDIO_Pos)
00086 #define ETH_CON_MDIO_B     (1 << ETH_CON_MDIO_Pos)
00087 #define ETH_CON_MDIO_C     (2 << ETH_CON_MDIO_Pos)
00088 #define ETH_CON_MDIO_D     (3 << ETH_CON_MDIO_Pos)
00089 
00090 #define ETH_CON_CLK_TX_A   (0 << ETH_CON_CLK_TX_Pos)
00091 #define ETH_CON_CLK_TX_B   (1 << ETH_CON_CLK_TX_Pos)
00092 #define ETH_CON_CLK_TX_C   (2 << ETH_CON_CLK_TX_Pos)
00093 #define ETH_CON_CLK_TX_D   (3 << ETH_CON_CLK_TX_Pos)
00094 
00095 #define ETH_CON_COL_A      (0 << ETH_CON_COL_Pos)
00096 #define ETH_CON_COL_B      (1 << ETH_CON_COL_Pos)
00097 #define ETH_CON_COL_C      (2 << ETH_CON_COL_Pos)
00098 #define ETH_CON_COL_D      (3 << ETH_CON_COL_Pos)
00099 
00100 #define ETH_CON_RXER_A     (0 << ETH_CON_RXER_Pos)
00101 #define ETH_CON_RXER_B     (1 << ETH_CON_RXER_Pos)
00102 #define ETH_CON_RXER_C     (2 << ETH_CON_RXER_Pos)
00103 #define ETH_CON_RXER_D     (3 << ETH_CON_RXER_Pos)
00104 
00105 #define ETH_CON_CRS_A      (0 << ETH_CON_CRS_Pos)
00106 #define ETH_CON_CRS_B      (1 << ETH_CON_CRS_Pos)
00107 #define ETH_CON_CRS_C      (2 << ETH_CON_CRS_Pos)
00108 #define ETH_CON_CRS_D      (3 << ETH_CON_CRS_Pos)
00109 
00110 #define ETH_CON_CRS_DV_A   (0 << ETH_CON_CRS_DV_Pos)
00111 #define ETH_CON_CRS_DV_B   (1 << ETH_CON_CRS_DV_Pos)
00112 #define ETH_CON_CRS_DV_C   (2 << ETH_CON_CRS_DV_Pos)
00113 #define ETH_CON_CRS_DV_D   (3 << ETH_CON_CRS_DV_Pos)
00114 
00115 #define ETH_CON_CLK_RMII_A (0 << ETH_CON_CLK_RMII_Pos)
00116 #define ETH_CON_CLK_RMII_B (1 << ETH_CON_CLK_RMII_Pos)
00117 #define ETH_CON_CLK_RMII_C (2 << ETH_CON_CLK_RMII_Pos)
00118 #define ETH_CON_CLK_RMII_D (3 << ETH_CON_CLK_RMII_Pos)
00119 
00120 #define ETH_CON_RXD3_A     (0 << ETH_CON_RXD3_Pos)
00121 #define ETH_CON_RXD3_B     (1 << ETH_CON_RXD3_Pos)
00122 #define ETH_CON_RXD3_C     (2 << ETH_CON_RXD3_Pos)
00123 #define ETH_CON_RXD3_D     (3 << ETH_CON_RXD3_Pos)
00124 
00125 #define ETH_CON_RXD2_A     (0 << ETH_CON_RXD2_Pos)
00126 #define ETH_CON_RXD2_B     (1 << ETH_CON_RXD2_Pos)
00127 #define ETH_CON_RXD2_C     (2 << ETH_CON_RXD2_Pos)
00128 #define ETH_CON_RXD2_D     (3 << ETH_CON_RXD2_Pos)
00129 
00130 #define ETH_CON_RXD1_A     (0 << ETH_CON_RXD1_Pos)
00131 #define ETH_CON_RXD1_B     (1 << ETH_CON_RXD1_Pos)
00132 #define ETH_CON_RXD1_C     (2 << ETH_CON_RXD1_Pos)
00133 #define ETH_CON_RXD1_D     (3 << ETH_CON_RXD1_Pos)
00134 
00135 #define ETH_CON_RXD0_A     (0 << ETH_CON_RXD0_Pos)
00136 #define ETH_CON_RXD0_B     (1 << ETH_CON_RXD0_Pos)
00137 #define ETH_CON_RXD0_C     (2 << ETH_CON_RXD0_Pos)
00138 #define ETH_CON_RXD0_D     (3 << ETH_CON_RXD0_Pos)
00139 
00140 //ETH0_MAC_CONFIGURATION register
00141 #define ETH_MAC_CONFIGURATION_RESERVED15_Msk (1 << 15)
00142 
00143 //ETH0_GMII_ADDRESS register
00144 #define ETH_GMII_ADDRESS_CR_DIV42  (0 << ETH_GMII_ADDRESS_CR_Pos)
00145 #define ETH_GMII_ADDRESS_CR_DIV62  (1 << ETH_GMII_ADDRESS_CR_Pos)
00146 #define ETH_GMII_ADDRESS_CR_DIV16  (2 << ETH_GMII_ADDRESS_CR_Pos)
00147 #define ETH_GMII_ADDRESS_CR_DIV26  (3 << ETH_GMII_ADDRESS_CR_Pos)
00148 #define ETH_GMII_ADDRESS_CR_DIV102 (4 << ETH_GMII_ADDRESS_CR_Pos)
00149 #define ETH_GMII_ADDRESS_CR_DIV124 (5 << ETH_GMII_ADDRESS_CR_Pos)
00150 
00151 //ETH0_BUS_MODE register
00152 #define ETH_BUS_MODE_RPBL_1  (1 << ETH_BUS_MODE_RPBL_Pos)
00153 #define ETH_BUS_MODE_RPBL_2  (2 << ETH_BUS_MODE_RPBL_Pos)
00154 #define ETH_BUS_MODE_RPBL_4  (4 << ETH_BUS_MODE_RPBL_Pos)
00155 #define ETH_BUS_MODE_RPBL_8  (8 << ETH_BUS_MODE_RPBL_Pos)
00156 #define ETH_BUS_MODE_RPBL_16 (16 << ETH_BUS_MODE_RPBL_Pos)
00157 #define ETH_BUS_MODE_RPBL_32 (32 << ETH_BUS_MODE_RPBL_Pos)
00158 
00159 #define ETH_BUS_MODE_PR_1_1  (0 << ETH_BUS_MODE_PR_Pos)
00160 #define ETH_BUS_MODE_PR_2_1  (1 << ETH_BUS_MODE_PR_Pos)
00161 #define ETH_BUS_MODE_PR_3_1  (2 << ETH_BUS_MODE_PR_Pos)
00162 #define ETH_BUS_MODE_PR_4_1  (3 << ETH_BUS_MODE_PR_Pos)
00163 
00164 #define ETH_BUS_MODE_PBL_1   (1 << ETH_BUS_MODE_PBL_Pos)
00165 #define ETH_BUS_MODE_PBL_2   (2 << ETH_BUS_MODE_PBL_Pos)
00166 #define ETH_BUS_MODE_PBL_4   (4 << ETH_BUS_MODE_PBL_Pos)
00167 #define ETH_BUS_MODE_PBL_8   (8 << ETH_BUS_MODE_PBL_Pos)
00168 #define ETH_BUS_MODE_PBL_16  (16 << ETH_BUS_MODE_PBL_Pos)
00169 #define ETH_BUS_MODE_PBL_32  (32 << ETH_BUS_MODE_PBL_Pos)
00170 
00171 //Transmit DMA descriptor flags
00172 #define ETH_TDES0_OWN     0x80000000
00173 #define ETH_TDES0_IC      0x40000000
00174 #define ETH_TDES0_LS      0x20000000
00175 #define ETH_TDES0_FS      0x10000000
00176 #define ETH_TDES0_DC      0x08000000
00177 #define ETH_TDES0_DP      0x04000000
00178 #define ETH_TDES0_TTSE    0x02000000
00179 #define ETH_TDES0_CIC     0x00C00000
00180 #define ETH_TDES0_TER     0x00200000
00181 #define ETH_TDES0_TCH     0x00100000
00182 #define ETH_TDES0_TTSS    0x00020000
00183 #define ETH_TDES0_IHE     0x00010000
00184 #define ETH_TDES0_ES      0x00008000
00185 #define ETH_TDES0_JT      0x00004000
00186 #define ETH_TDES0_FF      0x00002000
00187 #define ETH_TDES0_IPE     0x00001000
00188 #define ETH_TDES0_LCA     0x00000800
00189 #define ETH_TDES0_NC      0x00000400
00190 #define ETH_TDES0_LCO     0x00000200
00191 #define ETH_TDES0_EC      0x00000100
00192 #define ETH_TDES0_VF      0x00000080
00193 #define ETH_TDES0_CC      0x00000078
00194 #define ETH_TDES0_ED      0x00000004
00195 #define ETH_TDES0_UF      0x00000002
00196 #define ETH_TDES0_DB      0x00000001
00197 #define ETH_TDES1_TBS2    0x1FFF0000
00198 #define ETH_TDES1_TBS1    0x00001FFF
00199 #define ETH_TDES2_TBAP1   0xFFFFFFFF
00200 #define ETH_TDES3_TBAP2   0xFFFFFFFF
00201 
00202 //Receive DMA descriptor flags
00203 #define ETH_RDES0_OWN     0x80000000
00204 #define ETH_RDES0_AFM     0x40000000
00205 #define ETH_RDES0_FL      0x3FFF0000
00206 #define ETH_RDES0_ES      0x00008000
00207 #define ETH_RDES0_DE      0x00004000
00208 #define ETH_RDES0_SAF     0x00002000
00209 #define ETH_RDES0_LE      0x00001000
00210 #define ETH_RDES0_OE      0x00000800
00211 #define ETH_RDES0_VLAN    0x00000400
00212 #define ETH_RDES0_FS      0x00000200
00213 #define ETH_RDES0_LS      0x00000100
00214 #define ETH_RDES0_IPCE_GF 0x00000080
00215 #define ETH_RDES0_LCO     0x00000040
00216 #define ETH_RDES0_FT      0x00000020
00217 #define ETH_RDES0_RWT     0x00000010
00218 #define ETH_RDES0_RE      0x00000008
00219 #define ETH_RDES0_DBE     0x00000004
00220 #define ETH_RDES0_CE      0x00000002
00221 #define ETH_RDES0_PCE     0x00000001
00222 #define ETH_RDES1_DIC     0x80000000
00223 #define ETH_RDES1_RBS2    0x1FFF0000
00224 #define ETH_RDES1_RER     0x00008000
00225 #define ETH_RDES1_RCH     0x00004000
00226 #define ETH_RDES1_RBS1    0x00001FFF
00227 #define ETH_RDES2_RBAP1   0xFFFFFFFF
00228 #define ETH_RDES3_RBAP2   0xFFFFFFFF
00229 
00230 
00231 /**
00232  * @brief Transmit DMA descriptor
00233  **/
00234 
00235 typedef struct
00236 {
00237    uint32_t tdes0;
00238    uint32_t tdes1;
00239    uint32_t tdes2;
00240    uint32_t tdes3;
00241 } Xmc4800TxDmaDesc;
00242 
00243 
00244 /**
00245  * @brief Receive DMA descriptor
00246  **/
00247 
00248 typedef struct
00249 {
00250    uint32_t rdes0;
00251    uint32_t rdes1;
00252    uint32_t rdes2;
00253    uint32_t rdes3;
00254 } Xmc4800RxDmaDesc;
00255 
00256 
00257 //XMC4800 Ethernet MAC driver
00258 extern const NicDriver xmc4800EthDriver;
00259 
00260 //XMC4800 Ethernet MAC related functions
00261 error_t xmc4800EthInit(NetInterface *interface);
00262 void xmc4800EthInitGpio(NetInterface *interface);
00263 void xmc4800EthInitDmaDesc(NetInterface *interface);
00264 
00265 void xmc4800EthTick(NetInterface *interface);
00266 
00267 void xmc4800EthEnableIrq(NetInterface *interface);
00268 void xmc4800EthDisableIrq(NetInterface *interface);
00269 void xmc4800EthEventHandler(NetInterface *interface);
00270 
00271 error_t xmc4800EthSendPacket(NetInterface *interface,
00272    const NetBuffer *buffer, size_t offset);
00273 
00274 error_t xmc4800EthReceivePacket(NetInterface *interface);
00275 
00276 error_t xmc4800EthSetMulticastFilter(NetInterface *interface);
00277 error_t xmc4800EthUpdateMacConfig(NetInterface *interface);
00278 
00279 void xmc4800EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00280 uint16_t xmc4800EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00281 
00282 uint32_t xmc4800EthCalcCrc(const void *data, size_t length);
00283 
00284 #endif
00285