upd60611.h

00001 /**
00002  * @file upd60611.h
00003  * @brief uPD60611 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _UPD60611_H
00030 #define _UPD60611_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef UPD60611_PHY_ADDR
00037    #define UPD60611_PHY_ADDR 0
00038 #elif (UPD60611_PHY_ADDR < 0 || UPD60611_PHY_ADDR > 31)
00039    #error UPD60611_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //uPD60611 registers
00043 #define UPD60611_PHY_REG_BMCR       0x00
00044 #define UPD60611_PHY_REG_BMSR       0x01
00045 #define UPD60611_PHY_REG_PHYIDR1    0x02
00046 #define UPD60611_PHY_REG_PHYIDR2    0x03
00047 #define UPD60611_PHY_REG_ANAR       0x04
00048 #define UPD60611_PHY_REG_ANLPAR     0x05
00049 #define UPD60611_PHY_REG_ANER       0x06
00050 #define UPD60611_PHY_REG_ANNPTR     0x07
00051 #define UPD60611_PHY_REG_SRR        0x10
00052 #define UPD60611_PHY_REG_MCSR       0x11
00053 #define UPD60611_PHY_REG_SMR        0x12
00054 #define UPD60611_PHY_REG_EBSR       0x13
00055 #define UPD60611_PHY_REG_BER        0x17
00056 #define UPD60611_PHY_REG_FEQMR      0x18
00057 #define UPD60611_PHY_REG_DCSR       0x19
00058 #define UPD60611_PHY_REG_DCR        0x1A
00059 #define UPD60611_PHY_REG_SCSIR      0x1B
00060 #define UPD60611_PHY_REG_ISR        0x1D
00061 #define UPD60611_PHY_REG_IER        0x1E
00062 #define UPD60611_PHY_REG_PSCSR      0x1F
00063 
00064 //BMCR register
00065 #define BMCR_RESET                 (1 << 15)
00066 #define BMCR_LOOPBACK              (1 << 14)
00067 #define BMCR_SPEED_SEL             (1 << 13)
00068 #define BMCR_AN_EN                 (1 << 12)
00069 #define BMCR_POWER_DOWN            (1 << 11)
00070 #define BMCR_ISOLATE               (1 << 10)
00071 #define BMCR_RESTART_AN            (1 << 9)
00072 #define BMCR_DUPLEX_MODE           (1 << 8)
00073 #define BMCR_COL_TEST              (1 << 7)
00074 
00075 //BMSR register
00076 #define BMSR_100BT4                (1 << 15)
00077 #define BMSR_100BTX_FD             (1 << 14)
00078 #define BMSR_100BTX                (1 << 13)
00079 #define BMSR_10BT_FD               (1 << 12)
00080 #define BMSR_10BT                  (1 << 11)
00081 #define BMSR_AN_COMPLETE           (1 << 5)
00082 #define BMSR_REMOTE_FAULT          (1 << 4)
00083 #define BMSR_AN_ABLE               (1 << 3)
00084 #define BMSR_LINK_STATUS           (1 << 2)
00085 #define BMSR_JABBER_DETECT         (1 << 1)
00086 #define BMSR_EXTENDED_CAP          (1 << 0)
00087 
00088 //ANAR register
00089 #define ANAR_NP                    (1 << 15)
00090 #define ANAR_RF                    (1 << 13)
00091 #define ANAR_PAUSE1                (1 << 11)
00092 #define ANAR_PAUSE0                (1 << 10)
00093 #define ANAR_100BT4                (1 << 9)
00094 #define ANAR_100BTX_FD             (1 << 8)
00095 #define ANAR_100BTX                (1 << 7)
00096 #define ANAR_10BT_FD               (1 << 6)
00097 #define ANAR_10BT                  (1 << 5)
00098 #define ANAR_SELECTOR4             (1 << 4)
00099 #define ANAR_SELECTOR3             (1 << 3)
00100 #define ANAR_SELECTOR2             (1 << 2)
00101 #define ANAR_SELECTOR1             (1 << 1)
00102 #define ANAR_SELECTOR0             (1 << 0)
00103 
00104 //ANLPAR register
00105 #define ANLPAR_NP                  (1 << 15)
00106 #define ANLPAR_ACK                 (1 << 14)
00107 #define ANLPAR_RF                  (1 << 13)
00108 #define ANLPAR_PAUSE               (1 << 10)
00109 #define ANLPAR_100BT4              (1 << 9)
00110 #define ANLPAR_100BTX_FD           (1 << 8)
00111 #define ANLPAR_100BTX              (1 << 7)
00112 #define ANLPAR_10BT_FD             (1 << 6)
00113 #define ANLPAR_10BT                (1 << 5)
00114 #define ANLPAR_SELECTOR4           (1 << 4)
00115 #define ANLPAR_SELECTOR3           (1 << 3)
00116 #define ANLPAR_SELECTOR2           (1 << 2)
00117 #define ANLPAR_SELECTOR1           (1 << 1)
00118 #define ANLPAR_SELECTOR0           (1 << 0)
00119 
00120 //ANER register
00121 #define ANER_PDF                   (1 << 4)
00122 #define ANER_LP_NP_ABLE            (1 << 3)
00123 #define ANER_NP_ABLE               (1 << 2)
00124 #define ANER_PAGE_RX               (1 << 1)
00125 #define ANER_LP_AN_ABLE            (1 << 0)
00126 
00127 //ANNPTR register
00128 #define ANNPTR_NP                  (1 << 15)
00129 #define ANNPTR_MP                  (1 << 13)
00130 #define ANNPTR_ACK2                (1 << 12)
00131 #define ANNPTR_TOGGLE              (1 << 11)
00132 #define ANNPTR_CODE10              (1 << 10)
00133 #define ANNPTR_CODE9               (1 << 9)
00134 #define ANNPTR_CODE8               (1 << 8)
00135 #define ANNPTR_CODE7               (1 << 7)
00136 #define ANNPTR_CODE6               (1 << 6)
00137 #define ANNPTR_CODE5               (1 << 5)
00138 #define ANNPTR_CODE4               (1 << 4)
00139 #define ANNPTR_CODE3               (1 << 3)
00140 #define ANNPTR_CODE2               (1 << 2)
00141 #define ANNPTR_CODE1               (1 << 1)
00142 #define ANNPTR_CODE0               (1 << 0)
00143 
00144 //MCSR register
00145 #define MCSR_EDPWRDOWN             (1 << 13)
00146 #define MCSR_FARLOOPBACK           (1 << 9)
00147 #define MCSR_FASTEST               (1 << 8)
00148 #define MCSR_AUTOMDIX_EN           (1 << 7)
00149 #define MCSR_MDI MODE              (1 << 6)
00150 #define MCSR_FORCE_GOOD_LINK       (1 << 2)
00151 #define MCSR_ENERGYON              (1 << 1)
00152 
00153 //SMR register
00154 #define SMR_FX_MODE                (1 << 10)
00155 #define SMR_PHY_MODE3              (1 << 8)
00156 #define SMR_PHY_MODE2              (1 << 7)
00157 #define SMR_PHY_MODE1              (1 << 6)
00158 #define SMR_PHY_MODE0              (1 << 5)
00159 #define SMR_PHY_ADD_DEV1           (1 << 4)
00160 #define SMR_PHY_ADD_DEV0           (1 << 3)
00161 #define SMR_PHY_ADD_MOD2           (1 << 2)
00162 #define SMR_PHY_ADD_MOD1           (1 << 1)
00163 #define SMR_PHY_ADD_MOD0           (1 << 0)
00164 
00165 //EBSR register
00166 #define EBSR_T_EL_BUF_OVF          (1 << 7)
00167 #define EBSR_T_EL_BUF_UDF          (1 << 6)
00168 #define EBSR_R_EL_BUF_OVF          (1 << 5)
00169 #define EBSR_R_EL_BUF_UDF          (1 << 4)
00170 
00171 //BER register
00172 #define BER_LNK_OK                 (1 << 15)
00173 #define BER_CNT_LNK_EN             (1 << 14)
00174 #define BER_CNT_TRIG2              (1 << 13)
00175 #define BER_CNT_TRIG1              (1 << 12)
00176 #define BER_CNT_TRIG0              (1 << 11)
00177 #define BER_WINDOW3                (1 << 10)
00178 #define BER_WINDOW2                (1 << 9)
00179 #define BER_WINDOW1                (1 << 8)
00180 #define BER_WINDOW0                (1 << 7)
00181 #define BER_COUNT6                 (1 << 6)
00182 #define BER_COUNT5                 (1 << 5)
00183 #define BER_COUNT4                 (1 << 4)
00184 #define BER_COUNT3                 (1 << 3)
00185 #define BER_COUNT2                 (1 << 2)
00186 #define BER_COUNT1                 (1 << 1)
00187 #define BER_COUNT0                 (1 << 0)
00188 
00189 //DCSR register
00190 #define DCSR_DIAG_INIT             (1 << 14)
00191 #define DCSR_ADC_MAX_VALUE5        (1 << 13)
00192 #define DCSR_ADC_MAX_VALUE4        (1 << 12)
00193 #define DCSR_ADC_MAX_VALUE3        (1 << 11)
00194 #define DCSR_ADC_MAX_VALUE2        (1 << 10)
00195 #define DCSR_ADC_MAX_VALUE1        (1 << 9)
00196 #define DCSR_ADC_MAX_VALUE0        (1 << 8)
00197 #define DCSR_DIAG_DONE             (1 << 7)
00198 #define DCSR_DIAG_POL              (1 << 6)
00199 #define DCSR_DIAG_SEL_LINE         (1 << 5)
00200 #define DCSR_PW_DIAG4              (1 << 4)
00201 #define DCSR_PW_DIAG3              (1 << 3)
00202 #define DCSR_PW_DIAG2              (1 << 2)
00203 #define DCSR_PW_DIAG1              (1 << 1)
00204 #define DCSR_PW_DIAG0              (1 << 0)
00205 
00206 //DCR register
00207 #define DCR_CNT_WINDOW7            (1 << 15)
00208 #define DCR_CNT_WINDOW6            (1 << 14)
00209 #define DCR_CNT_WINDOW5            (1 << 13)
00210 #define DCR_CNT_WINDOW4            (1 << 12)
00211 #define DCR_CNT_WINDOW3            (1 << 11)
00212 #define DCR_CNT_WINDOW2            (1 << 10)
00213 #define DCR_CNT_WINDOW1            (1 << 9)
00214 #define DCR_CNT_WINDOW0            (1 << 8)
00215 #define DCR_DIAGCNT7               (1 << 7)
00216 #define DCR_DIAGCNT6               (1 << 6)
00217 #define DCR_DIAGCNT5               (1 << 5)
00218 #define DCR_DIAGCNT4               (1 << 4)
00219 #define DCR_DIAGCNT3               (1 << 3)
00220 #define DCR_DIAGCNT2               (1 << 2)
00221 #define DCR_DIAGCNT1               (1 << 1)
00222 #define DCR_DIAGCNT0               (1 << 0)
00223 
00224 //SCSIR register
00225 #define SCSIR_SWRST_FAST           (1 << 12)
00226 #define SCSIR_SQEOFF               (1 << 11)
00227 #define SCSIR_FEFIEN               (1 << 5)
00228 #define SCSIR_XPOL                 (1 << 4)
00229 
00230 //ISR register
00231 #define ISR_BER                    (1 << 10)
00232 #define ISR_FEQ                    (1 << 9)
00233 #define ISR_ENERGYON               (1 << 7)
00234 #define ISR_AN_COMPLETE            (1 << 6)
00235 #define ISR_REMOTE_FAULT           (1 << 5)
00236 #define ISR_LINK_DOWN              (1 << 4)
00237 #define ISR_AN_LP_ACK              (1 << 3)
00238 #define ISR_PD_FAULT               (1 << 2)
00239 #define ISR_AN_PAGE_RECEIVED       (1 << 1)
00240 
00241 //IER register
00242 #define IER_BER                    (1 << 10)
00243 #define IER_FEQ                    (1 << 9)
00244 #define IER_ENERGYON               (1 << 7)
00245 #define IER_AN_COMPLETE            (1 << 6)
00246 #define IER_REMOTE_FAULT           (1 << 5)
00247 #define IER_LINK_DOWN              (1 << 4)
00248 #define IER_AN_LP_ACK              (1 << 3)
00249 #define IER_PD_FAULT               (1 << 2)
00250 #define IER_AN_PAGE_RECEIVED       (1 << 1)
00251 
00252 //PSCSR register
00253 #define PSCSR_AUTODONE             (1 << 12)
00254 #define PSCSR_ENABLE_4B5B          (1 << 6)
00255 #define PSCSR_HCDSPEED2            (1 << 4)
00256 #define PSCSR_HCDSPEED1            (1 << 3)
00257 #define PSCSR_HCDSPEED0            (1 << 2)
00258 #define PSCSR_RX_DV_J2T            (1 << 1)
00259 #define PSCSR_SCRAMBLE_DIS         (1 << 0)
00260 
00261 //Speed indication
00262 #define PSCSR_HCDSPEED_MASK        (7 << 2)
00263 #define PSCSR_HCDSPEED_10BT        (1 << 2)
00264 #define PSCSR_HCDSPEED_100BTX      (2 << 2)
00265 #define PSCSR_HCDSPEED_10BT_FD     (5 << 2)
00266 #define PSCSR_HCDSPEED_100BTX_FD   (6 << 2)
00267 
00268 //uPD60611 Ethernet PHY driver
00269 extern const PhyDriver upd60611PhyDriver;
00270 
00271 //uPD60611 related functions
00272 error_t upd60611Init(NetInterface *interface);
00273 
00274 void upd60611Tick(NetInterface *interface);
00275 
00276 void upd60611EnableIrq(NetInterface *interface);
00277 void upd60611DisableIrq(NetInterface *interface);
00278 
00279 void upd60611EventHandler(NetInterface *interface);
00280 
00281 void upd60611WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00282 uint16_t upd60611ReadPhyReg(NetInterface *interface, uint8_t address);
00283 
00284 void upd60611DumpPhyReg(NetInterface *interface);
00285 
00286 #endif
00287