tm4c129_eth.h

00001 /**
00002  * @file tm4c129_eth.h
00003  * @brief Tiva TM4C129 Ethernet controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _TM4C129_ETH_H
00030 #define _TM4C129_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef TM4C129_ETH_TX_BUFFER_COUNT
00037    #define TM4C129_ETH_TX_BUFFER_COUNT 3
00038 #elif (TM4C129_ETH_TX_BUFFER_COUNT < 1)
00039    #error TM4C129_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef TM4C129_ETH_TX_BUFFER_SIZE
00044    #define TM4C129_ETH_TX_BUFFER_SIZE 1536
00045 #elif (TM4C129_ETH_TX_BUFFER_SIZE != 1536)
00046    #error TM4C129_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef TM4C129_ETH_RX_BUFFER_COUNT
00051    #define TM4C129_ETH_RX_BUFFER_COUNT 6
00052 #elif (TM4C129_ETH_RX_BUFFER_COUNT < 1)
00053    #error TM4C129_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef TM4C129_ETH_RX_BUFFER_SIZE
00058    #define TM4C129_ETH_RX_BUFFER_SIZE 1536
00059 #elif (TM4C129_ETH_RX_BUFFER_SIZE != 1536)
00060    #error TM4C129_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Interrupt priority grouping
00064 #ifndef TM4C129_ETH_IRQ_PRIORITY_GROUPING
00065    #define TM4C129_ETH_IRQ_PRIORITY_GROUPING 3
00066 #elif (TM4C129_ETH_IRQ_PRIORITY_GROUPING < 0)
00067    #error TM4C129_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
00068 #endif
00069 
00070 //Ethernet interrupt priority
00071 #ifndef TM4C129_ETH_IRQ_PRIORITY
00072    #define TM4C129_ETH_IRQ_PRIORITY 192
00073 #elif (TM4C129_ETH_IRQ_PRIORITY < 0)
00074    #error TM4C129_ETH_IRQ_PRIORITY parameter is not valid
00075 #endif
00076 
00077 //DMABUSMOD register
00078 #define EMAC_DMABUSMOD_RPBL_1  (1 << EMAC_DMABUSMOD_RPBL_S)
00079 #define EMAC_DMABUSMOD_RPBL_2  (2 << EMAC_DMABUSMOD_RPBL_S)
00080 #define EMAC_DMABUSMOD_RPBL_4  (4 << EMAC_DMABUSMOD_RPBL_S)
00081 #define EMAC_DMABUSMOD_RPBL_8  (8 << EMAC_DMABUSMOD_RPBL_S)
00082 #define EMAC_DMABUSMOD_RPBL_16 (16 << EMAC_DMABUSMOD_RPBL_S)
00083 #define EMAC_DMABUSMOD_RPBL_32 (32 << EMAC_DMABUSMOD_RPBL_S)
00084 
00085 #define EMAC_DMABUSMOD_PR_1_1  (0 << EMAC_DMABUSMOD_PR_S)
00086 #define EMAC_DMABUSMOD_PR_2_1  (1 << EMAC_DMABUSMOD_PR_S)
00087 #define EMAC_DMABUSMOD_PR_3_1  (2 << EMAC_DMABUSMOD_PR_S)
00088 #define EMAC_DMABUSMOD_PR_4_1  (3 << EMAC_DMABUSMOD_PR_S)
00089 
00090 #define EMAC_DMABUSMOD_PBL_1   (1 << EMAC_DMABUSMOD_PBL_S)
00091 #define EMAC_DMABUSMOD_PBL_2   (2 << EMAC_DMABUSMOD_PBL_S)
00092 #define EMAC_DMABUSMOD_PBL_4   (4 << EMAC_DMABUSMOD_PBL_S)
00093 #define EMAC_DMABUSMOD_PBL_8   (8 << EMAC_DMABUSMOD_PBL_S)
00094 #define EMAC_DMABUSMOD_PBL_16  (16 << EMAC_DMABUSMOD_PBL_S)
00095 #define EMAC_DMABUSMOD_PBL_32  (32 << EMAC_DMABUSMOD_PBL_S)
00096 
00097 //Transmit DMA descriptor flags
00098 #define EMAC_TDES0_OWN    0x80000000
00099 #define EMAC_TDES0_IC     0x40000000
00100 #define EMAC_TDES0_LS     0x20000000
00101 #define EMAC_TDES0_FS     0x10000000
00102 #define EMAC_TDES0_DC     0x08000000
00103 #define EMAC_TDES0_DP     0x04000000
00104 #define EMAC_TDES0_TTSE   0x02000000
00105 #define EMAC_TDES0_CRCR   0x01000000
00106 #define EMAC_TDES0_CIC    0x00C00000
00107 #define EMAC_TDES0_TER    0x00200000
00108 #define EMAC_TDES0_TCH    0x00100000
00109 #define EMAC_TDES0_VLIC   0x000C0000
00110 #define EMAC_TDES0_TTSS   0x00020000
00111 #define EMAC_TDES0_IHE    0x00010000
00112 #define EMAC_TDES0_ES     0x00008000
00113 #define EMAC_TDES0_JT     0x00004000
00114 #define EMAC_TDES0_FF     0x00002000
00115 #define EMAC_TDES0_IPE    0x00001000
00116 #define EMAC_TDES0_LCA    0x00000800
00117 #define EMAC_TDES0_NC     0x00000400
00118 #define EMAC_TDES0_LCO    0x00000200
00119 #define EMAC_TDES0_EC     0x00000100
00120 #define EMAC_TDES0_VF     0x00000080
00121 #define EMAC_TDES0_CC     0x00000078
00122 #define EMAC_TDES0_ED     0x00000004
00123 #define EMAC_TDES0_UF     0x00000002
00124 #define EMAC_TDES0_DB     0x00000001
00125 #define EMAC_TDES1_SAIC   0xE0000000
00126 #define EMAC_TDES1_TBS2   0x1FFF0000
00127 #define EMAC_TDES1_TBS1   0x00001FFF
00128 #define EMAC_TDES2_TBAP1  0xFFFFFFFF
00129 #define EMAC_TDES3_TBAP2  0xFFFFFFFF
00130 #define EMAC_TDES6_TTSL   0xFFFFFFFF
00131 #define EMAC_TDES7_TTSH   0xFFFFFFFF
00132 
00133 //Receive DMA descriptor flags
00134 #define EMAC_RDES0_OWN    0x80000000
00135 #define EMAC_RDES0_AFM    0x40000000
00136 #define EMAC_RDES0_FL     0x3FFF0000
00137 #define EMAC_RDES0_ES     0x00008000
00138 #define EMAC_RDES0_DE     0x00004000
00139 #define EMAC_RDES0_SAF    0x00002000
00140 #define EMAC_RDES0_LE     0x00001000
00141 #define EMAC_RDES0_OE     0x00000800
00142 #define EMAC_RDES0_VLAN   0x00000400
00143 #define EMAC_RDES0_FS     0x00000200
00144 #define EMAC_RDES0_LS     0x00000100
00145 #define EMAC_RDES0_TSA_GF 0x00000080
00146 #define EMAC_RDES0_LCO    0x00000040
00147 #define EMAC_RDES0_FT     0x00000020
00148 #define EMAC_RDES0_RWT    0x00000010
00149 #define EMAC_RDES0_RE     0x00000008
00150 #define EMAC_RDES0_DBE    0x00000004
00151 #define EMAC_RDES0_CE     0x00000002
00152 #define EMAC_RDES0_ESA    0x00000001
00153 #define EMAC_RDES1_DIC    0x80000000
00154 #define EMAC_RDES1_RBS2   0x1FFF0000
00155 #define EMAC_RDES1_RER    0x00008000
00156 #define EMAC_RDES1_RCH    0x00004000
00157 #define EMAC_RDES1_RBS1   0x00001FFF
00158 #define EMAC_RDES2_RBAP1  0xFFFFFFFF
00159 #define EMAC_RDES3_RBAP2  0xFFFFFFFF
00160 #define EMAC_RDES4_TSD    0x00004000
00161 #define EMAC_RDES4_PV     0x00002000
00162 #define EMAC_RDES4_PFT    0x00001000
00163 #define EMAC_RDES4_PMT    0x00000F00
00164 #define EMAC_RDES4_IPV6PR 0x00000080
00165 #define EMAC_RDES4_IPV4PR 0x00000040
00166 #define EMAC_RDES4_IPCB   0x00000020
00167 #define EMAC_RDES4_IPPE   0x00000010
00168 #define EMAC_RDES4_IPHE   0x00000008
00169 #define EMAC_RDES4_IPPT   0x00000007
00170 #define EMAC_RDES6_RTSL   0xFFFFFFFF
00171 #define EMAC_RDES7_RTSH   0xFFFFFFFF
00172 
00173 
00174 /**
00175  * @brief Enhanced TX DMA descriptor
00176  **/
00177 
00178 typedef struct
00179 {
00180    uint32_t tdes0;
00181    uint32_t tdes1;
00182    uint32_t tdes2;
00183    uint32_t tdes3;
00184    uint32_t tdes4;
00185    uint32_t tdes5;
00186    uint32_t tdes6;
00187    uint32_t tdes7;
00188 } Tm4c129TxDmaDesc;
00189 
00190 
00191 /**
00192  * @brief Enhanced RX DMA descriptor
00193  **/
00194 
00195 typedef struct
00196 {
00197    uint32_t rdes0;
00198    uint32_t rdes1;
00199    uint32_t rdes2;
00200    uint32_t rdes3;
00201    uint32_t rdes4;
00202    uint32_t rdes5;
00203    uint32_t rdes6;
00204    uint32_t rdes7;
00205 } Tm4c129RxDmaDesc;
00206 
00207 
00208 //TM4C129 Ethernet MAC driver
00209 extern const NicDriver tm4c129EthDriver;
00210 
00211 //TM4C129 Ethernet MAC related functions
00212 error_t tm4c129EthInit(NetInterface *interface);
00213 void tm4c129EthInitGpio(NetInterface *interface);
00214 void tm4c129EthInitDmaDesc(NetInterface *interface);
00215 
00216 void tm4c129EthTick(NetInterface *interface);
00217 
00218 void tm4c129EthEnableIrq(NetInterface *interface);
00219 void tm4c129EthDisableIrq(NetInterface *interface);
00220 void tm4c129EthEventHandler(NetInterface *interface);
00221 
00222 error_t tm4c129EthSendPacket(NetInterface *interface,
00223    const NetBuffer *buffer, size_t offset);
00224 
00225 error_t tm4c129EthReceivePacket(NetInterface *interface);
00226 
00227 error_t tm4c129EthSetMulticastFilter(NetInterface *interface);
00228 
00229 void tm4c129EthWritePhyReg(uint8_t regAddr, uint16_t data);
00230 uint16_t tm4c129EthReadPhyReg(uint8_t regAddr);
00231 void tm4c129EthDumpPhyReg(void);
00232 
00233 uint32_t tm4c129EthCalcCrc(const void *data, size_t length);
00234 
00235 #endif
00236