str912_eth.h

00001 /**
00002  * @file str912_eth.h
00003  * @brief STR9 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _STR912_ETH_H
00030 #define _STR912_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef STR912_ETH_TX_BUFFER_COUNT
00037    #define STR912_ETH_TX_BUFFER_COUNT 2
00038 #elif (STR912_ETH_TX_BUFFER_COUNT < 1)
00039    #error STR912_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef STR912_ETH_TX_BUFFER_SIZE
00044    #define STR912_ETH_TX_BUFFER_SIZE 1536
00045 #elif (STR912_ETH_TX_BUFFER_SIZE != 1536)
00046    #error STR912_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef STR912_ETH_RX_BUFFER_COUNT
00051    #define STR912_ETH_RX_BUFFER_COUNT 4
00052 #elif (STR912_ETH_RX_BUFFER_COUNT < 1)
00053    #error STR912_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef STR912_ETH_RX_BUFFER_SIZE
00058    #define STR912_ETH_RX_BUFFER_SIZE 1536
00059 #elif (STR912_ETH_RX_BUFFER_SIZE != 1536)
00060    #error STR912_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Ethernet interrupt priority
00064 #ifndef STR912_ETH_IRQ_PRIORITY
00065    #define STR912_ETH_IRQ_PRIORITY 15
00066 #elif (STR912_ETH_IRQ_PRIORITY < 0)
00067    #error STR912_ETH_IRQ_PRIORITY parameter is not valid
00068 #endif
00069 
00070 //ENET_SCR register
00071 #define ENET_SCR_TX_FIFO_SIZE          0xF0000000
00072 #define ENET_SCR_TX_IO_DATA_WIDTH      0x0C000000
00073 #define ENET_SCR_TX_CHAN_STATUS        0x03000000
00074 #define ENET_SCR_RX_FIFO_SIZE          0x00F00000
00075 #define ENET_SCR_RX_IO_DATA_WIDTH      0x000C0000
00076 #define ENET_SCR_RX_CHAN_STATUS        0x00030000
00077 #define ENET_SCR_TX_MAX_BURST_SIZE     0x000000C0
00078 #define ENET_SCR_RX_MAX_BURST_SIZE     0x00000030
00079 #define ENET_SCR_LOOPB                 0x00000002
00080 #define ENET_SCR_SRESET                0x00000001
00081 
00082 //ENET_IER register
00083 #define ENET_IER_TX_CURR_DONE_EN       0x80000000
00084 #define ENET_IER_MAC_802_3_INT_EN      0x10000000
00085 #define ENET_IER_TX_MERR_INT_EN        0x02000000
00086 #define ENET_IER_TX_DONE_EN            0x00800000
00087 #define ENET_IER_TX_NEXT_EN            0x00400000
00088 #define ENET_IER_TX_TO_EN              0x00080000
00089 #define ENET_IER_TX_ENTRY_EN           0x00040000
00090 #define ENET_IER_TX_FULL_EN            0x00020000
00091 #define ENET_IER_TX_EMPTY_EN           0x00010000
00092 #define ENET_IER_RX_CURR_DONE_EN       0x00008000
00093 #define ENET_IER_RX_MERR_INT_EN        0x00000200
00094 #define ENET_IER_RX_DONE_EN            0x00000080
00095 #define ENET_IER_RX_NEXT_EN            0x00000040
00096 #define ENET_IER_PACKET_LOST_EN        0x00000020
00097 #define ENET_IER_RX_TO_EN              0x00000008
00098 #define ENET_IER_RX_ENTRY_EN           0x00000004
00099 #define ENET_IER_RX_FULL_EN            0x00000002
00100 #define ENET_IER_RX_EMPTY_EN           0x00000001
00101 
00102 //ENET_ISR register
00103 #define ENET_ISR_TX_CURR_DONE          0x80000000
00104 #define ENET_ISR_MAC_802_3_INT         0x10000000
00105 #define ENET_ISR_TX_MERR_INT           0x02000000
00106 #define ENET_ISR_TX_DONE               0x00800000
00107 #define ENET_ISR_TX_NEXT               0x00400000
00108 #define ENET_ISR_TX_TO                 0x00080000
00109 #define ENET_ISR_TX_ENTRY              0x00040000
00110 #define ENET_ISR_TX_FULL               0x00020000
00111 #define ENET_ISR_TX_EMPTY              0x00010000
00112 #define ENET_ISR_RX_CURR_DONE          0x00008000
00113 #define ENET_ISR_RX_MERR_INT           0x00000200
00114 #define ENET_ISR_RX_DONE               0x00000080
00115 #define ENET_ISR_RX_NEXT               0x00000040
00116 #define ENET_ISR_PACKET_LOST           0x00000020
00117 #define ENET_ISR_RX_TO                 0x00000008
00118 #define ENET_ISR_RX_ENTRY              0x00000004
00119 #define ENET_ISR_RX_FULL               0x00000002
00120 #define ENET_ISR_RX_EMPTY              0x00000001
00121 
00122 //ENET_CCR register
00123 #define ENET_CCR_SEL_CLK               0x0000000C
00124 
00125 #define ENET_CCR_SEL_CLK_0             0x00000000
00126 #define ENET_CCR_SEL_CLK_1             0x00000004
00127 
00128 //ENET_RXSTR register
00129 #define ENET_RXSTR_DFETCH_DLY          0x00FFFF00
00130 #define ENET_RXSTR_COLL_SEEN           0x00000080
00131 #define ENET_RXSTR_RUNT_FRAME          0x00000040
00132 #define ENET_RXSTR_FILTER_FAIL         0x00000020
00133 #define ENET_RXSTR_START_FETCH         0x00000004
00134 #define ENET_RXSTR_DMA_EN              0x00000001
00135 
00136 #define ENET_RXSTR_DFETCH_DLY_DEFAULT  0x00800000
00137 
00138 //ENET_TXSTR register
00139 #define ENET_TXSTR_DFETCH_DLY          0x00FFFF00
00140 #define ENET_TXSTR_UNDER_RUN           0x00000020
00141 #define ENET_TXSTR_START_FETCH         0x00000004
00142 #define ENET_TXSTR_DMA_EN              0x00000001
00143 
00144 #define ENET_TXSTR_DFETCH_DLY_DEFAULT  0x00800000
00145 
00146 //ENET_MCR register
00147 #define ENET_MCR_RA                    0x80000000
00148 #define ENET_MCR_EN                    0x40000000
00149 #define ENET_MCR_PS                    0x03000000
00150 #define ENET_MCR_DRO                   0x00800000
00151 #define ENET_MCR_LM                    0x00600000
00152 #define ENET_MCR_FDM                   0x00100000
00153 #define ENET_MCR_AFM                   0x000E0000
00154 #define ENET_MCR_PWF                   0x00010000
00155 #define ENET_MCR_VFM                   0x00008000
00156 #define ENET_MCR_ELC                   0x00001000
00157 #define ENET_MCR_DBF                   0x00000800
00158 #define ENET_MCR_DPR                   0x00000400
00159 #define ENET_MCR_RVFF                  0x00000200
00160 #define ENET_MCR_APR                   0x00000100
00161 #define ENET_MCR_BL                    0x000000C0
00162 #define ENET_MCR_DCE                   0x00000020
00163 #define ENET_MCR_RVBE                  0x00000010
00164 #define ENET_MCR_TE                    0x00000008
00165 #define ENET_MCR_RE                    0x00000004
00166 #define ENET_MCR_RCFA                  0x00000001
00167 
00168 #define ENET_MCR_PS_0                  0x00000000
00169 #define ENET_MCR_PS_1                  0x01000000
00170 
00171 #define ENET_MCR_AFM_0                 0x00000000
00172 #define ENET_MCR_AFM_1                 0x00020000
00173 #define ENET_MCR_AFM_2                 0x00040000
00174 #define ENET_MCR_AFM_3                 0x00060000
00175 #define ENET_MCR_AFM_4                 0x00080000
00176 #define ENET_MCR_AFM_5                 0x000A0000
00177 #define ENET_MCR_AFM_6                 0x000C0000
00178 #define ENET_MCR_AFM_7                 0x000E0000
00179 
00180 #define ENET_MCR_BL_0                  0x00000000
00181 #define ENET_MCR_BL_1                  0x00000040
00182 #define ENET_MCR_BL_2                  0x00000080
00183 #define ENET_MCR_BL_3                  0x000000C0
00184 
00185 //ENET_MIIA register
00186 #define ENET_MIIA_PADDR                0x0000F800
00187 #define ENET_MIIA_RADDR                0x000007C0
00188 #define ENET_MIIA_PR                   0x00000004
00189 #define ENET_MIIA_WR                   0x00000002
00190 #define ENET_MIIA_BUSY                 0x00000001
00191 
00192 //ENET_MIID register
00193 #define ENET_MIID_RDATA                0x0000FFFF
00194 
00195 //TX DMA descriptor (control word)
00196 #define ENET_TDES_CTRL_DLY_EN          0x00008000
00197 #define ENET_TDES_CTRL_NXT_EN          0x00004000
00198 #define ENET_TDES_CTRL_CONT_EN         0x00001000
00199 #define ENET_TDES_CTRL_FL              0x00000FFF
00200 
00201 //TX DMA descriptor (start address)
00202 #define ENET_TDES_START_ADDR           0xFFFFFFFC
00203 #define ENET_TDES_START_FIX_ADDR       0x00000002
00204 #define ENET_TDES_START_WRAP_EN        0x00000001
00205 
00206 //TX DMA descriptor (next descriptor address)
00207 #define ENET_TDES_NEXT_ADDR            0xFFFFFFFC
00208 #define ENET_TDES_NEXT_NPOL_EN         0x00000001
00209 
00210 //TX DMA descriptor (status word)
00211 #define ENET_TDES_STATUS_PR            0x80000000
00212 #define ENET_TDES_STATUS_BC            0x7FFC0000
00213 #define ENET_TDES_STATUS_VALID         0x00010000
00214 #define ENET_TDES_STATUS_CC            0x00003C00
00215 #define ENET_TDES_STATUS_LCO           0x00000200
00216 #define ENET_TDES_STATUS_DEF           0x00000100
00217 #define ENET_TDES_STATUS_UR            0x00000080
00218 #define ENET_TDES_STATUS_EC            0x00000040
00219 #define ENET_TDES_STATUS_LC            0x00000020
00220 #define ENET_TDES_STATUS_ED            0x00000010
00221 #define ENET_TDES_STATUS_LOC           0x00000008
00222 #define ENET_TDES_STATUS_NC            0x00000004
00223 #define ENET_TDES_STATUS_FA            0x00000001
00224 
00225 //RX DMA descriptor (control word)
00226 #define ENET_RDES_CTRL_DLY_EN          0x00008000
00227 #define ENET_RDES_CTRL_NXT_EN          0x00004000
00228 #define ENET_RDES_CTRL_CONT_EN         0x00001000
00229 #define ENET_RDES_CTRL_FL              0x00000FFF
00230 
00231 //RX DMA descriptor (start address)
00232 #define ENET_RDES_START_ADDR           0xFFFFFFFC
00233 #define ENET_RDES_START_FIX_ADDR       0x00000002
00234 #define ENET_RDES_START_WRAP_EN        0x00000001
00235 
00236 //RX DMA descriptor (next descriptor address)
00237 #define ENET_RDES_NEXT_ADDR            0xFFFFFFFC
00238 #define ENET_RDES_NEXT_NPOL_EN         0x00000001
00239 
00240 //RX DMA descriptor (status word)
00241 #define ENET_RDES_STATUS_FA            0x80000000
00242 #define ENET_RDES_STATUS_PF            0x40000000
00243 #define ENET_RDES_STATUS_FF            0x20000000
00244 #define ENET_RDES_STATUS_BF            0x10000000
00245 #define ENET_RDES_STATUS_MCF           0x08000000
00246 #define ENET_RDES_STATUS_UCF           0x04000000
00247 #define ENET_RDES_STATUS_CF            0x02000000
00248 #define ENET_RDES_STATUS_LE            0x01000000
00249 #define ENET_RDES_STATUS_VL2           0x00800000
00250 #define ENET_RDES_STATUS_VL1           0x00400000
00251 #define ENET_RDES_STATUS_CE            0x00200000
00252 #define ENET_RDES_STATUS_EB            0x00100000
00253 #define ENET_RDES_STATUS_ME            0x00080000
00254 #define ENET_RDES_STATUS_FT            0x00040000
00255 #define ENET_RDES_STATUS_LC            0x00020000
00256 #define ENET_RDES_STATUS_VALID         0x00010000
00257 #define ENET_RDES_STATUS_RF            0x00008000
00258 #define ENET_RDES_STATUS_WT            0x00004000
00259 #define ENET_RDES_STATUS_FCI           0x00002000
00260 #define ENET_RDES_STATUS_OL            0x00001000
00261 #define ENET_RDES_STATUS_FL            0x000007FF
00262 
00263 //Error mask
00264 #define ENET_RDES_STATUS_ERROR (ENET_RDES_STATUS_FA | \
00265    ENET_RDES_STATUS_LE | ENET_RDES_STATUS_CE | \
00266    ENET_RDES_STATUS_EB | ENET_RDES_STATUS_ME | \
00267    ENET_RDES_STATUS_LC | ENET_RDES_STATUS_RF | \
00268    ENET_RDES_STATUS_WT | ENET_RDES_STATUS_OL)
00269 
00270 
00271 /**
00272  * @brief Transmit DMA descriptor
00273  **/
00274 
00275 typedef struct
00276 {
00277    uint32_t ctrl;
00278    uint32_t start;
00279    uint32_t next;
00280    uint32_t status;
00281 } Str912TxDmaDesc;
00282 
00283 
00284 /**
00285  * @brief Receive DMA descriptor
00286  **/
00287 
00288 typedef struct
00289 {
00290    uint32_t ctrl;
00291    uint32_t start;
00292    uint32_t next;
00293    uint32_t status;
00294 } Str912RxDmaDesc;
00295 
00296 
00297 //STR912 Ethernet MAC driver
00298 extern const NicDriver str912EthDriver;
00299 
00300 //STR912 Ethernet MAC related functions
00301 error_t str912EthInit(NetInterface *interface);
00302 void str912EthInitGpio(NetInterface *interface);
00303 void str912EthInitDmaDesc(NetInterface *interface);
00304 
00305 void str912EthTick(NetInterface *interface);
00306 
00307 void str912EthEnableIrq(NetInterface *interface);
00308 void str912EthDisableIrq(NetInterface *interface);
00309 void str912EthEventHandler(NetInterface *interface);
00310 
00311 error_t str912EthSendPacket(NetInterface *interface,
00312    const NetBuffer *buffer, size_t offset);
00313 
00314 error_t str912EthReceivePacket(NetInterface *interface);
00315 
00316 error_t str912EthSetMulticastFilter(NetInterface *interface);
00317 error_t str912EthUpdateMacConfig(NetInterface *interface);
00318 
00319 void str912EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00320 uint16_t str912EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00321 
00322 uint32_t str912EthCalcCrc(const void *data, size_t length);
00323 
00324 #endif
00325