sama5d3_gigabit_eth.h

00001 /**
00002  * @file sama5d3_gigabit_eth.h
00003  * @brief SAMA5D3 Gigabit Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _SAMA5D3_GIGABIT_ETH_H
00030 #define _SAMA5D3_GIGABIT_ETH_H
00031 
00032 //Number of TX buffers
00033 #ifndef SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT
00034    #define SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT 2
00035 #elif (SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT != 2)
00036    #error SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT parameter is not valid
00037 #endif
00038 
00039 //TX buffer size
00040 #ifndef SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE
00041    #define SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE 1536
00042 #elif (SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE != 1536)
00043    #error SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE parameter is not valid
00044 #endif
00045 
00046 //Number of RX buffers
00047 #ifndef SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT
00048    #define SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT 96
00049 #elif (SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT < 12)
00050    #error SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT parameter is not valid
00051 #endif
00052 
00053 //RX buffer size
00054 #ifndef SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE
00055    #define SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE 128
00056 #elif (SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE != 128)
00057    #error SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE parameter is not valid
00058 #endif
00059 
00060 //Gigabit Ethernet interrupt priority
00061 #ifndef SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY
00062    #define SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY 0
00063 #elif (SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY < 0)
00064    #error SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY parameter is not valid
00065 #endif
00066 
00067 //RGMII signals
00068 #define GMAC_RGMII_MASK (PIO_PB18A_G125CK | \
00069    PIO_PB17A_GMDIO | PIO_PB16A_GMDC | PIO_PB13A_GRXER | \
00070    PIO_PB12A_GRXDV | PIO_PB11A_GRXCK | PIO_PB9A_GTXEN | \
00071    PIO_PB8A_GTXCK | PIO_PB7A_GRX3 | PIO_PB6A_GRX2 | \
00072    PIO_PB5A_GRX1 | PIO_PB4A_GRX0 | PIO_PB3A_GTX3 | \
00073    PIO_PB2A_GTX2 | PIO_PB1A_GTX1 | PIO_PB0A_GTX0)
00074 
00075 //TX buffer descriptor flags
00076 #define GMAC_TX_USED           0x80000000
00077 #define GMAC_TX_WRAP           0x40000000
00078 #define GMAC_TX_RLE_ERROR      0x20000000
00079 #define GMAC_TX_UNDERRUN_ERROR 0x10000000
00080 #define GMAC_TX_AHB_ERROR      0x08000000
00081 #define GMAC_TX_LATE_COL_ERROR 0x04000000
00082 #define GMAC_TX_CHECKSUM_ERROR 0x00700000
00083 #define GMAC_TX_NO_CRC         0x00010000
00084 #define GMAC_TX_LAST           0x00008000
00085 #define GMAC_TX_LENGTH         0x00003FFF
00086 
00087 //RX buffer descriptor flags
00088 #define GMAC_RX_ADDRESS        0xFFFFFFFC
00089 #define GMAC_RX_WRAP           0x00000002
00090 #define GMAC_RX_OWNERSHIP      0x00000001
00091 #define GMAC_RX_BROADCAST      0x80000000
00092 #define GMAC_RX_MULTICAST_HASH 0x40000000
00093 #define GMAC_RX_UNICAST_HASH   0x20000000
00094 #define GMAC_RX_SAR            0x08000000
00095 #define GMAC_RX_SAR_MASK       0x06000000
00096 #define GMAC_RX_TYPE_ID        0x01000000
00097 #define GMAC_RX_SNAP           0x01000000
00098 #define GMAC_RX_TYPE_ID_MASK   0x00C00000
00099 #define GMAC_RX_CHECKSUM_VALID 0x00C00000
00100 #define GMAC_RX_VLAN_TAG       0x00200000
00101 #define GMAC_RX_PRIORITY_TAG   0x00100000
00102 #define GMAC_RX_VLAN_PRIORITY  0x000E0000
00103 #define GMAC_RX_CFI            0x00010000
00104 #define GMAC_RX_EOF            0x00008000
00105 #define GMAC_RX_SOF            0x00004000
00106 #define GMAC_RX_LENGTH_MSB     0x00002000
00107 #define GMAC_RX_BAD_FCS        0x00002000
00108 #define GMAC_RX_LENGTH         0x00001FFF
00109 
00110 
00111 #if !defined(_SAMA5D3_ETH_H)
00112 
00113 /**
00114  * @brief Transmit buffer descriptor
00115  **/
00116 
00117 typedef struct
00118 {
00119    uint32_t address;
00120    uint32_t status;
00121 } Sama5d3TxBufferDesc;
00122 
00123 
00124 /**
00125  * @brief Receive buffer descriptor
00126  **/
00127 
00128 typedef struct
00129 {
00130    uint32_t address;
00131    uint32_t status;
00132 } Sama5d3RxBufferDesc;
00133 
00134 #endif
00135 
00136 
00137 //SAMA5D3 Gigabit Ethernet MAC driver
00138 extern const NicDriver sama5d3GigabitEthDriver;
00139 
00140 //SAMA5D3 Gigabit Ethernet MAC related functions
00141 error_t sama5d3GigabitEthInit(NetInterface *interface);
00142 void sama5d3GigabitEthInitGpio(NetInterface *interface);
00143 void sama5d3GigabitEthInitBufferDesc(NetInterface *interface);
00144 
00145 void sama5d3GigabitEthTick(NetInterface *interface);
00146 
00147 void sama5d3GigabitEthEnableIrq(NetInterface *interface);
00148 void sama5d3GigabitEthDisableIrq(NetInterface *interface);
00149 void sama5d3GigabitEthIrqHandler(void);
00150 void sama5d3GigabitEthEventHandler(NetInterface *interface);
00151 
00152 error_t sama5d3GigabitEthSendPacket(NetInterface *interface,
00153    const NetBuffer *buffer, size_t offset);
00154 
00155 error_t sama5d3GigabitEthReceivePacket(NetInterface *interface);
00156 
00157 error_t sama5d3GigabitEthSetMulticastFilter(NetInterface *interface);
00158 error_t sama5d3GigabitEthUpdateMacConfig(NetInterface *interface);
00159 
00160 void sama5d3GigabitEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00161 uint16_t sama5d3GigabitEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00162 
00163 #endif
00164