sama5d3_gigabit_eth.c

00001 /**
00002  * @file sama5d3_gigabit_eth.c
00003  * @brief SAMA5D3 Gigabit Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 //Switch to the appropriate trace level
00030 #define TRACE_LEVEL NIC_TRACE_LEVEL
00031 
00032 //Dependencies
00033 #include <limits.h>
00034 #include "sama5d3x.h"
00035 #include "core/net.h"
00036 #include "drivers/sama5d3_gigabit_eth.h"
00037 #include "debug.h"
00038 
00039 //Underlying network interface
00040 static NetInterface *nicDriverInterface;
00041 
00042 //IAR EWARM compiler?
00043 #if defined(__ICCARM__)
00044 
00045 //TX buffer
00046 #pragma data_alignment = 8
00047 #pragma location = ".ram_no_cache"
00048 static uint8_t txBuffer[SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT][SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE];
00049 //RX buffer
00050 #pragma data_alignment = 8
00051 #pragma location = ".ram_no_cache"
00052 static uint8_t rxBuffer[SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT][SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE];
00053 //TX buffer descriptors
00054 #pragma data_alignment = 8
00055 #pragma location = ".ram_no_cache"
00056 static Sama5d3TxBufferDesc txBufferDesc[SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT];
00057 //RX buffer descriptors
00058 #pragma data_alignment = 8
00059 #pragma location = ".ram_no_cache"
00060 static Sama5d3RxBufferDesc rxBufferDesc[SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT];
00061 
00062 //GCC compiler?
00063 #else
00064 
00065 //TX buffer
00066 static uint8_t txBuffer[SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT][SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE]
00067    __attribute__((aligned(8), __section__(".ram_no_cache")));
00068 //RX buffer
00069 static uint8_t rxBuffer[SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT][SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE]
00070    __attribute__((aligned(8), __section__(".ram_no_cache")));
00071 //TX buffer descriptors
00072 static Sama5d3TxBufferDesc txBufferDesc[SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT]
00073    __attribute__((aligned(8), __section__(".ram_no_cache")));
00074 //RX buffer descriptors
00075 static Sama5d3RxBufferDesc rxBufferDesc[SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT]
00076    __attribute__((aligned(8), __section__(".ram_no_cache")));
00077 
00078 #endif
00079 
00080 //TX buffer index
00081 static uint_t txBufferIndex;
00082 //RX buffer index
00083 static uint_t rxBufferIndex;
00084 
00085 
00086 /**
00087  * @brief SAMA5D3 Gigabit Ethernet MAC driver
00088  **/
00089 
00090 const NicDriver sama5d3GigabitEthDriver =
00091 {
00092    NIC_TYPE_ETHERNET,
00093    ETH_MTU,
00094    sama5d3GigabitEthInit,
00095    sama5d3GigabitEthTick,
00096    sama5d3GigabitEthEnableIrq,
00097    sama5d3GigabitEthDisableIrq,
00098    sama5d3GigabitEthEventHandler,
00099    sama5d3GigabitEthSendPacket,
00100    sama5d3GigabitEthSetMulticastFilter,
00101    sama5d3GigabitEthUpdateMacConfig,
00102    sama5d3GigabitEthWritePhyReg,
00103    sama5d3GigabitEthReadPhyReg,
00104    TRUE,
00105    TRUE,
00106    TRUE,
00107    FALSE
00108 };
00109 
00110 
00111 /**
00112  * @brief SAMA5D3 Gigabit Ethernet MAC initialization
00113  * @param[in] interface Underlying network interface
00114  * @return Error code
00115  **/
00116 
00117 error_t sama5d3GigabitEthInit(NetInterface *interface)
00118 {
00119    error_t error;
00120    volatile uint32_t status;
00121 
00122    //Debug message
00123    TRACE_INFO("Initializing SAMA5D3 Gigabit Ethernet MAC...\r\n");
00124 
00125    //Save underlying network interface
00126    nicDriverInterface = interface;
00127 
00128    //Enable GMAC peripheral clock
00129    PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
00130    //Enable IRQ controller peripheral clock
00131    PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
00132 
00133    //GPIO configuration
00134    sama5d3GigabitEthInitGpio(interface);
00135 
00136    //Configure MDC clock speed
00137    GMAC->GMAC_NCFGR = GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_224;
00138    //Enable management port (MDC and MDIO)
00139    GMAC->GMAC_NCR |= GMAC_NCR_MPE;
00140 
00141    //PHY transceiver initialization
00142    error = interface->phyDriver->init(interface);
00143    //Failed to initialize PHY transceiver?
00144    if(error)
00145       return error;
00146 
00147    //Set the MAC address
00148    GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
00149    GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
00150 
00151    //Configure the receive filter
00152    GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
00153 
00154    //Initialize hash table
00155    GMAC->GMAC_HRB = 0;
00156    GMAC->GMAC_HRT = 0;
00157 
00158    //Initialize buffer descriptors
00159    sama5d3GigabitEthInitBufferDesc(interface);
00160 
00161    //Clear transmit status register
00162    GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
00163       GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
00164    //Clear receive status register
00165    GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
00166 
00167    //First disable all GMAC interrupts
00168    GMAC->GMAC_IDR = 0xFFFFFFFF;
00169    //Only the desired ones are enabled
00170    GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
00171       GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
00172 
00173    //Read GMAC ISR register to clear any pending interrupt
00174    status = GMAC->GMAC_ISR;
00175 
00176    //Configure interrupt controller
00177    AIC->AIC_SSR = ID_GMAC;
00178    AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY);
00179    AIC->AIC_SVR = (uint32_t) sama5d3GigabitEthIrqHandler;
00180 
00181    //Enable the GMAC to transmit and receive data
00182    GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
00183 
00184    //Accept any packets from the upper layer
00185    osSetEvent(&interface->nicTxEvent);
00186 
00187    //Successful initialization
00188    return NO_ERROR;
00189 }
00190 
00191 
00192 //SAMA5D3-Xplained evaluation board?
00193 #if defined(USE_SAMA5D3_XPLAINED)
00194 
00195 /**
00196  * @brief GPIO configuration
00197  * @param[in] interface Underlying network interface
00198  **/
00199 
00200 void sama5d3GigabitEthInitGpio(NetInterface *interface)
00201 {
00202    //Enable PIO peripheral clock
00203    PMC->PMC_PCER0 = (1 << ID_PIOB);
00204 
00205    //Disable pull-up resistors on RGMII pins
00206    PIOB->PIO_PUDR = GMAC_RGMII_MASK;
00207    //Disable interrupts-on-change
00208    PIOB->PIO_IDR = GMAC_RGMII_MASK;
00209    //Assign MII pins to peripheral A function
00210    PIOB->PIO_ABCDSR[0] &= ~GMAC_RGMII_MASK;
00211    PIOB->PIO_ABCDSR[1] &= ~GMAC_RGMII_MASK;
00212    //Disable the PIO from controlling the corresponding pins
00213    PIOB->PIO_PDR = GMAC_RGMII_MASK;
00214 
00215    //Select RGMII operation mode
00216    GMAC->GMAC_UR = GMAC_UR_RGMII;
00217 }
00218 
00219 #endif
00220 
00221 
00222 /**
00223  * @brief Initialize buffer descriptors
00224  * @param[in] interface Underlying network interface
00225  **/
00226 
00227 void sama5d3GigabitEthInitBufferDesc(NetInterface *interface)
00228 {
00229    uint_t i;
00230    uint32_t address;
00231 
00232    //Initialize TX buffer descriptors
00233    for(i = 0; i < SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT; i++)
00234    {
00235       //Calculate the address of the current TX buffer
00236       address = (uint32_t) txBuffer[i];
00237       //Write the address to the descriptor entry
00238       txBufferDesc[i].address = address;
00239       //Initialize status field
00240       txBufferDesc[i].status = GMAC_TX_USED;
00241    }
00242 
00243    //Mark the last descriptor entry with the wrap flag
00244    txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
00245    //Initialize TX buffer index
00246    txBufferIndex = 0;
00247 
00248    //Initialize RX buffer descriptors
00249    for(i = 0; i < SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT; i++)
00250    {
00251       //Calculate the address of the current RX buffer
00252       address = (uint32_t) rxBuffer[i];
00253       //Write the address to the descriptor entry
00254       rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
00255       //Clear status field
00256       rxBufferDesc[i].status = 0;
00257    }
00258 
00259    //Mark the last descriptor entry with the wrap flag
00260    rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
00261    //Initialize RX buffer index
00262    rxBufferIndex = 0;
00263 
00264    //Start location of the TX descriptor list
00265    GMAC->GMAC_TBQB = (uint32_t) txBufferDesc;
00266    //Start location of the RX descriptor list
00267    GMAC->GMAC_RBQB = (uint32_t) rxBufferDesc;
00268 }
00269 
00270 
00271 /**
00272  * @brief SAMA5D3 Gigabit Ethernet MAC timer handler
00273  *
00274  * This routine is periodically called by the TCP/IP stack to
00275  * handle periodic operations such as polling the link state
00276  *
00277  * @param[in] interface Underlying network interface
00278  **/
00279 
00280 void sama5d3GigabitEthTick(NetInterface *interface)
00281 {
00282    //Handle periodic operations
00283    interface->phyDriver->tick(interface);
00284 }
00285 
00286 
00287 /**
00288  * @brief Enable interrupts
00289  * @param[in] interface Underlying network interface
00290  **/
00291 
00292 void sama5d3GigabitEthEnableIrq(NetInterface *interface)
00293 {
00294    //Enable Ethernet MAC interrupts
00295    AIC->AIC_SSR = ID_GMAC;
00296    AIC->AIC_IECR = AIC_IECR_INTEN;
00297    //Enable Ethernet PHY interrupts
00298    interface->phyDriver->enableIrq(interface);
00299 }
00300 
00301 
00302 /**
00303  * @brief Disable interrupts
00304  * @param[in] interface Underlying network interface
00305  **/
00306 
00307 void sama5d3GigabitEthDisableIrq(NetInterface *interface)
00308 {
00309    //Disable Ethernet MAC interrupts
00310    AIC->AIC_SSR = ID_GMAC;
00311    AIC->AIC_IDCR = AIC_IDCR_INTD;
00312    //Disable Ethernet PHY interrupts
00313    interface->phyDriver->disableIrq(interface);
00314 }
00315 
00316 
00317 /**
00318  * @brief SAMA5D3 Gigabit Ethernet MAC interrupt service routine
00319  **/
00320 
00321 void sama5d3GigabitEthIrqHandler(void)
00322 {
00323    bool_t flag;
00324    volatile uint32_t isr;
00325    volatile uint32_t tsr;
00326    volatile uint32_t rsr;
00327 
00328    //Enter interrupt service routine
00329    osEnterIsr();
00330 
00331    //This flag will be set if a higher priority task must be woken
00332    flag = FALSE;
00333 
00334    //Each time the software reads GMAC_ISR, it has to check the
00335    //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
00336    isr = GMAC->GMAC_ISR;
00337    tsr = GMAC->GMAC_TSR;
00338    rsr = GMAC->GMAC_RSR;
00339 
00340    //A packet has been transmitted?
00341    if(tsr & (GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
00342       GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR))
00343    {
00344       //Only clear TSR flags that are currently set
00345       GMAC->GMAC_TSR = tsr;
00346 
00347       //Avoid DMA lockup by sending only one frame at a time (see errata 57.5.1)
00348       if((txBufferDesc[0].status & GMAC_TX_USED) &&
00349          (txBufferDesc[1].status & GMAC_TX_USED))
00350       {
00351          //Notify the TCP/IP stack that the transmitter is ready to send
00352          flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
00353       }
00354    }
00355 
00356    //A packet has been received?
00357    if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
00358    {
00359       //Set event flag
00360       nicDriverInterface->nicEvent = TRUE;
00361       //Notify the TCP/IP stack of the event
00362       flag |= osSetEventFromIsr(&netEvent);
00363    }
00364 
00365    //Write AIC_EOICR register before exiting
00366    AIC->AIC_EOICR = 0;
00367 
00368    //Leave interrupt service routine
00369    osExitIsr(flag);
00370 }
00371 
00372 
00373 /**
00374  * @brief SAMA5D3 Gigabit Ethernet MAC event handler
00375  * @param[in] interface Underlying network interface
00376  **/
00377 
00378 void sama5d3GigabitEthEventHandler(NetInterface *interface)
00379 {
00380    error_t error;
00381    uint32_t rsr;
00382 
00383    //Read receive status
00384    rsr = GMAC->GMAC_RSR;
00385 
00386    //Packet received?
00387    if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
00388    {
00389       //Only clear RSR flags that are currently set
00390       GMAC->GMAC_RSR = rsr;
00391 
00392       //Process all pending packets
00393       do
00394       {
00395          //Read incoming packet
00396          error = sama5d3GigabitEthReceivePacket(interface);
00397 
00398          //No more data in the receive buffer?
00399       } while(error != ERROR_BUFFER_EMPTY);
00400    }
00401 }
00402 
00403 
00404 /**
00405  * @brief Send a packet
00406  * @param[in] interface Underlying network interface
00407  * @param[in] buffer Multi-part buffer containing the data to send
00408  * @param[in] offset Offset to the first data byte
00409  * @return Error code
00410  **/
00411 
00412 error_t sama5d3GigabitEthSendPacket(NetInterface *interface,
00413    const NetBuffer *buffer, size_t offset)
00414 {
00415    size_t length;
00416 
00417    //Retrieve the length of the packet
00418    length = netBufferGetLength(buffer) - offset;
00419 
00420    //Check the frame length
00421    if(length > SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE)
00422    {
00423       //The transmitter can accept another packet
00424       osSetEvent(&interface->nicTxEvent);
00425       //Report an error
00426       return ERROR_INVALID_LENGTH;
00427    }
00428 
00429    //Make sure the current buffer is available for writing
00430    if(!(txBufferDesc[txBufferIndex].status & GMAC_TX_USED))
00431       return ERROR_FAILURE;
00432 
00433    //Copy user data to the transmit buffer
00434    netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
00435 
00436    //Set the necessary flags in the descriptor entry
00437    if(txBufferIndex < (SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT - 1))
00438    {
00439       //Write the status word
00440       txBufferDesc[txBufferIndex].status =
00441          GMAC_TX_LAST | (length & GMAC_TX_LENGTH);
00442 
00443       //Point to the next buffer
00444       txBufferIndex++;
00445    }
00446    else
00447    {
00448       //Write the status word
00449       txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP |
00450          GMAC_TX_LAST | (length & GMAC_TX_LENGTH);
00451 
00452       //Wrap around
00453       txBufferIndex = 0;
00454    }
00455 
00456    //Set the TSTART bit to initiate transmission
00457    GMAC->GMAC_NCR |= GMAC_NCR_TSTART;
00458 
00459    //Check whether the next buffer is available for writing
00460    if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
00461    {
00462       //The transmitter can accept another packet
00463       osSetEvent(&interface->nicTxEvent);
00464    }
00465 
00466    //Successful processing
00467    return NO_ERROR;
00468 }
00469 
00470 
00471 /**
00472  * @brief Receive a packet
00473  * @param[in] interface Underlying network interface
00474  * @return Error code
00475  **/
00476 
00477 error_t sama5d3GigabitEthReceivePacket(NetInterface *interface)
00478 {
00479    static uint8_t temp[ETH_MAX_FRAME_SIZE];
00480    error_t error;
00481    uint_t i;
00482    uint_t j;
00483    uint_t sofIndex;
00484    uint_t eofIndex;
00485    size_t n;
00486    size_t size;
00487    size_t length;
00488 
00489    //Initialize SOF and EOF indices
00490    sofIndex = UINT_MAX;
00491    eofIndex = UINT_MAX;
00492 
00493    //Search for SOF and EOF flags
00494    for(i = 0; i < SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT; i++)
00495    {
00496       //Point to the current entry
00497       j = rxBufferIndex + i;
00498 
00499       //Wrap around to the beginning of the buffer if necessary
00500       if(j >= SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT)
00501          j -= SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT;
00502 
00503       //No more entries to process?
00504       if(!(rxBufferDesc[j].address & GMAC_RX_OWNERSHIP))
00505       {
00506          //Stop processing
00507          break;
00508       }
00509       //A valid SOF has been found?
00510       if(rxBufferDesc[j].status & GMAC_RX_SOF)
00511       {
00512          //Save the position of the SOF
00513          sofIndex = i;
00514       }
00515       //A valid EOF has been found?
00516       if((rxBufferDesc[j].status & GMAC_RX_EOF) && sofIndex != UINT_MAX)
00517       {
00518          //Save the position of the EOF
00519          eofIndex = i;
00520          //Retrieve the length of the frame
00521          size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
00522          //Limit the number of data to read
00523          size = MIN(size, ETH_MAX_FRAME_SIZE);
00524          //Stop processing since we have reached the end of the frame
00525          break;
00526       }
00527    }
00528 
00529    //Determine the number of entries to process
00530    if(eofIndex != UINT_MAX)
00531       j = eofIndex + 1;
00532    else if(sofIndex != UINT_MAX)
00533       j = sofIndex;
00534    else
00535       j = i;
00536 
00537    //Total number of bytes that have been copied from the receive buffer
00538    length = 0;
00539 
00540    //Process incoming frame
00541    for(i = 0; i < j; i++)
00542    {
00543       //Any data to copy from current buffer?
00544       if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
00545       {
00546          //Calculate the number of bytes to read at a time
00547          n = MIN(size, SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE);
00548          //Copy data from receive buffer
00549          memcpy(temp + length, rxBuffer[rxBufferIndex], n);
00550          //Update byte counters
00551          length += n;
00552          size -= n;
00553       }
00554 
00555       //Mark the current buffer as free
00556       rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
00557 
00558       //Point to the following entry
00559       rxBufferIndex++;
00560 
00561       //Wrap around to the beginning of the buffer if necessary
00562       if(rxBufferIndex >= SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT)
00563          rxBufferIndex = 0;
00564    }
00565 
00566    //Any packet to process?
00567    if(length > 0)
00568    {
00569       //Pass the packet to the upper layer
00570       nicProcessPacket(interface, temp, length);
00571       //Valid packet received
00572       error = NO_ERROR;
00573    }
00574    else
00575    {
00576       //No more data in the receive buffer
00577       error = ERROR_BUFFER_EMPTY;
00578    }
00579 
00580    //Return status code
00581    return error;
00582 }
00583 
00584 
00585 /**
00586  * @brief Configure multicast MAC address filtering
00587  * @param[in] interface Underlying network interface
00588  * @return Error code
00589  **/
00590 
00591 error_t sama5d3GigabitEthSetMulticastFilter(NetInterface *interface)
00592 {
00593    uint_t i;
00594    uint_t k;
00595    uint8_t *p;
00596    uint32_t hashTable[2];
00597    MacFilterEntry *entry;
00598 
00599    //Debug message
00600    TRACE_DEBUG("Updating SAMA5D3 Gigabit hash table...\r\n");
00601 
00602    //Clear hash table
00603    hashTable[0] = 0;
00604    hashTable[1] = 0;
00605 
00606    //The MAC filter table contains the multicast MAC addresses
00607    //to accept when receiving an Ethernet frame
00608    for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
00609    {
00610       //Point to the current entry
00611       entry = &interface->macMulticastFilter[i];
00612 
00613       //Valid entry?
00614       if(entry->refCount > 0)
00615       {
00616          //Point to the MAC address
00617          p = entry->addr.b;
00618 
00619          //Apply the hash function
00620          k = (p[0] >> 6) ^ p[0];
00621          k ^= (p[1] >> 4) ^ (p[1] << 2);
00622          k ^= (p[2] >> 2) ^ (p[2] << 4);
00623          k ^= (p[3] >> 6) ^ p[3];
00624          k ^= (p[4] >> 4) ^ (p[4] << 2);
00625          k ^= (p[5] >> 2) ^ (p[5] << 4);
00626 
00627          //The hash value is reduced to a 6-bit index
00628          k &= 0x3F;
00629 
00630          //Update hash table contents
00631          hashTable[k / 32] |= (1 << (k % 32));
00632       }
00633    }
00634 
00635    //Write the hash table
00636    GMAC->GMAC_HRB = hashTable[0];
00637    GMAC->GMAC_HRT = hashTable[1];
00638 
00639    //Debug message
00640    TRACE_DEBUG("  HRB = %08" PRIX32 "\r\n", GMAC->GMAC_HRB);
00641    TRACE_DEBUG("  HRT = %08" PRIX32 "\r\n", GMAC->GMAC_HRT);
00642 
00643    //Successful processing
00644    return NO_ERROR;
00645 }
00646 
00647 
00648 /**
00649  * @brief Adjust MAC configuration parameters for proper operation
00650  * @param[in] interface Underlying network interface
00651  * @return Error code
00652  **/
00653 
00654 error_t sama5d3GigabitEthUpdateMacConfig(NetInterface *interface)
00655 {
00656    uint32_t config;
00657 
00658    //Read network configuration register
00659    config = GMAC->GMAC_NCFGR;
00660 
00661    //1000BASE-T operation mode?
00662    if(interface->linkSpeed == NIC_LINK_SPEED_1GBPS)
00663    {
00664       config |= GMAC_NCFGR_GBE;
00665       config &= ~GMAC_NCFGR_SPD;
00666    }
00667    //100BASE-TX operation mode?
00668    else if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
00669    {
00670       config &= ~GMAC_NCFGR_GBE;
00671       config |= GMAC_NCFGR_SPD;
00672    }
00673    //10BASE-T operation mode?
00674    else
00675    {
00676       config &= ~GMAC_NCFGR_GBE;
00677       config &= ~GMAC_NCFGR_SPD;
00678    }
00679 
00680    //Half-duplex or full-duplex mode?
00681    if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
00682       config |= GMAC_NCFGR_FD;
00683    else
00684       config &= ~GMAC_NCFGR_FD;
00685 
00686    //Write configuration value back to NCFGR register
00687    GMAC->GMAC_NCFGR = config;
00688 
00689    //Successful processing
00690    return NO_ERROR;
00691 }
00692 
00693 
00694 /**
00695  * @brief Write PHY register
00696  * @param[in] phyAddr PHY address
00697  * @param[in] regAddr Register address
00698  * @param[in] data Register value
00699  **/
00700 
00701 void sama5d3GigabitEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
00702 {
00703    uint32_t value;
00704 
00705    //Set up a write operation
00706    value = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
00707    //PHY address
00708    value |= GMAC_MAN_PHYA(phyAddr);
00709    //Register address
00710    value |= GMAC_MAN_REGA(regAddr);
00711    //Register value
00712    value |= GMAC_MAN_DATA(data);
00713 
00714    //Start a write operation
00715    GMAC->GMAC_MAN = value;
00716    //Wait for the write to complete
00717    while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
00718 }
00719 
00720 
00721 /**
00722  * @brief Read PHY register
00723  * @param[in] phyAddr PHY address
00724  * @param[in] regAddr Register address
00725  * @return Register value
00726  **/
00727 
00728 uint16_t sama5d3GigabitEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
00729 {
00730    uint32_t value;
00731 
00732    //Set up a read operation
00733    value = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
00734    //PHY address
00735    value |= GMAC_MAN_PHYA(phyAddr);
00736    //Register address
00737    value |= GMAC_MAN_REGA(regAddr);
00738 
00739    //Start a read operation
00740    GMAC->GMAC_MAN = value;
00741    //Wait for the read to complete
00742    while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
00743 
00744    //Return PHY register contents
00745    return GMAC->GMAC_MAN & GMAC_MAN_DATA_Msk;
00746 }
00747