sama5d3_eth.h

00001 /**
00002  * @file sama5d3_eth.h
00003  * @brief SAMA5D3 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _SAMA5D3_ETH_H
00030 #define _SAMA5D3_ETH_H
00031 
00032 //Number of TX buffers
00033 #ifndef SAMA5D3_ETH_TX_BUFFER_COUNT
00034    #define SAMA5D3_ETH_TX_BUFFER_COUNT 4
00035 #elif (SAMA5D3_ETH_TX_BUFFER_COUNT < 1)
00036    #error SAMA5D3_ETH_TX_BUFFER_COUNT parameter is not valid
00037 #endif
00038 
00039 //TX buffer size
00040 #ifndef SAMA5D3_ETH_TX_BUFFER_SIZE
00041    #define SAMA5D3_ETH_TX_BUFFER_SIZE 1536
00042 #elif (SAMA5D3_ETH_TX_BUFFER_SIZE != 1536)
00043    #error SAMA5D3_ETH_TX_BUFFER_SIZE parameter is not valid
00044 #endif
00045 
00046 //Number of RX buffers
00047 #ifndef SAMA5D3_ETH_RX_BUFFER_COUNT
00048    #define SAMA5D3_ETH_RX_BUFFER_COUNT 96
00049 #elif (SAMA5D3_ETH_RX_BUFFER_COUNT < 12)
00050    #error SAMA5D3_ETH_RX_BUFFER_COUNT parameter is not valid
00051 #endif
00052 
00053 //RX buffer size
00054 #ifndef SAMA5D3_ETH_RX_BUFFER_SIZE
00055    #define SAMA5D3_ETH_RX_BUFFER_SIZE 128
00056 #elif (SAMA5D3_ETH_RX_BUFFER_SIZE != 128)
00057    #error SAMA5D3_ETH_RX_BUFFER_SIZE parameter is not valid
00058 #endif
00059 
00060 //Ethernet interrupt priority
00061 #ifndef SAMA5D3_ETH_IRQ_PRIORITY
00062    #define SAMA5D3_ETH_IRQ_PRIORITY 0
00063 #elif (SAMA5D3_ETH_IRQ_PRIORITY < 0)
00064    #error SAMA5D3_ETH_IRQ_PRIORITY parameter is not valid
00065 #endif
00066 
00067 //RMII signals
00068 #define EMAC_RMII_MASK (PIO_PC9A_EMDIO | PIO_PC8A_EMDC | \
00069    PIO_PC7A_EREFCK | PIO_PC6A_ERXER | PIO_PC5A_ECRSDV | PIO_PC4A_ETXEN | \
00070    PIO_PC3A_ERX1 | PIO_PC2A_ERX0 | PIO_PC1A_ETX1 | PIO_PC0A_ETX0)
00071 
00072 //TX buffer descriptor flags
00073 #define EMAC_TX_USED           0x80000000
00074 #define EMAC_TX_WRAP           0x40000000
00075 #define EMAC_TX_ERROR          0x20000000
00076 #define EMAC_TX_UNDERRUN       0x10000000
00077 #define EMAC_TX_EXHAUSTED      0x08000000
00078 #define EMAC_TX_NO_CRC         0x00010000
00079 #define EMAC_TX_LAST           0x00008000
00080 #define EMAC_TX_LENGTH         0x000007FF
00081 
00082 //RX buffer descriptor flags
00083 #define EMAC_RX_ADDRESS        0xFFFFFFFC
00084 #define EMAC_RX_WRAP           0x00000002
00085 #define EMAC_RX_OWNERSHIP      0x00000001
00086 #define EMAC_RX_BROADCAST      0x80000000
00087 #define EMAC_RX_MULTICAST_HASH 0x40000000
00088 #define EMAC_RX_UNICAST_HASH   0x20000000
00089 #define EMAC_RX_EXT_ADDR       0x10000000
00090 #define EMAC_RX_SAR1           0x04000000
00091 #define EMAC_RX_SAR2           0x02000000
00092 #define EMAC_RX_SAR3           0x01000000
00093 #define EMAC_RX_SAR4           0x00800000
00094 #define EMAC_RX_TYPE_ID        0x00400000
00095 #define EMAC_RX_VLAN_TAG       0x00200000
00096 #define EMAC_RX_PRIORITY_TAG   0x00100000
00097 #define EMAC_RX_VLAN_PRIORITY  0x000E0000
00098 #define EMAC_RX_CFI            0x00010000
00099 #define EMAC_RX_EOF            0x00008000
00100 #define EMAC_RX_SOF            0x00004000
00101 #define EMAC_RX_OFFSET         0x00003000
00102 #define EMAC_RX_LENGTH         0x00000FFF
00103 
00104 
00105 #if !defined(_SAMA5D3_GIGABIT_ETH_H)
00106 
00107 /**
00108  * @brief Transmit buffer descriptor
00109  **/
00110 
00111 typedef struct
00112 {
00113    uint32_t address;
00114    uint32_t status;
00115 } Sama5d3TxBufferDesc;
00116 
00117 
00118 /**
00119  * @brief Receive buffer descriptor
00120  **/
00121 
00122 typedef struct
00123 {
00124    uint32_t address;
00125    uint32_t status;
00126 } Sama5d3RxBufferDesc;
00127 
00128 #endif
00129 
00130 
00131 //SAMA5D3 Ethernet MAC driver
00132 extern const NicDriver sama5d3EthDriver;
00133 
00134 //SAMA5D3 Ethernet MAC related functions
00135 error_t sama5d3EthInit(NetInterface *interface);
00136 void sama5d3EthInitGpio(NetInterface *interface);
00137 void sama5d3EthInitBufferDesc(NetInterface *interface);
00138 
00139 void sama5d3EthTick(NetInterface *interface);
00140 
00141 void sama5d3EthEnableIrq(NetInterface *interface);
00142 void sama5d3EthDisableIrq(NetInterface *interface);
00143 void sama5d3EthIrqHandler(void);
00144 void sama5d3EthEventHandler(NetInterface *interface);
00145 
00146 error_t sama5d3EthSendPacket(NetInterface *interface,
00147    const NetBuffer *buffer, size_t offset);
00148 
00149 error_t sama5d3EthReceivePacket(NetInterface *interface);
00150 
00151 error_t sama5d3EthSetMulticastFilter(NetInterface *interface);
00152 error_t sama5d3EthUpdateMacConfig(NetInterface *interface);
00153 
00154 void sama5d3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00155 uint16_t sama5d3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00156 
00157 #endif
00158