sama5d3_eth.c

00001 /**
00002  * @file sama5d3_eth.c
00003  * @brief SAMA5D3 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 //Switch to the appropriate trace level
00030 #define TRACE_LEVEL NIC_TRACE_LEVEL
00031 
00032 //Dependencies
00033 #include <limits.h>
00034 #include "sama5d3x.h"
00035 #include "core/net.h"
00036 #include "drivers/sama5d3_eth.h"
00037 #include "debug.h"
00038 
00039 //Underlying network interface
00040 static NetInterface *nicDriverInterface;
00041 
00042 //IAR EWARM compiler?
00043 #if defined(__ICCARM__)
00044 
00045 //TX buffer
00046 #pragma data_alignment = 8
00047 #pragma location = ".ram_no_cache"
00048 static uint8_t txBuffer[SAMA5D3_ETH_TX_BUFFER_COUNT][SAMA5D3_ETH_TX_BUFFER_SIZE];
00049 //RX buffer
00050 #pragma data_alignment = 8
00051 #pragma location = ".ram_no_cache"
00052 static uint8_t rxBuffer[SAMA5D3_ETH_RX_BUFFER_COUNT][SAMA5D3_ETH_RX_BUFFER_SIZE];
00053 //TX buffer descriptors
00054 #pragma data_alignment = 8
00055 #pragma location = ".ram_no_cache"
00056 static Sama5d3TxBufferDesc txBufferDesc[SAMA5D3_ETH_TX_BUFFER_COUNT];
00057 //RX buffer descriptors
00058 #pragma data_alignment = 8
00059 #pragma location = ".ram_no_cache"
00060 static Sama5d3RxBufferDesc rxBufferDesc[SAMA5D3_ETH_RX_BUFFER_COUNT];
00061 
00062 //GCC compiler?
00063 #else
00064 
00065 //TX buffer
00066 static uint8_t txBuffer[SAMA5D3_ETH_TX_BUFFER_COUNT][SAMA5D3_ETH_TX_BUFFER_SIZE]
00067    __attribute__((aligned(8), __section__(".ram_no_cache")));
00068 //RX buffer
00069 static uint8_t rxBuffer[SAMA5D3_ETH_RX_BUFFER_COUNT][SAMA5D3_ETH_RX_BUFFER_SIZE]
00070    __attribute__((aligned(8), __section__(".ram_no_cache")));
00071 //TX buffer descriptors
00072 static Sama5d3TxBufferDesc txBufferDesc[SAMA5D3_ETH_TX_BUFFER_COUNT]
00073    __attribute__((aligned(8), __section__(".ram_no_cache")));
00074 //RX buffer descriptors
00075 static Sama5d3RxBufferDesc rxBufferDesc[SAMA5D3_ETH_RX_BUFFER_COUNT]
00076    __attribute__((aligned(8), __section__(".ram_no_cache")));
00077 
00078 #endif
00079 
00080 //TX buffer index
00081 static uint_t txBufferIndex;
00082 //RX buffer index
00083 static uint_t rxBufferIndex;
00084 
00085 
00086 /**
00087  * @brief SAMA5D3 Ethernet MAC driver
00088  **/
00089 
00090 const NicDriver sama5d3EthDriver =
00091 {
00092    NIC_TYPE_ETHERNET,
00093    ETH_MTU,
00094    sama5d3EthInit,
00095    sama5d3EthTick,
00096    sama5d3EthEnableIrq,
00097    sama5d3EthDisableIrq,
00098    sama5d3EthEventHandler,
00099    sama5d3EthSendPacket,
00100    sama5d3EthSetMulticastFilter,
00101    sama5d3EthUpdateMacConfig,
00102    sama5d3EthWritePhyReg,
00103    sama5d3EthReadPhyReg,
00104    TRUE,
00105    TRUE,
00106    TRUE,
00107    FALSE
00108 };
00109 
00110 
00111 /**
00112  * @brief SAMA5D3 Ethernet MAC initialization
00113  * @param[in] interface Underlying network interface
00114  * @return Error code
00115  **/
00116 
00117 error_t sama5d3EthInit(NetInterface *interface)
00118 {
00119    error_t error;
00120    volatile uint32_t status;
00121 
00122    //Debug message
00123    TRACE_INFO("Initializing SAMA5D3 Ethernet MAC...\r\n");
00124 
00125    //Save underlying network interface
00126    nicDriverInterface = interface;
00127 
00128    //Enable EMAC peripheral clock
00129    PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
00130    //Enable IRQ controller peripheral clock
00131    PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
00132 
00133    //GPIO configuration
00134    sama5d3EthInitGpio(interface);
00135 
00136    //Configure MDC clock speed
00137    EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
00138    //Enable management port (MDC and MDIO)
00139    EMAC->EMAC_NCR |= EMAC_NCR_MPE;
00140 
00141    //PHY transceiver initialization
00142    error = interface->phyDriver->init(interface);
00143    //Failed to initialize PHY transceiver?
00144    if(error)
00145       return error;
00146 
00147    //Set the MAC address
00148    EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
00149    EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
00150 
00151    //Configure the receive filter
00152    EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI | EMAC_NCFGR_MTI;
00153 
00154    //Initialize hash table
00155    EMAC->EMAC_HRB = 0;
00156    EMAC->EMAC_HRT = 0;
00157 
00158    //Initialize buffer descriptors
00159    sama5d3EthInitBufferDesc(interface);
00160 
00161    //Clear transmit status register
00162    EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
00163       EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
00164    //Clear receive status register
00165    EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
00166 
00167    //First disable all EMAC interrupts
00168    EMAC->EMAC_IDR = 0xFFFFFFFF;
00169    //Only the desired ones are enabled
00170    EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
00171       EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
00172 
00173    //Read EMAC ISR register to clear any pending interrupt
00174    status = EMAC->EMAC_ISR;
00175 
00176    //Configure interrupt controller
00177    AIC->AIC_SSR = ID_EMAC;
00178    AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_ETH_IRQ_PRIORITY);
00179    AIC->AIC_SVR = (uint32_t) sama5d3EthIrqHandler;
00180 
00181    //Enable the EMAC to transmit and receive data
00182    EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
00183 
00184    //Accept any packets from the upper layer
00185    osSetEvent(&interface->nicTxEvent);
00186 
00187    //Successful initialization
00188    return NO_ERROR;
00189 }
00190 
00191 
00192 //SAMA5D3-Xplained evaluation board?
00193 #if defined(USE_SAMA5D3_XPLAINED)
00194 
00195 /**
00196  * @brief GPIO configuration
00197  * @param[in] interface Underlying network interface
00198  **/
00199 
00200 void sama5d3EthInitGpio(NetInterface *interface)
00201 {
00202    //Enable PIO peripheral clock
00203    PMC->PMC_PCER0 = (1 << ID_PIOC);
00204 
00205    //Disable pull-up resistors on RMII pins
00206    PIOC->PIO_PUDR = EMAC_RMII_MASK;
00207    //Disable interrupts-on-change
00208    PIOC->PIO_IDR = EMAC_RMII_MASK;
00209    //Assign RMII pins to peripheral A function
00210    PIOC->PIO_ABCDSR[0] &= ~EMAC_RMII_MASK;
00211    PIOC->PIO_ABCDSR[1] &= ~EMAC_RMII_MASK;
00212    //Disable the PIO from controlling the corresponding pins
00213    PIOC->PIO_PDR = EMAC_RMII_MASK;
00214 
00215    //Select RMII operation mode and enable transceiver clock
00216    EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
00217 }
00218 
00219 #endif
00220 
00221 
00222 /**
00223  * @brief Initialize buffer descriptors
00224  * @param[in] interface Underlying network interface
00225  **/
00226 
00227 void sama5d3EthInitBufferDesc(NetInterface *interface)
00228 {
00229    uint_t i;
00230    uint32_t address;
00231 
00232    //Initialize TX buffer descriptors
00233    for(i = 0; i < SAMA5D3_ETH_TX_BUFFER_COUNT; i++)
00234    {
00235       //Calculate the address of the current TX buffer
00236       address = (uint32_t) txBuffer[i];
00237       //Write the address to the descriptor entry
00238       txBufferDesc[i].address = address;
00239       //Initialize status field
00240       txBufferDesc[i].status = EMAC_TX_USED;
00241    }
00242 
00243    //Mark the last descriptor entry with the wrap flag
00244    txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
00245    //Initialize TX buffer index
00246    txBufferIndex = 0;
00247 
00248    //Initialize RX buffer descriptors
00249    for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
00250    {
00251       //Calculate the address of the current RX buffer
00252       address = (uint32_t) rxBuffer[i];
00253       //Write the address to the descriptor entry
00254       rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
00255       //Clear status field
00256       rxBufferDesc[i].status = 0;
00257    }
00258 
00259    //Mark the last descriptor entry with the wrap flag
00260    rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
00261    //Initialize RX buffer index
00262    rxBufferIndex = 0;
00263 
00264    //Start location of the TX descriptor list
00265    EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
00266    //Start location of the RX descriptor list
00267    EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
00268 }
00269 
00270 
00271 /**
00272  * @brief SAMA5D3 Ethernet MAC timer handler
00273  *
00274  * This routine is periodically called by the TCP/IP stack to
00275  * handle periodic operations such as polling the link state
00276  *
00277  * @param[in] interface Underlying network interface
00278  **/
00279 
00280 void sama5d3EthTick(NetInterface *interface)
00281 {
00282    //Handle periodic operations
00283    interface->phyDriver->tick(interface);
00284 }
00285 
00286 
00287 /**
00288  * @brief Enable interrupts
00289  * @param[in] interface Underlying network interface
00290  **/
00291 
00292 void sama5d3EthEnableIrq(NetInterface *interface)
00293 {
00294    //Enable Ethernet MAC interrupts
00295    AIC->AIC_SSR = ID_EMAC;
00296    AIC->AIC_IECR = AIC_IECR_INTEN;
00297    //Enable Ethernet PHY interrupts
00298    interface->phyDriver->enableIrq(interface);
00299 }
00300 
00301 
00302 /**
00303  * @brief Disable interrupts
00304  * @param[in] interface Underlying network interface
00305  **/
00306 
00307 void sama5d3EthDisableIrq(NetInterface *interface)
00308 {
00309    //Disable Ethernet MAC interrupts
00310    AIC->AIC_SSR = ID_EMAC;
00311    AIC->AIC_IDCR = AIC_IDCR_INTD;
00312    //Disable Ethernet PHY interrupts
00313    interface->phyDriver->disableIrq(interface);
00314 }
00315 
00316 
00317 /**
00318  * @brief SAMA5D3 Ethernet MAC interrupt service routine
00319  **/
00320 
00321 void sama5d3EthIrqHandler(void)
00322 {
00323    bool_t flag;
00324    volatile uint32_t isr;
00325    volatile uint32_t tsr;
00326    volatile uint32_t rsr;
00327 
00328    //Enter interrupt service routine
00329    osEnterIsr();
00330 
00331    //This flag will be set if a higher priority task must be woken
00332    flag = FALSE;
00333 
00334    //Each time the software reads EMAC_ISR, it has to check the
00335    //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
00336    isr = EMAC->EMAC_ISR;
00337    tsr = EMAC->EMAC_TSR;
00338    rsr = EMAC->EMAC_RSR;
00339 
00340    //A packet has been transmitted?
00341    if(tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
00342       EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR))
00343    {
00344       //Only clear TSR flags that are currently set
00345       EMAC->EMAC_TSR = tsr;
00346 
00347       //Check whether the TX buffer is available for writing
00348       if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
00349       {
00350          //Notify the TCP/IP stack that the transmitter is ready to send
00351          flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
00352       }
00353    }
00354 
00355    //A packet has been received?
00356    if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
00357    {
00358       //Set event flag
00359       nicDriverInterface->nicEvent = TRUE;
00360       //Notify the TCP/IP stack of the event
00361       flag |= osSetEventFromIsr(&netEvent);
00362    }
00363 
00364    //Write AIC_EOICR register before exiting
00365    AIC->AIC_EOICR = 0;
00366 
00367    //Leave interrupt service routine
00368    osExitIsr(flag);
00369 }
00370 
00371 
00372 /**
00373  * @brief SAMA5D3 Ethernet MAC event handler
00374  * @param[in] interface Underlying network interface
00375  **/
00376 
00377 void sama5d3EthEventHandler(NetInterface *interface)
00378 {
00379    error_t error;
00380    uint32_t rsr;
00381 
00382    //Read receive status
00383    rsr = EMAC->EMAC_RSR;
00384 
00385    //Packet received?
00386    if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
00387    {
00388       //Only clear RSR flags that are currently set
00389       EMAC->EMAC_RSR = rsr;
00390 
00391       //Process all pending packets
00392       do
00393       {
00394          //Read incoming packet
00395          error = sama5d3EthReceivePacket(interface);
00396 
00397          //No more data in the receive buffer?
00398       } while(error != ERROR_BUFFER_EMPTY);
00399    }
00400 }
00401 
00402 
00403 /**
00404  * @brief Send a packet
00405  * @param[in] interface Underlying network interface
00406  * @param[in] buffer Multi-part buffer containing the data to send
00407  * @param[in] offset Offset to the first data byte
00408  * @return Error code
00409  **/
00410 
00411 error_t sama5d3EthSendPacket(NetInterface *interface,
00412    const NetBuffer *buffer, size_t offset)
00413 {
00414    size_t length;
00415 
00416    //Retrieve the length of the packet
00417    length = netBufferGetLength(buffer) - offset;
00418 
00419    //Check the frame length
00420    if(length > SAMA5D3_ETH_TX_BUFFER_SIZE)
00421    {
00422       //The transmitter can accept another packet
00423       osSetEvent(&interface->nicTxEvent);
00424       //Report an error
00425       return ERROR_INVALID_LENGTH;
00426    }
00427 
00428    //Make sure the current buffer is available for writing
00429    if(!(txBufferDesc[txBufferIndex].status & EMAC_TX_USED))
00430       return ERROR_FAILURE;
00431 
00432    //Copy user data to the transmit buffer
00433    netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
00434 
00435    //Set the necessary flags in the descriptor entry
00436    if(txBufferIndex < (SAMA5D3_ETH_TX_BUFFER_COUNT - 1))
00437    {
00438       //Write the status word
00439       txBufferDesc[txBufferIndex].status =
00440          EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
00441 
00442       //Point to the next buffer
00443       txBufferIndex++;
00444    }
00445    else
00446    {
00447       //Write the status word
00448       txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP |
00449          EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
00450 
00451       //Wrap around
00452       txBufferIndex = 0;
00453    }
00454 
00455    //Set the TSTART bit to initiate transmission
00456    EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
00457 
00458    //Check whether the next buffer is available for writing
00459    if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
00460    {
00461       //The transmitter can accept another packet
00462       osSetEvent(&interface->nicTxEvent);
00463    }
00464 
00465    //Successful processing
00466    return NO_ERROR;
00467 }
00468 
00469 
00470 /**
00471  * @brief Receive a packet
00472  * @param[in] interface Underlying network interface
00473  * @return Error code
00474  **/
00475 
00476 error_t sama5d3EthReceivePacket(NetInterface *interface)
00477 {
00478    static uint8_t temp[ETH_MAX_FRAME_SIZE];
00479    error_t error;
00480    uint_t i;
00481    uint_t j;
00482    uint_t sofIndex;
00483    uint_t eofIndex;
00484    size_t n;
00485    size_t size;
00486    size_t length;
00487 
00488    //Initialize SOF and EOF indices
00489    sofIndex = UINT_MAX;
00490    eofIndex = UINT_MAX;
00491 
00492    //Search for SOF and EOF flags
00493    for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
00494    {
00495       //Point to the current entry
00496       j = rxBufferIndex + i;
00497 
00498       //Wrap around to the beginning of the buffer if necessary
00499       if(j >= SAMA5D3_ETH_RX_BUFFER_COUNT)
00500          j -= SAMA5D3_ETH_RX_BUFFER_COUNT;
00501 
00502       //No more entries to process?
00503       if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
00504       {
00505          //Stop processing
00506          break;
00507       }
00508       //A valid SOF has been found?
00509       if(rxBufferDesc[j].status & EMAC_RX_SOF)
00510       {
00511          //Save the position of the SOF
00512          sofIndex = i;
00513       }
00514       //A valid EOF has been found?
00515       if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
00516       {
00517          //Save the position of the EOF
00518          eofIndex = i;
00519          //Retrieve the length of the frame
00520          size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
00521          //Limit the number of data to read
00522          size = MIN(size, ETH_MAX_FRAME_SIZE);
00523          //Stop processing since we have reached the end of the frame
00524          break;
00525       }
00526    }
00527 
00528    //Determine the number of entries to process
00529    if(eofIndex != UINT_MAX)
00530       j = eofIndex + 1;
00531    else if(sofIndex != UINT_MAX)
00532       j = sofIndex;
00533    else
00534       j = i;
00535 
00536    //Total number of bytes that have been copied from the receive buffer
00537    length = 0;
00538 
00539    //Process incoming frame
00540    for(i = 0; i < j; i++)
00541    {
00542       //Any data to copy from current buffer?
00543       if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
00544       {
00545          //Calculate the number of bytes to read at a time
00546          n = MIN(size, SAMA5D3_ETH_RX_BUFFER_SIZE);
00547          //Copy data from receive buffer
00548          memcpy(temp + length, rxBuffer[rxBufferIndex], n);
00549          //Update byte counters
00550          length += n;
00551          size -= n;
00552       }
00553 
00554       //Mark the current buffer as free
00555       rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
00556 
00557       //Point to the following entry
00558       rxBufferIndex++;
00559 
00560       //Wrap around to the beginning of the buffer if necessary
00561       if(rxBufferIndex >= SAMA5D3_ETH_RX_BUFFER_COUNT)
00562          rxBufferIndex = 0;
00563    }
00564 
00565    //Any packet to process?
00566    if(length > 0)
00567    {
00568       //Pass the packet to the upper layer
00569       nicProcessPacket(interface, temp, length);
00570       //Valid packet received
00571       error = NO_ERROR;
00572    }
00573    else
00574    {
00575       //No more data in the receive buffer
00576       error = ERROR_BUFFER_EMPTY;
00577    }
00578 
00579    //Return status code
00580    return error;
00581 }
00582 
00583 
00584 /**
00585  * @brief Configure multicast MAC address filtering
00586  * @param[in] interface Underlying network interface
00587  * @return Error code
00588  **/
00589 
00590 error_t sama5d3EthSetMulticastFilter(NetInterface *interface)
00591 {
00592    uint_t i;
00593    uint_t k;
00594    uint8_t *p;
00595    uint32_t hashTable[2];
00596    MacFilterEntry *entry;
00597 
00598    //Debug message
00599    TRACE_DEBUG("Updating SAMA5D3 hash table...\r\n");
00600 
00601    //Clear hash table
00602    hashTable[0] = 0;
00603    hashTable[1] = 0;
00604 
00605    //The MAC filter table contains the multicast MAC addresses
00606    //to accept when receiving an Ethernet frame
00607    for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
00608    {
00609       //Point to the current entry
00610       entry = &interface->macMulticastFilter[i];
00611 
00612       //Valid entry?
00613       if(entry->refCount > 0)
00614       {
00615          //Point to the MAC address
00616          p = entry->addr.b;
00617 
00618          //Apply the hash function
00619          k = (p[0] >> 6) ^ p[0];
00620          k ^= (p[1] >> 4) ^ (p[1] << 2);
00621          k ^= (p[2] >> 2) ^ (p[2] << 4);
00622          k ^= (p[3] >> 6) ^ p[3];
00623          k ^= (p[4] >> 4) ^ (p[4] << 2);
00624          k ^= (p[5] >> 2) ^ (p[5] << 4);
00625 
00626          //The hash value is reduced to a 6-bit index
00627          k &= 0x3F;
00628 
00629          //Update hash table contents
00630          hashTable[k / 32] |= (1 << (k % 32));
00631       }
00632    }
00633 
00634    //Write the hash table
00635    EMAC->EMAC_HRB = hashTable[0];
00636    EMAC->EMAC_HRT = hashTable[1];
00637 
00638    //Debug message
00639    TRACE_DEBUG("  HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
00640    TRACE_DEBUG("  HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
00641 
00642    //Successful processing
00643    return NO_ERROR;
00644 }
00645 
00646 
00647 /**
00648  * @brief Adjust MAC configuration parameters for proper operation
00649  * @param[in] interface Underlying network interface
00650  * @return Error code
00651  **/
00652 
00653 error_t sama5d3EthUpdateMacConfig(NetInterface *interface)
00654 {
00655    uint32_t config;
00656 
00657    //Read network configuration register
00658    config = EMAC->EMAC_NCFGR;
00659 
00660    //10BASE-T or 100BASE-TX operation mode?
00661    if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
00662       config |= EMAC_NCFGR_SPD;
00663    else
00664       config &= ~EMAC_NCFGR_SPD;
00665 
00666    //Half-duplex or full-duplex mode?
00667    if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
00668       config |= EMAC_NCFGR_FD;
00669    else
00670       config &= ~EMAC_NCFGR_FD;
00671 
00672    //Write configuration value back to NCFGR register
00673    EMAC->EMAC_NCFGR = config;
00674 
00675    //Successful processing
00676    return NO_ERROR;
00677 }
00678 
00679 
00680 /**
00681  * @brief Write PHY register
00682  * @param[in] phyAddr PHY address
00683  * @param[in] regAddr Register address
00684  * @param[in] data Register value
00685  **/
00686 
00687 void sama5d3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
00688 {
00689    uint32_t value;
00690 
00691    //Set up a write operation
00692    value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
00693    //PHY address
00694    value |= EMAC_MAN_PHYA(phyAddr);
00695    //Register address
00696    value |= EMAC_MAN_REGA(regAddr);
00697    //Register value
00698    value |= EMAC_MAN_DATA(data);
00699 
00700    //Start a write operation
00701    EMAC->EMAC_MAN = value;
00702    //Wait for the write to complete
00703    while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
00704 }
00705 
00706 
00707 /**
00708  * @brief Read PHY register
00709  * @param[in] phyAddr PHY address
00710  * @param[in] regAddr Register address
00711  * @return Register value
00712  **/
00713 
00714 uint16_t sama5d3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
00715 {
00716    uint32_t value;
00717 
00718    //Set up a read operation
00719    value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
00720    //PHY address
00721    value |= EMAC_MAN_PHYA(phyAddr);
00722    //Register address
00723    value |= EMAC_MAN_REGA(regAddr);
00724 
00725    //Start a read operation
00726    EMAC->EMAC_MAN = value;
00727    //Wait for the read to complete
00728    while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
00729 
00730    //Return PHY register contents
00731    return EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
00732 }
00733