sama5d2_eth.h

00001 /**
00002  * @file sama5d2_eth.h
00003  * @brief SAMA5D2 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _SAMA5D2_ETH_H
00030 #define _SAMA5D2_ETH_H
00031 
00032 //Number of TX buffers
00033 #ifndef SAMA5D2_ETH_TX_BUFFER_COUNT
00034    #define SAMA5D2_ETH_TX_BUFFER_COUNT 4
00035 #elif (SAMA5D2_ETH_TX_BUFFER_COUNT < 1)
00036    #error SAMA5D2_ETH_TX_BUFFER_COUNT parameter is not valid
00037 #endif
00038 
00039 //TX buffer size
00040 #ifndef SAMA5D2_ETH_TX_BUFFER_SIZE
00041    #define SAMA5D2_ETH_TX_BUFFER_SIZE 1536
00042 #elif (SAMA5D2_ETH_TX_BUFFER_SIZE != 1536)
00043    #error SAMA5D2_ETH_TX_BUFFER_SIZE parameter is not valid
00044 #endif
00045 
00046 //Number of RX buffers
00047 #ifndef SAMA5D2_ETH_RX_BUFFER_COUNT
00048    #define SAMA5D2_ETH_RX_BUFFER_COUNT 96
00049 #elif (SAMA5D2_ETH_RX_BUFFER_COUNT < 12)
00050    #error SAMA5D2_ETH_RX_BUFFER_COUNT parameter is not valid
00051 #endif
00052 
00053 //RX buffer size
00054 #ifndef SAMA5D2_ETH_RX_BUFFER_SIZE
00055    #define SAMA5D2_ETH_RX_BUFFER_SIZE 128
00056 #elif (SAMA5D2_ETH_RX_BUFFER_SIZE != 128)
00057    #error SAMA5D2_ETH_RX_BUFFER_SIZE parameter is not valid
00058 #endif
00059 
00060 //Number of dummy buffers
00061 #ifndef SAMA5D2_ETH_DUMMY_BUFFER_COUNT
00062    #define SAMA5D2_ETH_DUMMY_BUFFER_COUNT 2
00063 #elif (SAMA5D2_ETH_DUMMY_BUFFER_COUNT < 1)
00064    #error SAMA5D2_ETH_DUMMY_BUFFER_COUNT parameter is not valid
00065 #endif
00066 
00067 //Dummy buffer size
00068 #ifndef SAMA5D2_ETH_DUMMY_BUFFER_SIZE
00069    #define SAMA5D2_ETH_DUMMY_BUFFER_SIZE 128
00070 #elif (SAMA5D2_ETH_DUMMY_BUFFER_SIZE != 128)
00071    #error SAMA5D2_ETH_DUMMY_BUFFER_SIZE parameter is not valid
00072 #endif
00073 
00074 //Ethernet interrupt priority
00075 #ifndef SAMA5D2_ETH_IRQ_PRIORITY
00076    #define SAMA5D2_ETH_IRQ_PRIORITY 0
00077 #elif (SAMA5D2_ETH_IRQ_PRIORITY < 0)
00078    #error SAMA5D2_ETH_IRQ_PRIORITY parameter is not valid
00079 #endif
00080 
00081 //TX buffer descriptor flags
00082 #define GMAC_TX_USED           0x80000000
00083 #define GMAC_TX_WRAP           0x40000000
00084 #define GMAC_TX_RLE_ERROR      0x20000000
00085 #define GMAC_TX_UNDERRUN_ERROR 0x10000000
00086 #define GMAC_TX_AHB_ERROR      0x08000000
00087 #define GMAC_TX_LATE_COL_ERROR 0x04000000
00088 #define GMAC_TX_CHECKSUM_ERROR 0x00700000
00089 #define GMAC_TX_NO_CRC         0x00010000
00090 #define GMAC_TX_LAST           0x00008000
00091 #define GMAC_TX_LENGTH         0x00003FFF
00092 
00093 //RX buffer descriptor flags
00094 #define GMAC_RX_ADDRESS        0xFFFFFFFC
00095 #define GMAC_RX_WRAP           0x00000002
00096 #define GMAC_RX_OWNERSHIP      0x00000001
00097 #define GMAC_RX_BROADCAST      0x80000000
00098 #define GMAC_RX_MULTICAST_HASH 0x40000000
00099 #define GMAC_RX_UNICAST_HASH   0x20000000
00100 #define GMAC_RX_SAR            0x08000000
00101 #define GMAC_RX_SAR_MASK       0x06000000
00102 #define GMAC_RX_TYPE_ID        0x01000000
00103 #define GMAC_RX_SNAP           0x01000000
00104 #define GMAC_RX_TYPE_ID_MASK   0x00C00000
00105 #define GMAC_RX_CHECKSUM_VALID 0x00C00000
00106 #define GMAC_RX_VLAN_TAG       0x00200000
00107 #define GMAC_RX_PRIORITY_TAG   0x00100000
00108 #define GMAC_RX_VLAN_PRIORITY  0x000E0000
00109 #define GMAC_RX_CFI            0x00010000
00110 #define GMAC_RX_EOF            0x00008000
00111 #define GMAC_RX_SOF            0x00004000
00112 #define GMAC_RX_LENGTH_MSB     0x00002000
00113 #define GMAC_RX_BAD_FCS        0x00002000
00114 #define GMAC_RX_LENGTH         0x00001FFF
00115 
00116 
00117 /**
00118  * @brief Transmit buffer descriptor
00119  **/
00120 
00121 typedef struct
00122 {
00123    uint32_t address;
00124    uint32_t status;
00125 } Sama5d2TxBufferDesc;
00126 
00127 
00128 /**
00129  * @brief Receive buffer descriptor
00130  **/
00131 
00132 typedef struct
00133 {
00134    uint32_t address;
00135    uint32_t status;
00136 } Sama5d2RxBufferDesc;
00137 
00138 
00139 //SAMA5D2 Ethernet MAC driver
00140 extern const NicDriver sama5d2EthDriver;
00141 
00142 //SAMA5D2 Ethernet MAC related functions
00143 error_t sama5d2EthInit(NetInterface *interface);
00144 void sama5d2EthInitGpio(NetInterface *interface);
00145 void sama5d2EthInitBufferDesc(NetInterface *interface);
00146 
00147 void sama5d2EthTick(NetInterface *interface);
00148 
00149 void sama5d2EthEnableIrq(NetInterface *interface);
00150 void sama5d2EthDisableIrq(NetInterface *interface);
00151 void sama5d2EthIrqHandler(void);
00152 void sama5d2EthEventHandler(NetInterface *interface);
00153 
00154 error_t sama5d2EthSendPacket(NetInterface *interface,
00155    const NetBuffer *buffer, size_t offset);
00156 
00157 error_t sama5d2EthReceivePacket(NetInterface *interface);
00158 
00159 error_t sama5d2EthSetMulticastFilter(NetInterface *interface);
00160 error_t sama5d2EthUpdateMacConfig(NetInterface *interface);
00161 
00162 void sama5d2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00163 uint16_t sama5d2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00164 
00165 #endif
00166