sam3x_eth.c

00001 /**
00002  * @file sam3x_eth.c
00003  * @brief SAM3X Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 //Switch to the appropriate trace level
00030 #define TRACE_LEVEL NIC_TRACE_LEVEL
00031 
00032 //Dependencies
00033 #include <limits.h>
00034 #include "sam3xa.h"
00035 #include "core/net.h"
00036 #include "drivers/sam3x_eth.h"
00037 #include "debug.h"
00038 
00039 //Underlying network interface
00040 static NetInterface *nicDriverInterface;
00041 
00042 //IAR EWARM compiler?
00043 #if defined(__ICCARM__)
00044 
00045 //TX buffer
00046 #pragma data_alignment = 8
00047 static uint8_t txBuffer[SAM3X_ETH_TX_BUFFER_COUNT][SAM3X_ETH_TX_BUFFER_SIZE];
00048 //RX buffer
00049 #pragma data_alignment = 8
00050 static uint8_t rxBuffer[SAM3X_ETH_RX_BUFFER_COUNT][SAM3X_ETH_RX_BUFFER_SIZE];
00051 //TX buffer descriptors
00052 #pragma data_alignment = 4
00053 static Sam3xTxBufferDesc txBufferDesc[SAM3X_ETH_TX_BUFFER_COUNT];
00054 //RX buffer descriptors
00055 #pragma data_alignment = 4
00056 static Sam3xRxBufferDesc rxBufferDesc[SAM3X_ETH_RX_BUFFER_COUNT];
00057 
00058 //Keil MDK-ARM or GCC compiler?
00059 #else
00060 
00061 //TX buffer
00062 static uint8_t txBuffer[SAM3X_ETH_TX_BUFFER_COUNT][SAM3X_ETH_TX_BUFFER_SIZE]
00063    __attribute__((aligned(8)));
00064 //RX buffer
00065 static uint8_t rxBuffer[SAM3X_ETH_RX_BUFFER_COUNT][SAM3X_ETH_RX_BUFFER_SIZE]
00066    __attribute__((aligned(8)));
00067 //TX buffer descriptors
00068 static Sam3xTxBufferDesc txBufferDesc[SAM3X_ETH_TX_BUFFER_COUNT]
00069    __attribute__((aligned(4)));
00070 //RX buffer descriptors
00071 static Sam3xRxBufferDesc rxBufferDesc[SAM3X_ETH_RX_BUFFER_COUNT]
00072    __attribute__((aligned(4)));
00073 
00074 #endif
00075 
00076 //TX buffer index
00077 static uint_t txBufferIndex;
00078 //RX buffer index
00079 static uint_t rxBufferIndex;
00080 
00081 
00082 /**
00083  * @brief SAM3X Ethernet MAC driver
00084  **/
00085 
00086 const NicDriver sam3xEthDriver =
00087 {
00088    NIC_TYPE_ETHERNET,
00089    ETH_MTU,
00090    sam3xEthInit,
00091    sam3xEthTick,
00092    sam3xEthEnableIrq,
00093    sam3xEthDisableIrq,
00094    sam3xEthEventHandler,
00095    sam3xEthSendPacket,
00096    sam3xEthSetMulticastFilter,
00097    sam3xEthUpdateMacConfig,
00098    sam3xEthWritePhyReg,
00099    sam3xEthReadPhyReg,
00100    TRUE,
00101    TRUE,
00102    TRUE,
00103    FALSE
00104 };
00105 
00106 
00107 /**
00108  * @brief SAM3X Ethernet MAC initialization
00109  * @param[in] interface Underlying network interface
00110  * @return Error code
00111  **/
00112 
00113 error_t sam3xEthInit(NetInterface *interface)
00114 {
00115    error_t error;
00116    volatile uint32_t status;
00117 
00118    //Debug message
00119    TRACE_INFO("Initializing SAM3X Ethernet MAC...\r\n");
00120 
00121    //Save underlying network interface
00122    nicDriverInterface = interface;
00123 
00124    //Enable EMAC peripheral clock
00125    PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
00126 
00127    //GPIO configuration
00128    sam3xEthInitGpio(interface);
00129 
00130    //Configure MDC clock speed
00131    EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
00132    //Enable management port (MDC and MDIO)
00133    EMAC->EMAC_NCR |= EMAC_NCR_MPE;
00134 
00135    //PHY transceiver initialization
00136    error = interface->phyDriver->init(interface);
00137    //Failed to initialize PHY transceiver?
00138    if(error)
00139       return error;
00140 
00141    //Set the MAC address
00142    EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
00143    EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
00144 
00145    //Configure the receive filter
00146    EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI | EMAC_NCFGR_MTI;
00147 
00148    //Initialize hash table
00149    EMAC->EMAC_HRB = 0;
00150    EMAC->EMAC_HRT = 0;
00151 
00152    //Initialize buffer descriptors
00153    sam3xEthInitBufferDesc(interface);
00154 
00155    //Clear transmit status register
00156    EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
00157       EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
00158    //Clear receive status register
00159    EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
00160 
00161    //First disable all EMAC interrupts
00162    EMAC->EMAC_IDR = 0xFFFFFFFF;
00163    //Only the desired ones are enabled
00164    EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
00165       EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
00166 
00167    //Read EMAC ISR register to clear any pending interrupt
00168    status = EMAC->EMAC_ISR;
00169 
00170    //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
00171    NVIC_SetPriorityGrouping(SAM3X_ETH_IRQ_PRIORITY_GROUPING);
00172 
00173    //Configure EMAC interrupt priority
00174    NVIC_SetPriority(EMAC_IRQn, NVIC_EncodePriority(SAM3X_ETH_IRQ_PRIORITY_GROUPING,
00175       SAM3X_ETH_IRQ_GROUP_PRIORITY, SAM3X_ETH_IRQ_SUB_PRIORITY));
00176 
00177    //Enable the EMAC to transmit and receive data
00178    EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
00179 
00180    //Accept any packets from the upper layer
00181    osSetEvent(&interface->nicTxEvent);
00182 
00183    //Successful initialization
00184    return NO_ERROR;
00185 }
00186 
00187 
00188 //SAM3X-EK evaluation board?
00189 #if defined(USE_SAM3X_EK)
00190 
00191 /**
00192  * @brief GPIO configuration
00193  * @param[in] interface Underlying network interface
00194  **/
00195 
00196 void sam3xEthInitGpio(NetInterface *interface)
00197 {
00198    //Enable PIO peripheral clock
00199    PMC->PMC_PCER0 = (1 << ID_PIOB);
00200 
00201    //Disable pull-up resistors on RMII pins
00202    PIOB->PIO_PUDR = EMAC_RMII_MASK;
00203    //Disable interrupts-on-change
00204    PIOB->PIO_IDR = EMAC_RMII_MASK;
00205    //Assign RMII pins to peripheral A function
00206    PIOB->PIO_ABSR &= ~EMAC_RMII_MASK;
00207    //Disable the PIO from controlling the corresponding pins
00208    PIOB->PIO_PDR = EMAC_RMII_MASK;
00209 
00210    //Select RMII operation mode and enable transceiver clock
00211    EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
00212 }
00213 
00214 #endif
00215 
00216 
00217 /**
00218  * @brief Initialize buffer descriptors
00219  * @param[in] interface Underlying network interface
00220  **/
00221 
00222 void sam3xEthInitBufferDesc(NetInterface *interface)
00223 {
00224    uint_t i;
00225    uint32_t address;
00226 
00227    //Initialize TX buffer descriptors
00228    for(i = 0; i < SAM3X_ETH_TX_BUFFER_COUNT; i++)
00229    {
00230       //Calculate the address of the current TX buffer
00231       address = (uint32_t) txBuffer[i];
00232       //Write the address to the descriptor entry
00233       txBufferDesc[i].address = address;
00234       //Initialize status field
00235       txBufferDesc[i].status = EMAC_TX_USED;
00236    }
00237 
00238    //Mark the last descriptor entry with the wrap flag
00239    txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
00240    //Initialize TX buffer index
00241    txBufferIndex = 0;
00242 
00243    //Initialize RX buffer descriptors
00244    for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
00245    {
00246       //Calculate the address of the current RX buffer
00247       address = (uint32_t) rxBuffer[i];
00248       //Write the address to the descriptor entry
00249       rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
00250       //Clear status field
00251       rxBufferDesc[i].status = 0;
00252    }
00253 
00254    //Mark the last descriptor entry with the wrap flag
00255    rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
00256    //Initialize RX buffer index
00257    rxBufferIndex = 0;
00258 
00259    //Start location of the TX descriptor list
00260    EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
00261    //Start location of the RX descriptor list
00262    EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
00263 }
00264 
00265 
00266 /**
00267  * @brief SAM3X Ethernet MAC timer handler
00268  *
00269  * This routine is periodically called by the TCP/IP stack to
00270  * handle periodic operations such as polling the link state
00271  *
00272  * @param[in] interface Underlying network interface
00273  **/
00274 
00275 void sam3xEthTick(NetInterface *interface)
00276 {
00277    //Handle periodic operations
00278    interface->phyDriver->tick(interface);
00279 }
00280 
00281 
00282 /**
00283  * @brief Enable interrupts
00284  * @param[in] interface Underlying network interface
00285  **/
00286 
00287 void sam3xEthEnableIrq(NetInterface *interface)
00288 {
00289    //Enable Ethernet MAC interrupts
00290    NVIC_EnableIRQ(EMAC_IRQn);
00291    //Enable Ethernet PHY interrupts
00292    interface->phyDriver->enableIrq(interface);
00293 }
00294 
00295 
00296 /**
00297  * @brief Disable interrupts
00298  * @param[in] interface Underlying network interface
00299  **/
00300 
00301 void sam3xEthDisableIrq(NetInterface *interface)
00302 {
00303    //Disable Ethernet MAC interrupts
00304    NVIC_DisableIRQ(EMAC_IRQn);
00305    //Disable Ethernet PHY interrupts
00306    interface->phyDriver->disableIrq(interface);
00307 }
00308 
00309 
00310 /**
00311  * @brief SAM3X Ethernet MAC interrupt service routine
00312  **/
00313 
00314 void EMAC_Handler(void)
00315 {
00316    bool_t flag;
00317    volatile uint32_t isr;
00318    volatile uint32_t tsr;
00319    volatile uint32_t rsr;
00320 
00321    //Enter interrupt service routine
00322    osEnterIsr();
00323 
00324    //This flag will be set if a higher priority task must be woken
00325    flag = FALSE;
00326 
00327    //Each time the software reads EMAC_ISR, it has to check the
00328    //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
00329    isr = EMAC->EMAC_ISR;
00330    tsr = EMAC->EMAC_TSR;
00331    rsr = EMAC->EMAC_RSR;
00332 
00333    //A packet has been transmitted?
00334    if(tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
00335       EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR))
00336    {
00337       //Only clear TSR flags that are currently set
00338       EMAC->EMAC_TSR = tsr;
00339 
00340       //Check whether the TX buffer is available for writing
00341       if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
00342       {
00343          //Notify the TCP/IP stack that the transmitter is ready to send
00344          flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
00345       }
00346    }
00347 
00348    //A packet has been received?
00349    if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
00350    {
00351       //Set event flag
00352       nicDriverInterface->nicEvent = TRUE;
00353       //Notify the TCP/IP stack of the event
00354       flag |= osSetEventFromIsr(&netEvent);
00355    }
00356 
00357    //Leave interrupt service routine
00358    osExitIsr(flag);
00359 }
00360 
00361 
00362 /**
00363  * @brief SAM3X Ethernet MAC event handler
00364  * @param[in] interface Underlying network interface
00365  **/
00366 
00367 void sam3xEthEventHandler(NetInterface *interface)
00368 {
00369    error_t error;
00370    uint32_t rsr;
00371 
00372    //Read receive status
00373    rsr = EMAC->EMAC_RSR;
00374 
00375    //Packet received?
00376    if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
00377    {
00378       //Only clear RSR flags that are currently set
00379       EMAC->EMAC_RSR = rsr;
00380 
00381       //Process all pending packets
00382       do
00383       {
00384          //Read incoming packet
00385          error = sam3xEthReceivePacket(interface);
00386 
00387          //No more data in the receive buffer?
00388       } while(error != ERROR_BUFFER_EMPTY);
00389    }
00390 }
00391 
00392 
00393 /**
00394  * @brief Send a packet
00395  * @param[in] interface Underlying network interface
00396  * @param[in] buffer Multi-part buffer containing the data to send
00397  * @param[in] offset Offset to the first data byte
00398  * @return Error code
00399  **/
00400 
00401 error_t sam3xEthSendPacket(NetInterface *interface,
00402    const NetBuffer *buffer, size_t offset)
00403 {
00404    size_t length;
00405 
00406    //Retrieve the length of the packet
00407    length = netBufferGetLength(buffer) - offset;
00408 
00409    //Check the frame length
00410    if(length > SAM3X_ETH_TX_BUFFER_SIZE)
00411    {
00412       //The transmitter can accept another packet
00413       osSetEvent(&interface->nicTxEvent);
00414       //Report an error
00415       return ERROR_INVALID_LENGTH;
00416    }
00417 
00418    //Make sure the current buffer is available for writing
00419    if(!(txBufferDesc[txBufferIndex].status & EMAC_TX_USED))
00420       return ERROR_FAILURE;
00421 
00422    //Copy user data to the transmit buffer
00423    netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
00424 
00425    //Set the necessary flags in the descriptor entry
00426    if(txBufferIndex < (SAM3X_ETH_TX_BUFFER_COUNT - 1))
00427    {
00428       //Write the status word
00429       txBufferDesc[txBufferIndex].status =
00430          EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
00431 
00432       //Point to the next buffer
00433       txBufferIndex++;
00434    }
00435    else
00436    {
00437       //Write the status word
00438       txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP |
00439          EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
00440 
00441       //Wrap around
00442       txBufferIndex = 0;
00443    }
00444 
00445    //Set the TSTART bit to initiate transmission
00446    EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
00447 
00448    //Check whether the next buffer is available for writing
00449    if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
00450    {
00451       //The transmitter can accept another packet
00452       osSetEvent(&interface->nicTxEvent);
00453    }
00454 
00455    //Successful processing
00456    return NO_ERROR;
00457 }
00458 
00459 
00460 /**
00461  * @brief Receive a packet
00462  * @param[in] interface Underlying network interface
00463  * @return Error code
00464  **/
00465 
00466 error_t sam3xEthReceivePacket(NetInterface *interface)
00467 {
00468    static uint8_t temp[ETH_MAX_FRAME_SIZE];
00469    error_t error;
00470    uint_t i;
00471    uint_t j;
00472    uint_t sofIndex;
00473    uint_t eofIndex;
00474    size_t n;
00475    size_t size;
00476    size_t length;
00477 
00478    //Initialize SOF and EOF indices
00479    sofIndex = UINT_MAX;
00480    eofIndex = UINT_MAX;
00481 
00482    //Search for SOF and EOF flags
00483    for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
00484    {
00485       //Point to the current entry
00486       j = rxBufferIndex + i;
00487 
00488       //Wrap around to the beginning of the buffer if necessary
00489       if(j >= SAM3X_ETH_RX_BUFFER_COUNT)
00490          j -= SAM3X_ETH_RX_BUFFER_COUNT;
00491 
00492       //No more entries to process?
00493       if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
00494       {
00495          //Stop processing
00496          break;
00497       }
00498       //A valid SOF has been found?
00499       if(rxBufferDesc[j].status & EMAC_RX_SOF)
00500       {
00501          //Save the position of the SOF
00502          sofIndex = i;
00503       }
00504       //A valid EOF has been found?
00505       if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
00506       {
00507          //Save the position of the EOF
00508          eofIndex = i;
00509          //Retrieve the length of the frame
00510          size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
00511          //Limit the number of data to read
00512          size = MIN(size, ETH_MAX_FRAME_SIZE);
00513          //Stop processing since we have reached the end of the frame
00514          break;
00515       }
00516    }
00517 
00518    //Determine the number of entries to process
00519    if(eofIndex != UINT_MAX)
00520       j = eofIndex + 1;
00521    else if(sofIndex != UINT_MAX)
00522       j = sofIndex;
00523    else
00524       j = i;
00525 
00526    //Total number of bytes that have been copied from the receive buffer
00527    length = 0;
00528 
00529    //Process incoming frame
00530    for(i = 0; i < j; i++)
00531    {
00532       //Any data to copy from current buffer?
00533       if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
00534       {
00535          //Calculate the number of bytes to read at a time
00536          n = MIN(size, SAM3X_ETH_RX_BUFFER_SIZE);
00537          //Copy data from receive buffer
00538          memcpy(temp + length, rxBuffer[rxBufferIndex], n);
00539          //Update byte counters
00540          length += n;
00541          size -= n;
00542       }
00543 
00544       //Mark the current buffer as free
00545       rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
00546 
00547       //Point to the following entry
00548       rxBufferIndex++;
00549 
00550       //Wrap around to the beginning of the buffer if necessary
00551       if(rxBufferIndex >= SAM3X_ETH_RX_BUFFER_COUNT)
00552          rxBufferIndex = 0;
00553    }
00554 
00555    //Any packet to process?
00556    if(length > 0)
00557    {
00558       //Pass the packet to the upper layer
00559       nicProcessPacket(interface, temp, length);
00560       //Valid packet received
00561       error = NO_ERROR;
00562    }
00563    else
00564    {
00565       //No more data in the receive buffer
00566       error = ERROR_BUFFER_EMPTY;
00567    }
00568 
00569    //Return status code
00570    return error;
00571 }
00572 
00573 
00574 /**
00575  * @brief Configure multicast MAC address filtering
00576  * @param[in] interface Underlying network interface
00577  * @return Error code
00578  **/
00579 
00580 error_t sam3xEthSetMulticastFilter(NetInterface *interface)
00581 {
00582    uint_t i;
00583    uint_t k;
00584    uint8_t *p;
00585    uint32_t hashTable[2];
00586    MacFilterEntry *entry;
00587 
00588    //Debug message
00589    TRACE_DEBUG("Updating SAM3X hash table...\r\n");
00590 
00591    //Clear hash table
00592    hashTable[0] = 0;
00593    hashTable[1] = 0;
00594 
00595    //The MAC filter table contains the multicast MAC addresses
00596    //to accept when receiving an Ethernet frame
00597    for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
00598    {
00599       //Point to the current entry
00600       entry = &interface->macMulticastFilter[i];
00601 
00602       //Valid entry?
00603       if(entry->refCount > 0)
00604       {
00605          //Point to the MAC address
00606          p = entry->addr.b;
00607 
00608          //Apply the hash function
00609          k = (p[0] >> 6) ^ p[0];
00610          k ^= (p[1] >> 4) ^ (p[1] << 2);
00611          k ^= (p[2] >> 2) ^ (p[2] << 4);
00612          k ^= (p[3] >> 6) ^ p[3];
00613          k ^= (p[4] >> 4) ^ (p[4] << 2);
00614          k ^= (p[5] >> 2) ^ (p[5] << 4);
00615 
00616          //The hash value is reduced to a 6-bit index
00617          k &= 0x3F;
00618 
00619          //Update hash table contents
00620          hashTable[k / 32] |= (1 << (k % 32));
00621       }
00622    }
00623 
00624    //Write the hash table
00625    EMAC->EMAC_HRB = hashTable[0];
00626    EMAC->EMAC_HRT = hashTable[1];
00627 
00628    //Debug message
00629    TRACE_DEBUG("  HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
00630    TRACE_DEBUG("  HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
00631 
00632    //Successful processing
00633    return NO_ERROR;
00634 }
00635 
00636 
00637 /**
00638  * @brief Adjust MAC configuration parameters for proper operation
00639  * @param[in] interface Underlying network interface
00640  * @return Error code
00641  **/
00642 
00643 error_t sam3xEthUpdateMacConfig(NetInterface *interface)
00644 {
00645    uint32_t config;
00646 
00647    //Read network configuration register
00648    config = EMAC->EMAC_NCFGR;
00649 
00650    //10BASE-T or 100BASE-TX operation mode?
00651    if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
00652       config |= EMAC_NCFGR_SPD;
00653    else
00654       config &= ~EMAC_NCFGR_SPD;
00655 
00656    //Half-duplex or full-duplex mode?
00657    if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
00658       config |= EMAC_NCFGR_FD;
00659    else
00660       config &= ~EMAC_NCFGR_FD;
00661 
00662    //Write configuration value back to NCFGR register
00663    EMAC->EMAC_NCFGR = config;
00664 
00665    //Successful processing
00666    return NO_ERROR;
00667 }
00668 
00669 
00670 /**
00671  * @brief Write PHY register
00672  * @param[in] phyAddr PHY address
00673  * @param[in] regAddr Register address
00674  * @param[in] data Register value
00675  **/
00676 
00677 void sam3xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
00678 {
00679    uint32_t value;
00680 
00681    //Set up a write operation
00682    value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
00683    //PHY address
00684    value |= EMAC_MAN_PHYA(phyAddr);
00685    //Register address
00686    value |= EMAC_MAN_REGA(regAddr);
00687    //Register value
00688    value |= EMAC_MAN_DATA(data);
00689 
00690    //Start a write operation
00691    EMAC->EMAC_MAN = value;
00692    //Wait for the write to complete
00693    while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
00694 }
00695 
00696 
00697 /**
00698  * @brief Read PHY register
00699  * @param[in] phyAddr PHY address
00700  * @param[in] regAddr Register address
00701  * @return Register value
00702  **/
00703 
00704 uint16_t sam3xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
00705 {
00706    uint32_t value;
00707 
00708    //Set up a read operation
00709    value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
00710    //PHY address
00711    value |= EMAC_MAN_PHYA(phyAddr);
00712    //Register address
00713    value |= EMAC_MAN_REGA(regAddr);
00714 
00715    //Start a read operation
00716    EMAC->EMAC_MAN = value;
00717    //Wait for the read to complete
00718    while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
00719 
00720    //Return PHY register contents
00721    return EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
00722 }
00723