s7g2_eth.h

00001 /**
00002  * @file s7g2_eth.h
00003  * @brief Renesas Synergy S7G2 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _S7G2_ETH_H
00030 #define _S7G2_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef S7G2_ETH_TX_BUFFER_COUNT
00037    #define S7G2_ETH_TX_BUFFER_COUNT 3
00038 #elif (S7G2_ETH_TX_BUFFER_COUNT < 1)
00039    #error S7G2_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef S7G2_ETH_TX_BUFFER_SIZE
00044    #define S7G2_ETH_TX_BUFFER_SIZE 1536
00045 #elif (S7G2_ETH_TX_BUFFER_SIZE != 1536)
00046    #error S7G2_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef S7G2_ETH_RX_BUFFER_COUNT
00051    #define S7G2_ETH_RX_BUFFER_COUNT 6
00052 #elif (S7G2_ETH_RX_BUFFER_COUNT < 1)
00053    #error S7G2_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef S7G2_ETH_RX_BUFFER_SIZE
00058    #define S7G2_ETH_RX_BUFFER_SIZE 1536
00059 #elif (S7G2_ETH_RX_BUFFER_SIZE != 1536)
00060    #error S7G2_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Interrupt priority grouping
00064 #ifndef S7G2_ETH_IRQ_PRIORITY_GROUPING
00065    #define S7G2_ETH_IRQ_PRIORITY_GROUPING 3
00066 #elif (S7G2_ETH_IRQ_PRIORITY_GROUPING < 0)
00067    #error S7G2_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
00068 #endif
00069 
00070 //Ethernet interrupt group priority
00071 #ifndef S7G2_ETH_IRQ_GROUP_PRIORITY
00072    #define S7G2_ETH_IRQ_GROUP_PRIORITY 12
00073 #elif (S7G2_ETH_IRQ_GROUP_PRIORITY < 0)
00074    #error S7G2_ETH_IRQ_GROUP_PRIORITY parameter is not valid
00075 #endif
00076 
00077 //Ethernet interrupt subpriority
00078 #ifndef S7G2_ETH_IRQ_SUB_PRIORITY
00079    #define S7G2_ETH_IRQ_SUB_PRIORITY 0
00080 #elif (S7G2_ETH_IRQ_SUB_PRIORITY < 0)
00081    #error S7G2_ETH_IRQ_SUB_PRIORITY parameter is not valid
00082 #endif
00083 
00084 //EESR register
00085 #define EDMAC_EESR_TWB     0x40000000
00086 #define EDMAC_EESR_TABT    0x04000000
00087 #define EDMAC_EESR_RABT    0x02000000
00088 #define EDMAC_EESR_RFCOF   0x01000000
00089 #define EDMAC_EESR_ADE     0x00800000
00090 #define EDMAC_EESR_ECI     0x00400000
00091 #define EDMAC_EESR_TC      0x00200000
00092 #define EDMAC_EESR_TDE     0x00100000
00093 #define EDMAC_EESR_TFUF    0x00080000
00094 #define EDMAC_EESR_FR      0x00040000
00095 #define EDMAC_EESR_RDE     0x00020000
00096 #define EDMAC_EESR_RFOF    0x00010000
00097 #define EDMAC_EESR_CND     0x00000800
00098 #define EDMAC_EESR_DLC     0x00000400
00099 #define EDMAC_EESR_CD      0x00000200
00100 #define EDMAC_EESR_TRO     0x00000100
00101 #define EDMAC_EESR_RMAF    0x00000080
00102 #define EDMAC_EESR_RRF     0x00000010
00103 #define EDMAC_EESR_RTLF    0x00000008
00104 #define EDMAC_EESR_RTSF    0x00000004
00105 #define EDMAC_EESR_PRE     0x00000002
00106 #define EDMAC_EESR_CERF    0x00000001
00107 
00108 //Transmit DMA descriptor flags
00109 #define EDMAC_TD0_TACT     0x80000000
00110 #define EDMAC_TD0_TDLE     0x40000000
00111 #define EDMAC_TD0_TFP_SOF  0x20000000
00112 #define EDMAC_TD0_TFP_EOF  0x10000000
00113 #define EDMAC_TD0_TFE      0x08000000
00114 #define EDMAC_TD0_TWBI     0x04000000
00115 #define EDMAC_TD0_TFS_MASK 0x0000010F
00116 #define EDMAC_TD0_TFS_TABT 0x00000100
00117 #define EDMAC_TD0_TFS_CND  0x00000008
00118 #define EDMAC_TD0_TFS_DLC  0x00000004
00119 #define EDMAC_TD0_TFS_CD   0x00000002
00120 #define EDMAC_TD0_TFS_TRO  0x00000001
00121 #define EDMAC_TD1_TBL      0xFFFF0000
00122 #define EDMAC_TD2_TBA      0xFFFFFFFF
00123 
00124 //Receive DMA descriptor flags
00125 #define EDMAC_RD0_RACT     0x80000000
00126 #define EDMAC_RD0_RDLE     0x40000000
00127 #define EDMAC_RD0_RFP_SOF  0x20000000
00128 #define EDMAC_RD0_RFP_EOF  0x10000000
00129 #define EDMAC_RD0_RFE      0x08000000
00130 #define EDMAC_RD0_RFS_MASK 0x0000039F
00131 #define EDMAC_RD0_RFS_RFOF 0x00000200
00132 #define EDMAC_RD0_RFS_RABT 0x00000100
00133 #define EDMAC_RD0_RFS_RMAF 0x00000080
00134 #define EDMAC_RD0_RFS_RRF  0x00000010
00135 #define EDMAC_RD0_RFS_RTLF 0x00000008
00136 #define EDMAC_RD0_RFS_RTSF 0x00000004
00137 #define EDMAC_RD0_RFS_PRE  0x00000002
00138 #define EDMAC_RD0_RFS_CERF 0x00000001
00139 #define EDMAC_RD1_RBL      0xFFFF0000
00140 #define EDMAC_RD1_RFL      0x0000FFFF
00141 #define EDMAC_RD2_RBA      0xFFFFFFFF
00142 
00143 //Serial Management Interface
00144 #define SMI_SYNC           0xFFFFFFFF
00145 #define SMI_START          0x00000001
00146 #define SMI_WRITE          0x00000001
00147 #define SMI_READ           0x00000002
00148 #define SMI_TA             0x00000002
00149 
00150 
00151 /**
00152  * @brief Transmit DMA descriptor
00153  **/
00154 
00155 typedef struct
00156 {
00157    uint32_t td0;
00158    uint32_t td1;
00159    uint32_t td2;
00160    uint32_t padding;
00161 } S7g2TxDmaDesc;
00162 
00163 
00164 /**
00165  * @brief Receive DMA descriptor
00166  **/
00167 
00168 typedef struct
00169 {
00170    uint32_t rd0;
00171    uint32_t rd1;
00172    uint32_t rd2;
00173    uint32_t padding;
00174 } S7g2RxDmaDesc;
00175 
00176 
00177 //S7G2 Ethernet MAC driver
00178 extern const NicDriver s7g2EthDriver;
00179 
00180 //S7G2 Ethernet MAC related functions
00181 error_t s7g2EthInit(NetInterface *interface);
00182 void s7g2EthInitGpio(NetInterface *interface);
00183 void s7g2EthInitDmaDesc(NetInterface *interface);
00184 
00185 void s7g2EthTick(NetInterface *interface);
00186 
00187 void s7g2EthEnableIrq(NetInterface *interface);
00188 void s7g2EthDisableIrq(NetInterface *interface);
00189 void s7g2EthEventHandler(NetInterface *interface);
00190 
00191 error_t s7g2EthSendPacket(NetInterface *interface,
00192    const NetBuffer *buffer, size_t offset);
00193 
00194 error_t s7g2EthReceivePacket(NetInterface *interface);
00195 
00196 error_t s7g2EthSetMulticastFilter(NetInterface *interface);
00197 error_t s7g2EthUpdateMacConfig(NetInterface *interface);
00198 
00199 void s7g2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00200 uint16_t s7g2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00201 
00202 void s7g2EthWriteSmi(uint32_t data, uint_t length);
00203 uint32_t s7g2EthReadSmi(uint_t length);
00204 
00205 #endif
00206