rza1_eth.h

00001 /**
00002  * @file rza1_eth.h
00003  * @brief Renesas RZ/A1 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _RZA1_ETH_H
00030 #define _RZA1_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef RZA1_ETH_TX_BUFFER_COUNT
00037    #define RZA1_ETH_TX_BUFFER_COUNT 8
00038 #elif (RZA1_ETH_TX_BUFFER_COUNT < 1)
00039    #error RZA1_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef RZA1_ETH_TX_BUFFER_SIZE
00044    #define RZA1_ETH_TX_BUFFER_SIZE 1536
00045 #elif (RZA1_ETH_TX_BUFFER_SIZE != 1536)
00046    #error RZA1_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef RZA1_ETH_RX_BUFFER_COUNT
00051    #define RZA1_ETH_RX_BUFFER_COUNT 8
00052 #elif (RZA1_ETH_RX_BUFFER_COUNT < 1)
00053    #error RZA1_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef RZA1_ETH_RX_BUFFER_SIZE
00058    #define RZA1_ETH_RX_BUFFER_SIZE 1536
00059 #elif (RZA1_ETH_RX_BUFFER_SIZE != 1536)
00060    #error RZA1_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Ethernet interrupt priority
00064 #ifndef RZA1_ETH_IRQ_PRIORITY
00065    #define RZA1_ETH_IRQ_PRIORITY 25
00066 #elif (RZA1_ETH_IRQ_PRIORITY < 0)
00067    #error RZA1_ETH_IRQ_PRIORITY parameter is not valid
00068 #endif
00069 
00070 //ARSTR register
00071 #define ETHER_ARSTR_ARST         0x00000001
00072 
00073 //ECMR0 register
00074 #define ETH_ECMR0_TRCCM          0x04000000
00075 #define ETH_ECMR0_RCSC           0x00800000
00076 #define ETH_ECMR0_DPAD           0x00200000
00077 #define ETH_ECMR0_RZPF           0x00100000
00078 #define ETH_ECMR0_ZPF            0x00080000
00079 #define ETH_ECMR0_PFR            0x00040000
00080 #define ETH_ECMR0_RXF            0x00020000
00081 #define ETH_ECMR0_TXF            0x00010000
00082 #define ETH_ECMR0_MCT            0x00002000
00083 #define ETH_ECMR0_RE             0x00000040
00084 #define ETH_ECMR0_TE             0x00000020
00085 #define ETH_ECMR0_DM             0x00000002
00086 #define ETH_ECMR0_PRM            0x00000001
00087 
00088 //PIR0 register
00089 #define ETHER_PIR0_MDI           0x00000008
00090 #define ETHER_PIR0_MDO           0x00000004
00091 #define ETHER_PIR0_MMD           0x00000002
00092 #define ETHER_PIR0_MDC           0x00000001
00093 
00094 //TSU_ADSBSY register
00095 #define ETHER_TSU_ADSBSY_ADSBSY  0x00000001
00096 
00097 //EDSR0 register
00098 #define ETHER_EDSR0_ENT          0x00000002
00099 #define ETHER_EDSR0_ENR          0x00000001
00100 
00101 //EDMR0 register
00102 #define ETHER_EDMR0_DE           0x00000040
00103 #define ETHER_EDMR0_DL           0x00000030
00104 #define ETHER_EDMR0_SWRT         0x00000002
00105 #define ETHER_EDMR0_SWRR         0x00000001
00106 
00107 #define ETHER_EDMR0_DL_16        0x00000000
00108 #define ETHER_EDMR0_DL_32        0x00000010
00109 #define ETHER_EDMR0_DL_64        0x00000020
00110 
00111 //EDTRR0 register
00112 #define ETHER_EDTRR0_TR          0x00000003
00113 
00114 //EDRRR0 register
00115 #define ETHER_EDRRR0_RR          0x00000001
00116 
00117 //EESR0 register
00118 #define ETHER_EESR0_TWB          0xC0000000
00119 #define ETHER_EESR0_TC1          0x20000000
00120 #define ETHER_EESR0_TUC          0x10000000
00121 #define ETHER_EESR0_ROC          0x08000000
00122 #define ETHER_EESR0_TABT         0x04000000
00123 #define ETHER_EESR0_RABT         0x02000000
00124 #define ETHER_EESR0_RFCOF        0x01000000
00125 #define ETHER_EESR0_ECI          0x00400000
00126 #define ETHER_EESR0_TC0          0x00200000
00127 #define ETHER_EESR0_TDE          0x00100000
00128 #define ETHER_EESR0_TFUF         0x00080000
00129 #define ETHER_EESR0_FR           0x00040000
00130 #define ETHER_EESR0_RDE          0x00020000
00131 #define ETHER_EESR0_RFOF         0x00010000
00132 #define ETHER_EESR0_RMAF         0x00000080
00133 #define ETHER_EESR0_RRF          0x00000010
00134 #define ETHER_EESR0_RTLF         0x00000008
00135 #define ETHER_EESR0_RTSF         0x00000004
00136 #define ETHER_EESR0_PRE          0x00000002
00137 #define ETHER_EESR0_CERF         0x00000001
00138 
00139 //EESIPR0 register
00140 #define ETHER_EESIPR0_TWBIP      0xC0000000
00141 #define ETHER_EESIPR0_TC1IP      0x20000000
00142 #define ETHER_EESIPR0_TUCIP      0x10000000
00143 #define ETHER_EESIPR0_ROCIP      0x08000000
00144 #define ETHER_EESIPR0_TABTIP     0x04000000
00145 #define ETHER_EESIPR0_RABTIP     0x02000000
00146 #define ETHER_EESIPR0_RFCOFIP    0x01000000
00147 #define ETHER_EESIPR0_ECIIP      0x00400000
00148 #define ETHER_EESIPR0_TC0IP      0x00200000
00149 #define ETHER_EESIPR0_TDEIP      0x00100000
00150 #define ETHER_EESIPR0_TFUFIP     0x00080000
00151 #define ETHER_EESIPR0_FRIP       0x00040000
00152 #define ETHER_EESIPR0_RDEIP      0x00020000
00153 #define ETHER_EESIPR0_RFOFIP     0x00010000
00154 #define ETHER_EESIPR0_RMAFIP     0x00000080
00155 #define ETHER_EESIPR0_RRFIP      0x00000010
00156 #define ETHER_EESIPR0_RTLFIP     0x00000008
00157 #define ETHER_EESIPR0_RTSFIP     0x00000004
00158 #define ETHER_EESIPR0_PREIP      0x00000002
00159 #define ETHER_EESIPR0_CERFIP     0x00000001
00160 
00161 //TDFFR0 register
00162 #define ETHER_TDFFR_TDLF         0x00000001
00163 
00164 //RDFFR0 register
00165 #define ETHER_RDFFR0_RDLF        0x00000001
00166 
00167 //FDR0 register
00168 #define ETHER_FDR0_TFD           0x00000700
00169 #define ETHER_FDR0_RFD           0X0000001F
00170 
00171 #define ETHER_FDR0_TFD_2048      0x00000700
00172 #define ETHER_FDR0_RFD_2048      0x00000007
00173 
00174 //RMCR0 register
00175 #define ETHER_RMCR0_RNC          0x00000001
00176 
00177 //FCFTR register
00178 #define ETHER_FCFTR0_RFF         0x001F0000
00179 #define ETHER_FCFTR0_RFD         0x000000FF
00180 
00181 #define ETHER_FCFTR0_RFF_8       0x00070000
00182 #define ETHER_FCFTR0_RFD_2048    0x00000007
00183 
00184 //Transmit DMA descriptor flags
00185 #define ETHER_TD0_TACT           0x80000000
00186 #define ETHER_TD0_TDLE           0x40000000
00187 #define ETHER_TD0_TFP_SOF        0x20000000
00188 #define ETHER_TD0_TFP_EOF        0x10000000
00189 #define ETHER_TD0_TFE            0x08000000
00190 #define ETHER_TD0_TWBI           0x04000000
00191 #define ETHER_TD0_TFS_MASK       0x00000300
00192 #define ETHER_TD0_TFS_TUC        0x00000200
00193 #define ETHER_TD0_TFS_TABT       0x00000100
00194 #define ETHER_TD1_TDL            0xFFFF0000
00195 #define ETHER_TD2_TBA            0xFFFFFFFF
00196 
00197 //Receive DMA descriptor flags
00198 #define ETHER_RD0_RACT           0x80000000
00199 #define ETHER_RD0_RDLE           0x40000000
00200 #define ETHER_RD0_RFP_SOF        0x20000000
00201 #define ETHER_RD0_RFP_EOF        0x10000000
00202 #define ETHER_RD0_RFE            0x08000000
00203 #define ETHER_RD0_RCSE           0x04000000
00204 #define ETHER_RD0_RFS_MASK       0x02DF0000
00205 #define ETHER_RD0_RFS_RFOF       0x02000000
00206 #define ETHER_RD0_RFS_RMAF       0x00800000
00207 #define ETHER_RD0_RFS_RUAF       0x00400000
00208 #define ETHER_RD0_RFS_RRF        0x00100000
00209 #define ETHER_RD0_RFS_RTLF       0x00080000
00210 #define ETHER_RD0_RFS_RTSF       0x00040000
00211 #define ETHER_RD0_RFS_PRE        0x00020000
00212 #define ETHER_RD0_RFS_CERF       0x00010000
00213 #define ETHER_RD0_RCS            0x0000FFFF
00214 #define ETHER_RD1_RBL            0xFFFF0000
00215 #define ETHER_RD1_RDL            0x0000FFFF
00216 #define ETHER_RD2_RBA            0xFFFFFFFF
00217 
00218 //Serial Management Interface
00219 #define SMI_SYNC                 0xFFFFFFFF
00220 #define SMI_START                0x00000001
00221 #define SMI_WRITE                0x00000001
00222 #define SMI_READ                 0x00000002
00223 #define SMI_TA                   0x00000002
00224 
00225 
00226 /**
00227  * @brief Transmit DMA descriptor
00228  **/
00229 
00230 typedef struct
00231 {
00232    uint32_t td0;
00233    uint32_t td1;
00234    uint32_t td2;
00235    uint32_t padding;
00236 } Rza1TxDmaDesc;
00237 
00238 
00239 /**
00240  * @brief Receive DMA descriptor
00241  **/
00242 
00243 typedef struct
00244 {
00245    uint32_t rd0;
00246    uint32_t rd1;
00247    uint32_t rd2;
00248    uint32_t padding;
00249 } Rza1RxDmaDesc;
00250 
00251 
00252 //RZ/A1 Ethernet MAC driver
00253 extern const NicDriver rza1EthDriver;
00254 
00255 //RZ/A1 Ethernet MAC related functions
00256 error_t rza1EthInit(NetInterface *interface);
00257 void rza1EthInitGpio(NetInterface *interface);
00258 void rza1EthInitDmaDesc(NetInterface *interface);
00259 
00260 void rza1EthTick(NetInterface *interface);
00261 
00262 void rza1EthEnableIrq(NetInterface *interface);
00263 void rza1EthDisableIrq(NetInterface *interface);
00264 void rza1EthIrqHandler(uint32_t intSense);
00265 void rza1EthEventHandler(NetInterface *interface);
00266 
00267 error_t rza1EthSendPacket(NetInterface *interface,
00268    const NetBuffer *buffer, size_t offset);
00269 
00270 error_t rza1EthReceivePacket(NetInterface *interface);
00271 
00272 error_t rza1EthSetMulticastFilter(NetInterface *interface);
00273 error_t rza1EthUpdateMacConfig(NetInterface *interface);
00274 
00275 void rza1EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00276 uint16_t rza1EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00277 
00278 void rza1EthWriteSmi(uint32_t data, uint_t length);
00279 uint32_t rza1EthReadSmi(uint_t length);
00280 
00281 #endif
00282