pic32mz_eth.h

00001 /**
00002  * @file pic32mz_eth.h
00003  * @brief PIC32MZ Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _PIC32MZ_ETH_H
00030 #define _PIC32MZ_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef PIC32MZ_ETH_TX_BUFFER_COUNT
00037    #define PIC32MZ_ETH_TX_BUFFER_COUNT 3
00038 #elif (PIC32MZ_ETH_TX_BUFFER_COUNT < 1)
00039    #error PIC32MZ_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef PIC32MZ_ETH_TX_BUFFER_SIZE
00044    #define PIC32MZ_ETH_TX_BUFFER_SIZE 1536
00045 #elif (PIC32MZ_ETH_TX_BUFFER_SIZE != 1536)
00046    #error PIC32MZ_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef PIC32MZ_ETH_RX_BUFFER_COUNT
00051    #define PIC32MZ_ETH_RX_BUFFER_COUNT 6
00052 #elif (PIC32MZ_ETH_RX_BUFFER_COUNT < 1)
00053    #error PIC32MZ_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef PIC32MZ_ETH_RX_BUFFER_SIZE
00058    #define PIC32MZ_ETH_RX_BUFFER_SIZE 1536
00059 #elif (PIC32MZ_ETH_RX_BUFFER_SIZE != 1536)
00060    #error PIC32MZ_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Ethernet interrupt priority
00064 #ifndef PIC32MZ_ETH_IRQ_PRIORITY
00065    #define PIC32MZ_ETH_IRQ_PRIORITY 2
00066 #elif (PIC32MZ_ETH_IRQ_PRIORITY < 0)
00067    #error PIC32MZ_ETH_IRQ_PRIORITY parameter is not valid
00068 #endif
00069 
00070 //Ethernet interrupt subpriority
00071 #ifndef PIC32MZ_ETH_IRQ_SUB_PRIORITY
00072    #define PIC32MZ_ETH_IRQ_SUB_PRIORITY 0
00073 #elif (PIC32MZ_ETH_IRQ_SUB_PRIORITY < 0)
00074    #error PIC32MZ_ETH_IRQ_SUB_PRIORITY parameter is not valid
00075 #endif
00076 
00077 //EMAC1MCFG register
00078 #define _EMAC1MCFG_CLKSEL_DIV4  (0 << _EMAC1MCFG_CLKSEL_POSITION)
00079 #define _EMAC1MCFG_CLKSEL_DIV6  (2 << _EMAC1MCFG_CLKSEL_POSITION)
00080 #define _EMAC1MCFG_CLKSEL_DIV8  (3 << _EMAC1MCFG_CLKSEL_POSITION)
00081 #define _EMAC1MCFG_CLKSEL_DIV10 (4 << _EMAC1MCFG_CLKSEL_POSITION)
00082 #define _EMAC1MCFG_CLKSEL_DIV14 (5 << _EMAC1MCFG_CLKSEL_POSITION)
00083 #define _EMAC1MCFG_CLKSEL_DIV20 (6 << _EMAC1MCFG_CLKSEL_POSITION)
00084 #define _EMAC1MCFG_CLKSEL_DIV28 (7 << _EMAC1MCFG_CLKSEL_POSITION)
00085 #define _EMAC1MCFG_CLKSEL_DIV40 (8 << _EMAC1MCFG_CLKSEL_POSITION)
00086 #define _EMAC1MCFG_CLKSEL_DIV48 (9 << _EMAC1MCFG_CLKSEL_POSITION)
00087 #define _EMAC1MCFG_CLKSEL_DIV50 (10 << _EMAC1MCFG_CLKSEL_POSITION)
00088 
00089 //Transmit buffer descriptor flags
00090 #define ETH_TX_CTRL_SOP                   0x80000000
00091 #define ETH_TX_CTRL_EOP                   0x40000000
00092 #define ETH_TX_CTRL_BYTE_COUNT            0x07FF0000
00093 #define ETH_TX_CTRL_NPV                   0x00000100
00094 #define ETH_TX_CTRL_EOWN                  0x00000080
00095 #define ETH_TX_STATUS1_VLAN               0x00080000
00096 #define ETH_TX_STATUS1_BACKPRESSURE       0x00040000
00097 #define ETH_TX_STATUS1_PAUSE              0x00020000
00098 #define ETH_TX_STATUS1_CONTROL            0x00010000
00099 #define ETH_TX_STATUS1_TOTAL_BYTES        0x0000FFFF
00100 #define ETH_TX_STATUS2_UNDERRUN           0x80000000
00101 #define ETH_TX_STATUS2_GIANT              0x40000000
00102 #define ETH_TX_STATUS2_LATE_COL           0x20000000
00103 #define ETH_TX_STATUS2_MAX_COL            0x10000000
00104 #define ETH_TX_STATUS2_EXCESSIVE_DEFER    0x08000000
00105 #define ETH_TX_STATUS2_PACKET_DEFER       0x04000000
00106 #define ETH_TX_STATUS2_BROADCAST          0x02000000
00107 #define ETH_TX_STATUS2_MULTICAST          0x01000000
00108 #define ETH_TX_STATUS2_DONE               0x00800000
00109 #define ETH_TX_STATUS2_LEN_OUT_OF_RANGE   0x00400000
00110 #define ETH_TX_STATUS2_LEN_CHECK_ERROR    0x00200000
00111 #define ETH_TX_STATUS2_CRC_ERROR          0x00100000
00112 #define ETH_TX_STATUS2_COL_COUNT          0x000F0000
00113 #define ETH_TX_STATUS2_BYTE_COUNT         0x0000FFFF
00114 
00115 //Receive buffer descriptor flags
00116 #define ETH_RX_CTRL_SOP                   0x80000000
00117 #define ETH_RX_CTRL_EOP                   0x40000000
00118 #define ETH_RX_CTRL_BYTE_COUNT            0x07FF0000
00119 #define ETH_RX_CTRL_NPV                   0x00000100
00120 #define ETH_RX_CTRL_EOWN                  0x00000080
00121 #define ETH_RX_STATUS1_MULTICAST_MATCH    0x80000000
00122 #define ETH_RX_STATUS1_BROADCAST_MATCH    0x40000000
00123 #define ETH_RX_STATUS1_UNICAST_MATCH      0x20000000
00124 #define ETH_RX_STATUS1_PATTERN_MATCH      0x10000000
00125 #define ETH_RX_STATUS1_MAGIC_PACKET_MATCH 0x08000000
00126 #define ETH_RX_STATUS1_HASH_TABLE_MATCH   0x04000000
00127 #define ETH_RX_STATUS1_NOT_MATCH          0x02000000
00128 #define ETH_RX_STATUS1_RUNT_PACKET        0x01000000
00129 #define ETH_RX_STATUS1_PACKET_CHECKSUM    0x0000FFFF
00130 #define ETH_RX_STATUS2_VLAN               0x40000000
00131 #define ETH_RX_STATUS2_UNKNOWN_OP_CODE    0x20000000
00132 #define ETH_RX_STATUS2_PAUSE              0x10000000
00133 #define ETH_RX_STATUS2_CONTROL            0x08000000
00134 #define ETH_RX_STATUS2_DRIBBLE_NIBBLE     0x04000000
00135 #define ETH_RX_STATUS2_BROADCAST          0x02000000
00136 #define ETH_RX_STATUS2_MULTICAST          0x01000000
00137 #define ETH_RX_STATUS2_OK                 0x00800000
00138 #define ETH_RX_STATUS2_LEN_OUT_OF_RANGE   0x00400000
00139 #define ETH_RX_STATUS2_LEN_CHECK_ERROR    0x00200000
00140 #define ETH_RX_STATUS2_CRC_ERROR          0x00100000
00141 #define ETH_RX_STATUS2_CODE_VIOLATION     0x00080000
00142 #define ETH_RX_STATUS2_CARRIER_EVENT      0x00040000
00143 #define ETH_RX_STATUS2_RXDV_EVENT         0x00020000
00144 #define ETH_RX_STATUS2_LONG_EVENT         0x00010000
00145 #define ETH_RX_STATUS2_BYTE_COUNT         0x0000FFFF
00146 
00147 
00148 /**
00149  * @brief TX buffer descriptor
00150  **/
00151 
00152 typedef struct
00153 {
00154    uint32_t control;
00155    uint32_t address;
00156    uint32_t status1;
00157    uint32_t status2;
00158    uint32_t next;
00159 } Pic32mzTxBufferDesc;
00160 
00161 
00162 /**
00163  * @brief RX buffer descriptor
00164  **/
00165 
00166 typedef struct
00167 {
00168    uint32_t control;
00169    uint32_t address;
00170    uint32_t status1;
00171    uint32_t status2;
00172    uint32_t next;
00173 } Pic32mzRxBufferDesc;
00174 
00175 
00176 //PIC32MZ Ethernet MAC driver
00177 extern const NicDriver pic32mzEthDriver;
00178 
00179 //PIC32MZ Ethernet MAC related functions
00180 error_t pic32mzEthInit(NetInterface *interface);
00181 void pic32mzEthInitGpio(NetInterface *interface);
00182 void pic32mzEthInitBufferDesc(NetInterface *interface);
00183 
00184 void pic32mzEthTick(NetInterface *interface);
00185 
00186 void pic32mzEthEnableIrq(NetInterface *interface);
00187 void pic32mzEthDisableIrq(NetInterface *interface);
00188 void pic32mzEthIrqHandler(void);
00189 void pic32mzEthEventHandler(NetInterface *interface);
00190 
00191 error_t pic32mzEthSendPacket(NetInterface *interface,
00192    const NetBuffer *buffer, size_t offset);
00193 
00194 error_t pic32mzEthReceivePacket(NetInterface *interface);
00195 
00196 error_t pic32mzEthSetMulticastFilter(NetInterface *interface);
00197 error_t pic32mzEthUpdateMacConfig(NetInterface *interface);
00198 
00199 void pic32mzEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00200 uint16_t pic32mzEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00201 
00202 uint32_t pic32mzEthCalcCrc(const void *data, size_t length);
00203 
00204 #endif
00205