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omapl138_eth.h
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00001 /** 00002 * @file omapl138_eth.h 00003 * @brief OMAP-L138 Ethernet MAC controller 00004 * 00005 * @section License 00006 * 00007 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved. 00008 * 00009 * This file is part of CycloneTCP Open. 00010 * 00011 * This program is free software; you can redistribute it and/or 00012 * modify it under the terms of the GNU General Public License 00013 * as published by the Free Software Foundation; either version 2 00014 * of the License, or (at your option) any later version. 00015 * 00016 * This program is distributed in the hope that it will be useful, 00017 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00019 * GNU General Public License for more details. 00020 * 00021 * You should have received a copy of the GNU General Public License 00022 * along with this program; if not, write to the Free Software Foundation, 00023 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00024 * 00025 * @author Oryx Embedded SARL (www.oryx-embedded.com) 00026 * @version 1.7.6 00027 **/ 00028 00029 #ifndef _OMAPL138_ETH_H 00030 #define _OMAPL138_ETH_H 00031 00032 //Dependencies 00033 #include "core/nic.h" 00034 00035 //Number of TX buffers 00036 #ifndef OMAPL138_ETH_TX_BUFFER_COUNT 00037 #define OMAPL138_ETH_TX_BUFFER_COUNT 8 00038 #elif (OMAPL138_ETH_TX_BUFFER_COUNT < 1) 00039 #error OMAPL138_ETH_TX_BUFFER_COUNT parameter is not valid 00040 #endif 00041 00042 //TX buffer size 00043 #ifndef OMAPL138_ETH_TX_BUFFER_SIZE 00044 #define OMAPL138_ETH_TX_BUFFER_SIZE 1536 00045 #elif (OMAPL138_ETH_TX_BUFFER_SIZE != 1536) 00046 #error OMAPL138_ETH_TX_BUFFER_SIZE parameter is not valid 00047 #endif 00048 00049 //Number of RX buffers 00050 #ifndef OMAPL138_ETH_RX_BUFFER_COUNT 00051 #define OMAPL138_ETH_RX_BUFFER_COUNT 8 00052 #elif (OMAPL138_ETH_RX_BUFFER_COUNT < 1) 00053 #error OMAPL138_ETH_RX_BUFFER_COUNT parameter is not valid 00054 #endif 00055 00056 //RX buffer size 00057 #ifndef OMAPL138_ETH_RX_BUFFER_SIZE 00058 #define OMAPL138_ETH_RX_BUFFER_SIZE 1536 00059 #elif (OMAPL138_ETH_RX_BUFFER_SIZE != 1536) 00060 #error OMAPL138_ETH_RX_BUFFER_SIZE parameter is not valid 00061 #endif 00062 00063 //Channel number for the TX interrupt 00064 #ifndef OMAPL138_ETH_TX_IRQ_CHANNEL 00065 #define OMAPL138_ETH_TX_IRQ_CHANNEL 3 00066 #elif (OMAPL138_ETH_TX_IRQ_CHANNEL < 0 || OMAPL138_ETH_TX_IRQ_CHANNEL > 31) 00067 #error OMAPL138_ETH_TX_IRQ_CHANNEL parameter is not valid 00068 #endif 00069 00070 //Channel number for the RX interrupt 00071 #ifndef OMAPL138_ETH_RX_IRQ_CHANNEL 00072 #define OMAPL138_ETH_RX_IRQ_CHANNEL 3 00073 #elif (OMAPL138_ETH_RX_IRQ_CHANNEL < 0 || OMAPL138_ETH_RX_IRQ_CHANNEL > 31) 00074 #error OMAPL138_ETH_RX_IRQ_CHANNEL parameter is not valid 00075 #endif 00076 00077 //EMAC cores 00078 #define EMAC_CORE0 0 00079 #define EMAC_CORE1 1 00080 #define EMAC_CORE2 2 00081 00082 //EMAC channels 00083 #define EMAC_CH0 0 00084 #define EMAC_CH1 1 00085 #define EMAC_CH2 2 00086 #define EMAC_CH3 3 00087 #define EMAC_CH4 4 00088 #define EMAC_CH5 5 00089 #define EMAC_CH6 6 00090 #define EMAC_CH7 7 00091 00092 //SYSCFG0 registers 00093 #define SYSCFG0_PINMUX_R(n) HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n)) 00094 #define SYSCFG0_CFGCHIP3_R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3) 00095 00096 //EMAC registers 00097 #define EMAC_TXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXREVID) 00098 #define EMAC_TXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCONTROL) 00099 #define EMAC_TXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXTEARDOWN) 00100 #define EMAC_RXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXREVID) 00101 #define EMAC_RXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCONTROL) 00102 #define EMAC_RXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXTEARDOWN) 00103 #define EMAC_TXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATRAW) 00104 #define EMAC_TXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATMASKED) 00105 #define EMAC_TXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKSET) 00106 #define EMAC_TXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKCLEAR) 00107 #define EMAC_MACINVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINVECTOR) 00108 #define EMAC_MACEOIVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACEOIVECTOR) 00109 #define EMAC_RXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATRAW) 00110 #define EMAC_RXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATMASKED) 00111 #define EMAC_RXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKSET) 00112 #define EMAC_RXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKCLEAR) 00113 #define EMAC_MACINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATRAW) 00114 #define EMAC_MACINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATMASKED) 00115 #define EMAC_MACINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKSET) 00116 #define EMAC_MACINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKCLEAR) 00117 #define EMAC_RXMBPENABLE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMBPENABLE) 00118 #define EMAC_RXUNICASTSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTSET) 00119 #define EMAC_RXUNICASTCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTCLEAR) 00120 #define EMAC_RXMAXLEN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMAXLEN) 00121 #define EMAC_RXBUFFEROFFSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBUFFEROFFSET) 00122 #define EMAC_RXFILTERLOWTHRESH_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERLOWTHRESH) 00123 #define EMAC_RXFLOWTHRESH_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFLOWTHRESH(n)) 00124 #define EMAC_RXFREEBUFFER_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFREEBUFFER(n)) 00125 #define EMAC_MACCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONTROL) 00126 #define EMAC_MACSTATUS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSTATUS) 00127 #define EMAC_EMCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_EMCONTROL) 00128 #define EMAC_FIFOCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FIFOCONTROL) 00129 #define EMAC_MACCONFIG_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONFIG) 00130 #define EMAC_SOFTRESET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_SOFTRESET) 00131 #define EMAC_MACSRCADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRLO) 00132 #define EMAC_MACSRCADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRHI) 00133 #define EMAC_MACHASH1_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH1) 00134 #define EMAC_MACHASH2_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH2) 00135 #define EMAC_BOFFTEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_BOFFTEST) 00136 #define EMAC_TPACETEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TPACETEST) 00137 #define EMAC_RXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSE) 00138 #define EMAC_TXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSE) 00139 #define EMAC_RXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXGOODFRAMES) 00140 #define EMAC_RXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBCASTFRAMES) 00141 #define EMAC_RXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMCASTFRAMES) 00142 #define EMAC_RXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSEFRAMES) 00143 #define EMAC_RXCRCERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCRCERRORS) 00144 #define EMAC_RXALIGNCODEERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMACEMAC_RXOVERSIZED) 00145 #define EMAC_RXJABBER_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXJABBER) 00146 #define EMAC_RXUNDERSIZED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNDERSIZED) 00147 #define EMAC_RXFRAGMENTS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFRAGMENTS) 00148 #define EMAC_RXFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERED) 00149 #define EMAC_RXQOSFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXQOSFILTERED) 00150 #define EMAC_RXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXOCTETS) 00151 #define EMAC_TXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXGOODFRAMES) 00152 #define EMAC_TXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXBCASTFRAMES) 00153 #define EMAC_TXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMCASTFRAMES) 00154 #define EMAC_TXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSEFRAMES) 00155 #define EMAC_TXDEFERRED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXDEFERRED) 00156 #define EMAC_TXCOLLISION_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCOLLISION) 00157 #define EMAC_TXSINGLECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXSINGLECOLL) 00158 #define EMAC_TXMULTICOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMULTICOLL) 00159 #define EMAC_TXEXCESSIVECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXEXCESSIVECOLL) 00160 #define EMAC_TXLATECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXLATECOLL) 00161 #define EMAC_TXUNDERRUN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXUNDERRUN) 00162 #define EMAC_TXCARRIERSENSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCARRIERSENSE) 00163 #define EMAC_TXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXOCTETS) 00164 #define EMAC_FRAME64_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME64) 00165 #define EMAC_FRAME65T127_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME65T127) 00166 #define EMAC_FRAME128T255_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME128T255) 00167 #define EMAC_FRAME256T511_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME256T511) 00168 #define EMAC_FRAME512T1023_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME512T1023) 00169 #define EMAC_FRAME1024TUP_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME1024TUP) 00170 #define EMAC_NETOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_NETOCTETS) 00171 #define EMAC_RXSOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXSOFOVERRUNS) 00172 #define EMAC_RXMOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMOFOVERRUNS) 00173 #define EMAC_RXDMAOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXDMAOVERRUNS) 00174 #define EMAC_MACADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRLO) 00175 #define EMAC_MACADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRHI) 00176 #define EMAC_MACINDEX_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINDEX) 00177 #define EMAC_TXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXHDP(n)) 00178 #define EMAC_RXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXHDP(n)) 00179 #define EMAC_TXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCP(n)) 00180 #define EMAC_RXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCP(n)) 00181 00182 //EMAC control registers 00183 #define EMAC_CTRL_REVID_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_REVID) 00184 #define EMAC_CTRL_SOFTRESET_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_SOFTRESET) 00185 #define EMAC_CTRL_INTCONTRO_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_INTCONTROL) 00186 #define EMAC_CTRL_C0RXTHRESHEN_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHEN) 00187 #define EMAC_CTRL_CnRXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXEN(n)) 00188 #define EMAC_CTRL_CnTXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnTXEN(n)) 00189 #define EMAC_CTRL_CnMISCEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnMISCEN(n)) 00190 #define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXTHRESHEN(n)) 00191 #define EMAC_CTRL_C0RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHSTAT) 00192 #define EMAC_CTRL_C0RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXSTAT) 00193 #define EMAC_CTRL_C0TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXSTAT) 00194 #define EMAC_CTRL_C0MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0MISCSTAT) 00195 #define EMAC_CTRL_C1RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT) 00196 #define EMAC_CTRL_C1RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT) 00197 #define EMAC_CTRL_C1TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXSTAT) 00198 #define EMAC_CTRL_C1MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1MISCSTAT) 00199 #define EMAC_CTRL_C2RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXTHRESHSTAT) 00200 #define EMAC_CTRL_C2RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXSTAT) 00201 #define EMAC_CTRL_C2TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXSTAT) 00202 #define EMAC_CTRL_C2MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2MISCSTAT) 00203 #define EMAC_CTRL_C0RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXIMAX) 00204 #define EMAC_CTRL_C0TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXIMAX) 00205 #define EMAC_CTRL_C1RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXIMAX) 00206 #define EMAC_CTRL_C1TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXIMAX) 00207 #define EMAC_CTRL_C2RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXIMAX) 00208 #define EMAC_CTRL_C2TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXIMAX) 00209 00210 //MDIO registers 00211 #define MDIO_REVID_R HWREG(SOC_MDIO_0_REGS + MDIO_REVID) 00212 #define MDIO_CONTROL_R HWREG(SOC_MDIO_0_REGS + MDIO_CONTROL) 00213 #define MDIO_ALIVE_R HWREG(SOC_MDIO_0_REGS + MDIO_ALIVE) 00214 #define MDIO_LINK_R HWREG(SOC_MDIO_0_REGS + MDIO_LINK) 00215 #define MDIO_LINKINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTRAW) 00216 #define MDIO_LINKINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTMASKED) 00217 #define MDIO_USERINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTRAW) 00218 #define MDIO_USERINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKED) 00219 #define MDIO_USERINTMASKSET_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKSET) 00220 #define MDIO_USERINTMASKCLEAR_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKCLEAR) 00221 #define MDIO_USERACCESS0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS0) 00222 #define MDIO_USERPHYSEL0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL0) 00223 #define MDIO_USERACCESS1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS1) 00224 #define MDIO_USERPHYSEL1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL1) 00225 00226 //MACEOIVECTOR register 00227 #define EMAC_MACEOIVECTOR_C0RXTHRESH 0x00000000 00228 #define EMAC_MACEOIVECTOR_C0RX 0x00000001 00229 #define EMAC_MACEOIVECTOR_C0TX 0x00000002 00230 #define EMAC_MACEOIVECTOR_C0MISC 0x00000003 00231 #define EMAC_MACEOIVECTOR_C1RXTHRESH 0x00000004 00232 #define EMAC_MACEOIVECTOR_C1RX 0x00000005 00233 #define EMAC_MACEOIVECTOR_C1TX 0x00000006 00234 #define EMAC_MACEOIVECTOR_C1MISC 0x00000007 00235 #define EMAC_MACEOIVECTOR_C2RXTHRESH 0x00000008 00236 #define EMAC_MACEOIVECTOR_C2RX 0x00000009 00237 #define EMAC_MACEOIVECTOR_C2TX 0x0000000A 00238 #define EMAC_MACEOIVECTOR_C2MISC 0x0000000B 00239 00240 //TX buffer descriptor flags 00241 #define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF 00242 #define EMAC_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF 00243 #define EMAC_TX_WORD2_BUFFER_OFFSET 0xFFFF0000 00244 #define EMAC_TX_WORD2_BUFFER_LENGTH 0x0000FFFF 00245 #define EMAC_TX_WORD3_SOP 0x80000000 00246 #define EMAC_TX_WORD3_EOP 0x40000000 00247 #define EMAC_TX_WORD3_OWNER 0x20000000 00248 #define EMAC_TX_WORD3_EOQ 0x10000000 00249 #define EMAC_TX_WORD3_TDOWNCMPLT 0x08000000 00250 #define EMAC_TX_WORD3_PASSCRC 0x04000000 00251 #define EMAC_TX_WORD3_PACKET_LENGTH 0x0000FFFF 00252 00253 //RX buffer descriptor flags 00254 #define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF 00255 #define EMAC_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF 00256 #define EMAC_RX_WORD2_BUFFER_OFFSET 0x07FF0000 00257 #define EMAC_RX_WORD2_BUFFER_LENGTH 0x000007FF 00258 #define EMAC_RX_WORD3_SOP 0x80000000 00259 #define EMAC_RX_WORD3_EOP 0x40000000 00260 #define EMAC_RX_WORD3_OWNER 0x20000000 00261 #define EMAC_RX_WORD3_EOQ 0x10000000 00262 #define EMAC_RX_WORD3_TDOWNCMPLT 0x08000000 00263 #define EMAC_RX_WORD3_PASSCRC 0x04000000 00264 #define EMAC_RX_WORD3_ERROR_MASK 0x03FF0000 00265 #define EMAC_RX_WORD3_JABBER 0x02000000 00266 #define EMAC_RX_WORD3_OVERSIZE 0x01000000 00267 #define EMAC_RX_WORD3_FRAGMENT 0x00800000 00268 #define EMAC_RX_WORD3_UNDERSIZED 0x00400000 00269 #define EMAC_RX_WORD3_CONTROL 0x00200000 00270 #define EMAC_RX_WORD3_OVERRUN 0x00100000 00271 #define EMAC_RX_WORD3_CODEERROR 0x00080000 00272 #define EMAC_RX_WORD3_ALIGNERROR 0x00040000 00273 #define EMAC_RX_WORD3_CRCERROR 0x00020000 00274 #define EMAC_RX_WORD3_NOMATCH 0x00010000 00275 #define EMAC_RX_WORD3_PACKET_LENGTH 0x0000FFFF 00276 00277 00278 /** 00279 * @brief TX buffer descriptor 00280 **/ 00281 00282 typedef struct _Omapl138TxBufferDesc 00283 { 00284 uint32_t word0; 00285 uint32_t word1; 00286 uint32_t word2; 00287 uint32_t word3; 00288 struct _Omapl138TxBufferDesc *next; 00289 struct _Omapl138TxBufferDesc *prev; 00290 } Omapl138TxBufferDesc; 00291 00292 00293 /** 00294 * @brief RX buffer descriptor 00295 **/ 00296 00297 typedef struct _Omapl138RxBufferDesc 00298 { 00299 uint32_t word0; 00300 uint32_t word1; 00301 uint32_t word2; 00302 uint32_t word3; 00303 struct _Omapl138RxBufferDesc *next; 00304 struct _Omapl138RxBufferDesc *prev; 00305 } Omapl138RxBufferDesc; 00306 00307 00308 //AM335x Ethernet MAC driver 00309 extern const NicDriver omapl138EthDriver; 00310 00311 //AM335x Ethernet MAC related functions 00312 error_t omapl138EthInit(NetInterface *interface); 00313 void omapl138EthInitGpio(NetInterface *interface); 00314 void omapl138EthInitBufferDesc(NetInterface *interface); 00315 00316 void omapl138EthTick(NetInterface *interface); 00317 00318 void omapl138EthEnableIrq(NetInterface *interface); 00319 void omapl138EthDisableIrq(NetInterface *interface); 00320 void omapl138EthTxIrqHandler(void); 00321 void omapl138EthRxIrqHandler(void); 00322 void omapl138EthEventHandler(NetInterface *interface); 00323 00324 error_t omapl138EthSendPacket(NetInterface *interface, 00325 const NetBuffer *buffer, size_t offset); 00326 00327 error_t omapl138EthReceivePacket(NetInterface *interface); 00328 00329 error_t omapl138EthSetMulticastFilter(NetInterface *interface); 00330 error_t omapl138EthUpdateMacConfig(NetInterface *interface); 00331 00332 void omapl138EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data); 00333 uint16_t omapl138EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr); 00334 00335 #endif 00336
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