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m2sxxx_eth.h
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00001 /** 00002 * @file m2sxxx_eth.h 00003 * @brief SmartFusion2 (M2Sxxx) Ethernet MAC controller 00004 * 00005 * @section License 00006 * 00007 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved. 00008 * 00009 * This file is part of CycloneTCP Open. 00010 * 00011 * This program is free software; you can redistribute it and/or 00012 * modify it under the terms of the GNU General Public License 00013 * as published by the Free Software Foundation; either version 2 00014 * of the License, or (at your option) any later version. 00015 * 00016 * This program is distributed in the hope that it will be useful, 00017 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00019 * GNU General Public License for more details. 00020 * 00021 * You should have received a copy of the GNU General Public License 00022 * along with this program; if not, write to the Free Software Foundation, 00023 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00024 * 00025 * @author Oryx Embedded SARL (www.oryx-embedded.com) 00026 * @version 1.7.6 00027 **/ 00028 00029 #ifndef _M2SXXX_ETH_H 00030 #define _M2SXXX_ETH_H 00031 00032 //Dependencies 00033 #include "core/nic.h" 00034 00035 //Number of TX buffers 00036 #ifndef M2SXXX_ETH_TX_BUFFER_COUNT 00037 #define M2SXXX_ETH_TX_BUFFER_COUNT 2 00038 #elif (M2SXXX_ETH_TX_BUFFER_COUNT < 1) 00039 #error M2SXXX_ETH_TX_BUFFER_COUNT parameter is not valid 00040 #endif 00041 00042 //TX buffer size 00043 #ifndef M2SXXX_ETH_TX_BUFFER_SIZE 00044 #define M2SXXX_ETH_TX_BUFFER_SIZE 1536 00045 #elif (M2SXXX_ETH_TX_BUFFER_SIZE != 1536) 00046 #error M2SXXX_ETH_TX_BUFFER_SIZE parameter is not valid 00047 #endif 00048 00049 //Number of RX buffers 00050 #ifndef M2SXXX_ETH_RX_BUFFER_COUNT 00051 #define M2SXXX_ETH_RX_BUFFER_COUNT 4 00052 #elif (M2SXXX_ETH_RX_BUFFER_COUNT < 1) 00053 #error M2SXXX_ETH_RX_BUFFER_COUNT parameter is not valid 00054 #endif 00055 00056 //RX buffer size 00057 #ifndef M2SXXX_ETH_RX_BUFFER_SIZE 00058 #define M2SXXX_ETH_RX_BUFFER_SIZE 1536 00059 #elif (M2SXXX_ETH_RX_BUFFER_SIZE != 1536) 00060 #error M2SXXX_ETH_RX_BUFFER_SIZE parameter is not valid 00061 #endif 00062 00063 //Interrupt priority grouping 00064 #ifndef M2SXXX_ETH_IRQ_PRIORITY_GROUPING 00065 #define M2SXXX_ETH_IRQ_PRIORITY_GROUPING 3 00066 #elif (M2SXXX_ETH_IRQ_PRIORITY_GROUPING < 0) 00067 #error M2SXXX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid 00068 #endif 00069 00070 //Ethernet interrupt group priority 00071 #ifndef M2SXXX_ETH_IRQ_GROUP_PRIORITY 00072 #define M2SXXX_ETH_IRQ_GROUP_PRIORITY 12 00073 #elif (M2SXXX_ETH_IRQ_GROUP_PRIORITY < 0) 00074 #error M2SXXX_ETH_IRQ_GROUP_PRIORITY parameter is not valid 00075 #endif 00076 00077 //Ethernet interrupt subpriority 00078 #ifndef M2SXXX_ETH_IRQ_SUB_PRIORITY 00079 #define M2SXXX_ETH_IRQ_SUB_PRIORITY 0 00080 #elif (M2SXXX_ETH_IRQ_SUB_PRIORITY < 0) 00081 #error M2SXXX_ETH_IRQ_SUB_PRIORITY parameter is not valid 00082 #endif 00083 00084 //EDAC_CR register 00085 #define EDAC_CR_CAN_EDAC_EN 0x00000040 00086 #define EDAC_CR_USB_EDAC_EN 0x00000020 00087 #define EDAC_CR_MAC_EDAC_RX_EN 0x00000010 00088 #define EDAC_CR_MAC_EDAC_TX_EN 0x00000008 00089 #define EDAC_CR_ESRAM1_EDAC_EN 0x00000002 00090 #define EDAC_CR_ESRAM0_EDAC_EN 0x00000001 00091 00092 //MAC_CR register 00093 #define MAC_CR_RGMII_TXC_DELAY_SEL 0x000001E0 00094 #define MAC_CR_ETH_PHY_MODE 0x0000001C 00095 #define MAC_CR_ETH_LINE_SPEED 0x00000003 00096 00097 #define MAC_CR_ETH_PHY_MODE_RMII 0x00000000 00098 #define MAC_CR_ETH_PHY_MODE_TBI 0x00000008 00099 #define MAC_CR_ETH_PHY_MODE_MII 0x0000000C 00100 #define MAC_CR_ETH_PHY_MODE_GMII 0x00000010 00101 00102 #define MAC_CR_ETH_LINE_SPEED_10MBPS 0x00000000 00103 #define MAC_CR_ETH_LINE_SPEED_100MBPS 0x00000001 00104 #define MAC_CR_ETH_LINE_SPEED_1000MBPS 0x00000002 00105 00106 //DMA_TX_CTRL register 00107 #define DMA_TX_CTRL_TX_EN 0x00000001 00108 00109 //DMA_TX_STATUS register 00110 #define DMA_TX_STATUS_TX_PKT_COUNT 0x00FF0000 00111 #define DMA_TX_STATUS_TX_BUS_ERROR 0x00000008 00112 #define DMA_TX_STATUS_TX_UNDERRUN 0x00000002 00113 #define DMA_TX_STATUS_TX_PKT_SENT 0x00000001 00114 00115 //DMA_RX_CTRL register 00116 #define DMA_RX_CTRL_RX_EN 0x00000001 00117 00118 //DMA_RX_STATUS register 00119 #define DMA_RX_STATUS_RX_PKT_COUNT 0x00FF0000 00120 #define DMA_RX_STATUS_RX_BUS_ERROR 0x00000008 00121 #define DMA_RX_STATUS_RX_OVERFLOW 0x00000004 00122 #define DMA_RX_STATUS_RX_PKT_RECEIVED 0x00000001 00123 00124 //DMA_IRQ_MASK register 00125 #define DMA_IRQ_MASK_RX_BUS_ERROR 0x00000080 00126 #define DMA_IRQ_MASK_RX_OVERFLOW 0x00000040 00127 #define DMA_IRQ_MASK_RX_PKT_RECEIVED 0x00000010 00128 #define DMA_IRQ_MASK_TX_BUS_ERROR 0x00000008 00129 #define DMA_IRQ_MASK_TX_UNDERRUN 0x00000002 00130 #define DMA_IRQ_MASK_TX_PKT_SENT 0x00000001 00131 00132 //DMA_IRQ register 00133 #define DMA_IRQ_RX_BUS_ERROR 0x00000080 00134 #define DMA_IRQ_RX_OVERFLOW 0x00000040 00135 #define DMA_IRQ_RX_PKT_RECEIVED 0x00000010 00136 #define DMA_IRQ_TX_BUS_ERROR 0x00000008 00137 #define DMA_IRQ_TX_UNDERRUN 0x00000002 00138 #define DMA_IRQ_TX_PKT_SENT 0x00000001 00139 00140 //CFG1 register 00141 #define CFG1_SOFT_RESET 0x80000000 00142 #define CFG1_SIMULATION_RESET 0x40000000 00143 #define CFG1_RESET_RX_MAC_CTRL 0x00080000 00144 #define CFG1_RESET_TX_MAC_CTRL 0x00040000 00145 #define CFG1_RESET_RX_FUNCTION 0x00020000 00146 #define CFG1_RESET_TX_FUNCTION 0x00010000 00147 #define CFG1_LOOP_BACK 0x00000100 00148 #define CFG1_RX_FLOW_CTRL_EN 0x00000020 00149 #define CFG1_TX_FLOW_CTRL_EN 0x00000010 00150 #define CFG1_SYNC_RX_EN 0x00000008 00151 #define CFG1_RX_EN 0x00000004 00152 #define CFG1_SYNC_TX_EN 0x00000002 00153 #define CFG1_TX_EN 0x00000001 00154 00155 //CFG2 register 00156 #define CFG2_PREAMBLE_LENGTH 0x0000F000 00157 #define CFG2_INTERFACE_MODE 0x00000300 00158 #define CFG2_HUGE FRAME_EN 0x00000020 00159 #define CFG2_LENGTH_FIELD_CHECK 0x00000010 00160 #define CFG2_PAD_CRC_EN 0x00000004 00161 #define CFG2_CRC_EN 0x00000002 00162 #define CFG2_FULL_DUPLEX 0x00000001 00163 00164 #define CFG2_PREAMBLE_7 0x00007000 00165 00166 #define CFG2_INTERFACE_MODE_NIBBLE 0x00000100 00167 #define CFG2_INTERFACE_MODE_BYTE 0x00000200 00168 00169 //MII_CONFIG register 00170 #define MII_CONFIG_CLKSEL_DIV4 0x00000000 00171 #define MII_CONFIG_CLKSEL_DIV6 0x00000002 00172 #define MII_CONFIG_CLKSEL_DIV8 0x00000003 00173 #define MII_CONFIG_CLKSEL_DIV10 0x00000004 00174 #define MII_CONFIG_CLKSEL_DIV14 0x00000005 00175 #define MII_CONFIG_CLKSEL_DIV20 0x00000006 00176 #define MII_CONFIG_CLKSEL_DIV28 0x00000007 00177 00178 //MII_COMMAND register 00179 #define MII_COMMAND_SCAN 0x00000002 00180 #define MII_COMMAND_READ 0x00000001 00181 00182 //MII_ADDRESS register 00183 #define MII_ADDRESS_PHY_ADDR 0x00001F00 00184 #define MII_ADDRESS_REG_ADDR 0x0000001F 00185 00186 #define MII_ADDRESS_PHY_ADDR_POS 8 00187 #define MII_ADDRESS_REG_ADDR_POS 0 00188 00189 //MII_INDICATORS register 00190 #define MII_INDICATORS_NOT_VALID 0x00000004 00191 #define MII_INDICATORS_SCANNING 0x00000002 00192 #define MII_INDICATORS_BUSY 0x00000001 00193 00194 //INTERFACE_CTRL register 00195 #define INTERFACE_CTRL_RESET 0x80000000 00196 #define INTERFACE_CTRL_TBI_MODE 0x08000000 00197 #define INTERFACE_CTRL_GHD_MODE 0x04000000 00198 #define INTERFACE_CTRL_LHD_MODE 0x02000000 00199 #define INTERFACE_CTRL_PHY_MODE 0x01000000 00200 #define INTERFACE_CTRL_RESET_PERMII 0x00800000 00201 #define INTERFACE_CTRL_SPEED 0x00010000 00202 #define INTERFACE_CTRL_RESET_PE100X 0x00008000 00203 #define INTERFACE_CTRL_FORCE_QUIET 0x00000400 00204 #define INTERFACE_CTRL_NO_CIPHER 0x00000200 00205 #define INTERFACE_CTRL_DISABLE_LINK_FAIL 0x00000100 00206 #define INTERFACE_CTRL_EN_JABBER_PROTECT 0x00000001 00207 00208 //FIFO_CFG0 register 00209 #define FIFO_CFG0_STFENRPLY 0x00080000 00210 #define FIFO_CFG0_FRFENRPLY 0x00040000 00211 #define FIFO_CFG0_SRFENRPLY 0x00020000 00212 #define FIFO_CFG0_WTMENRPLY 0x00010000 00213 #define FIFO_CFG0_FTFENREQ 0x00001000 00214 #define FIFO_CFG0_STFENREQ 0x00000800 00215 #define FIFO_CFG0_FRFENREQ 0x00000400 00216 #define FIFO_CFG0_SRFENREQ 0x00000200 00217 #define FIFO_CFG0_WTMENREQ 0x00000100 00218 #define FIFO_CFG0_HSTRSTFT 0x00000010 00219 #define FIFO_CFG0_HSTRSTST 0x00000008 00220 #define FIFO_CFG0_HSTRSTFR 0x00000004 00221 #define FIFO_CFG0_HSTRSTSR 0x00000002 00222 #define FIFO_CFG0_HSTRSTWT 0x00000001 00223 00224 //FIFO_CFG1 register 00225 #define FIFO_CFG1_CFGSRTH 0x0FFF0000 00226 #define FIFO_CFG1_CFGXOFFRTX 0x0000FFFF 00227 00228 #define FIFO_CFG1_DEFAULT_VALUE 0x0FFF0000 00229 00230 //FIFO_CFG2 register 00231 #define FIFO_CFG2_CFGHWM 0x1FFF0000 00232 #define FIFO_CFG2_CFGLWM 0x00001FFF 00233 00234 #define FIFO_CFG2_DEFAULT_VALUE 0x04000180 00235 00236 //FIFO_CFG3 register 00237 #define FIFO_CFG3_CFGHWMFT 0x0FFF0000 00238 #define FIFO_CFG3_CFGFTTH 0x00000FFF 00239 00240 #define FIFO_CFG3_DEFAULT_VALUE 0x0258FFFF 00241 00242 //FIFO_CFG4 register 00243 #define FIFO_CFG4_HSTFLTRFRM 0x0003FFFF 00244 #define FIFO_CFG4_RECEIVE_LONG_EVENT 0x00020000 00245 #define FIFO_CFG4_VLAN 0x00010000 00246 #define FIFO_CFG4_CONTROL_NOT_PAUSE 0x00008000 00247 #define FIFO_CFG4_CONTROL_PAUSE 0x00004000 00248 #define FIFO_CFG4_CONTROL 0x00002000 00249 #define FIFO_CFG4_TRUNCATED 0x00001000 00250 #define FIFO_CFG4_LONG_EVENT 0x00000800 00251 #define FIFO_CFG4_DRIBBLE_NIBBLE 0x00000400 00252 #define FIFO_CFG4_BROADCAST 0x00000200 00253 #define FIFO_CFG4_MULTICAST 0x00000100 00254 #define FIFO_CFG4_RECEPTION_OK 0x00000080 00255 #define FIFO_CFG4_TYPE_ERROR 0x00000040 00256 #define FIFO_CFG4_LENGTH_ERROR 0x00000020 00257 #define FIFO_CFG4_INVALID_CRC 0x00000010 00258 #define FIFO_CFG4_RECEIVE_ERROR 0x00000008 00259 #define FIFO_CFG4_FALSE_CARRIER 0x00000004 00260 #define FIFO_CFG4_RX_DV_EVENT 0x00000002 00261 #define FIFO_CFG4_PRIOR_PKT_DROPPED 0x00000001 00262 00263 //FIFO_CFG5 register 00264 #define FIFO_CFG5_CFGHDPLX 0x00400000 00265 #define FIFO_CFG5_SRFULL 0x00200000 00266 #define FIFO_CFG5_HSTSRFULLCLR 0x00100000 00267 #define FIFO_CFG5_CFGBYTMODE 0x00080000 00268 #define FIFO_CFG5_HSTDRPLT64 0x00040000 00269 #define FIFO_CFG5_HSTFLTRFRMDC 0x0003FFFF 00270 #define FIFO_CFG5_RECEIVE_LONG_EVENT 0x00020000 00271 #define FIFO_CFG5_VLAN 0x00010000 00272 #define FIFO_CFG5_CONTROL_NOT_PAUSE 0x00008000 00273 #define FIFO_CFG5_CONTROL_PAUSE 0x00004000 00274 #define FIFO_CFG5_CONTROL 0x00002000 00275 #define FIFO_CFG5_TRUNCATED 0x00001000 00276 #define FIFO_CFG5_LONG_EVENT 0x00000800 00277 #define FIFO_CFG5_DRIBBLE_NIBBLE 0x00000400 00278 #define FIFO_CFG5_BROADCAST 0x00000200 00279 #define FIFO_CFG5_MULTICAST 0x00000100 00280 #define FIFO_CFG5_RECEPTION_OK 0x00000080 00281 #define FIFO_CFG5_TYPE_ERROR 0x00000040 00282 #define FIFO_CFG5_LENGTH_ERROR 0x00000020 00283 #define FIFO_CFG5_INVALID_CRC 0x00000010 00284 #define FIFO_CFG5_RECEIVE_ERROR 0x00000008 00285 #define FIFO_CFG5_FALSE_CARRIER 0x00000004 00286 #define FIFO_CFG5_RX_DV_EVENT 0x00000002 00287 #define FIFO_CFG5_PRIOR_PKT_DROPPED 0x00000001 00288 00289 //DMA descriptor flags 00290 #define DMA_DESC_EMPTY_FLAG 0x80000000 00291 #define DMA_DESC_SIZE_MASK 0x00000FFF 00292 00293 00294 /** 00295 * @brief Transmit DMA descriptor 00296 **/ 00297 00298 typedef struct 00299 { 00300 uint32_t addr; 00301 uint32_t size; 00302 uint32_t next; 00303 } M2sxxxTxDmaDesc; 00304 00305 00306 /** 00307 * @brief Receive DMA descriptor 00308 **/ 00309 00310 typedef struct 00311 { 00312 uint32_t addr; 00313 uint32_t size; 00314 uint32_t next; 00315 } M2sxxxRxDmaDesc; 00316 00317 00318 //M2Sxxx Ethernet MAC driver 00319 extern const NicDriver m2sxxxEthDriver; 00320 00321 //M2Sxxx Ethernet MAC related functions 00322 error_t m2sxxxEthInit(NetInterface *interface); 00323 void m2sxxxEthInitGpio(NetInterface *interface); 00324 void m2sxxxEthInitDmaDesc(NetInterface *interface); 00325 00326 void m2sxxxEthTick(NetInterface *interface); 00327 00328 void m2sxxxEthEnableIrq(NetInterface *interface); 00329 void m2sxxxEthDisableIrq(NetInterface *interface); 00330 void m2sxxxEthEventHandler(NetInterface *interface); 00331 00332 error_t m2sxxxEthSendPacket(NetInterface *interface, 00333 const NetBuffer *buffer, size_t offset); 00334 00335 error_t m2sxxxEthReceivePacket(NetInterface *interface); 00336 00337 error_t m2sxxxEthSetMulticastFilter(NetInterface *interface); 00338 error_t m2sxxxEthUpdateMacConfig(NetInterface *interface); 00339 00340 void m2sxxxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data); 00341 uint16_t m2sxxxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr); 00342 00343 #endif 00344
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