lpc43xx_eth.h

00001 /**
00002  * @file lpc43xx_eth.h
00003  * @brief LPC4300 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _LPC43XX_ETH_H
00030 #define _LPC43XX_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef LPC43XX_ETH_TX_BUFFER_COUNT
00037    #define LPC43XX_ETH_TX_BUFFER_COUNT 3
00038 #elif (LPC43XX_ETH_TX_BUFFER_COUNT < 1)
00039    #error LPC43XX_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef LPC43XX_ETH_TX_BUFFER_SIZE
00044    #define LPC43XX_ETH_TX_BUFFER_SIZE 1536
00045 #elif (LPC43XX_ETH_TX_BUFFER_SIZE != 1536)
00046    #error LPC43XX_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef LPC43XX_ETH_RX_BUFFER_COUNT
00051    #define LPC43XX_ETH_RX_BUFFER_COUNT 6
00052 #elif (LPC43XX_ETH_RX_BUFFER_COUNT < 1)
00053    #error LPC43XX_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef LPC43XX_ETH_RX_BUFFER_SIZE
00058    #define LPC43XX_ETH_RX_BUFFER_SIZE 1536
00059 #elif (LPC43XX_ETH_RX_BUFFER_SIZE != 1536)
00060    #error LPC43XX_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Interrupt priority grouping
00064 #ifndef LPC43XX_ETH_IRQ_PRIORITY_GROUPING
00065    #define LPC43XX_ETH_IRQ_PRIORITY_GROUPING 4
00066 #elif (LPC43XX_ETH_IRQ_PRIORITY_GROUPING < 0)
00067    #error LPC43XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
00068 #endif
00069 
00070 //Ethernet interrupt group priority
00071 #ifndef LPC43XX_ETH_IRQ_GROUP_PRIORITY
00072    #define LPC43XX_ETH_IRQ_GROUP_PRIORITY 6
00073 #elif (LPC43XX_ETH_IRQ_GROUP_PRIORITY < 0)
00074    #error LPC43XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
00075 #endif
00076 
00077 //Ethernet interrupt subpriority
00078 #ifndef LPC43XX_ETH_IRQ_SUB_PRIORITY
00079    #define LPC43XX_ETH_IRQ_SUB_PRIORITY 0
00080 #elif (LPC43XX_ETH_IRQ_SUB_PRIORITY < 0)
00081    #error LPC43XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
00082 #endif
00083 
00084 //CREG6 register
00085 #define CREG6_ETHMODE_MII               (0 << CREG_CREG6_ETHMODE_Pos)
00086 #define CREG6_ETHMODE_RMII              (4 << CREG_CREG6_ETHMODE_Pos)
00087 
00088 //MAC_MII_ADDR register
00089 #define ETHERNET_MAC_MII_ADDR_CR_DIV42  (0 << ETHERNET_MAC_MII_ADDR_CR_Pos)
00090 #define ETHERNET_MAC_MII_ADDR_CR_DIV62  (1 << ETHERNET_MAC_MII_ADDR_CR_Pos)
00091 #define ETHERNET_MAC_MII_ADDR_CR_DIV16  (2 << ETHERNET_MAC_MII_ADDR_CR_Pos)
00092 #define ETHERNET_MAC_MII_ADDR_CR_DIV26  (3 << ETHERNET_MAC_MII_ADDR_CR_Pos)
00093 #define ETHERNET_MAC_MII_ADDR_CR_DIV102 (4 << ETHERNET_MAC_MII_ADDR_CR_Pos)
00094 #define ETHERNET_MAC_MII_ADDR_CR_DIV124 (5 << ETHERNET_MAC_MII_ADDR_CR_Pos)
00095 
00096 //DMA_BUS_MODE register
00097 #define ETHERNET_DMA_BUS_MODE_RPBL_1    (1 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
00098 #define ETHERNET_DMA_BUS_MODE_RPBL_2    (2 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
00099 #define ETHERNET_DMA_BUS_MODE_RPBL_4    (4 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
00100 #define ETHERNET_DMA_BUS_MODE_RPBL_8    (8 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
00101 #define ETHERNET_DMA_BUS_MODE_RPBL_16   (16 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
00102 #define ETHERNET_DMA_BUS_MODE_RPBL_32   (32 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
00103 
00104 #define ETHERNET_DMA_BUS_MODE_PR_1_1    (0 << ETHERNET_DMA_BUS_MODE_PR_Pos)
00105 #define ETHERNET_DMA_BUS_MODE_PR_2_1    (1 << ETHERNET_DMA_BUS_MODE_PR_Pos)
00106 #define ETHERNET_DMA_BUS_MODE_PR_3_1    (2 << ETHERNET_DMA_BUS_MODE_PR_Pos)
00107 #define ETHERNET_DMA_BUS_MODE_PR_4_1    (3 << ETHERNET_DMA_BUS_MODE_PR_Pos)
00108 
00109 #define ETHERNET_DMA_BUS_MODE_PBL_1     (1 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
00110 #define ETHERNET_DMA_BUS_MODE_PBL_2     (2 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
00111 #define ETHERNET_DMA_BUS_MODE_PBL_4     (4 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
00112 #define ETHERNET_DMA_BUS_MODE_PBL_8     (8 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
00113 #define ETHERNET_DMA_BUS_MODE_PBL_16    (16 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
00114 #define ETHERNET_DMA_BUS_MODE_PBL_32    (32 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
00115 
00116 //DMA_OP_MODE register
00117 #define ETHERNET_DMA_OP_MODE_TTC_64     (0 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00118 #define ETHERNET_DMA_OP_MODE_TTC_128    (1 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00119 #define ETHERNET_DMA_OP_MODE_TTC_192    (2 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00120 #define ETHERNET_DMA_OP_MODE_TTC_256    (3 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00121 #define ETHERNET_DMA_OP_MODE_TTC_40     (4 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00122 #define ETHERNET_DMA_OP_MODE_TTC_32     (5 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00123 #define ETHERNET_DMA_OP_MODE_TTC_24     (6 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00124 #define ETHERNET_DMA_OP_MODE_TTC_16     (7 << ETHERNET_DMA_OP_MODE_TTC_Pos)
00125 
00126 #define ETHERNET_DMA_OP_MODE_RTC_64     (0 << ETHERNET_DMA_OP_MODE_RTC_Pos)
00127 #define ETHERNET_DMA_OP_MODE_RTC_32     (1 << ETHERNET_DMA_OP_MODE_RTC_Pos)
00128 #define ETHERNET_DMA_OP_MODE_RTC_96     (2 << ETHERNET_DMA_OP_MODE_RTC_Pos)
00129 #define ETHERNET_DMA_OP_MODE_RTC_128    (3 << ETHERNET_DMA_OP_MODE_RTC_Pos)
00130 
00131 //Transmit DMA descriptor flags
00132 #define ETH_TDES0_OWN        0x80000000
00133 #define ETH_TDES0_IC         0x40000000
00134 #define ETH_TDES0_LS         0x20000000
00135 #define ETH_TDES0_FS         0x10000000
00136 #define ETH_TDES0_DC         0x08000000
00137 #define ETH_TDES0_DP         0x04000000
00138 #define ETH_TDES0_TTSE       0x02000000
00139 #define ETH_TDES0_TER        0x00200000
00140 #define ETH_TDES0_TCH        0x00100000
00141 #define ETH_TDES0_TTSS       0x00020000
00142 #define ETH_TDES0_IHE        0x00010000
00143 #define ETH_TDES0_ES         0x00008000
00144 #define ETH_TDES0_JT         0x00004000
00145 #define ETH_TDES0_FF         0x00002000
00146 #define ETH_TDES0_IPE        0x00001000
00147 #define ETH_TDES0_LCA        0x00000800
00148 #define ETH_TDES0_NC         0x00000400
00149 #define ETH_TDES0_LCO        0x00000200
00150 #define ETH_TDES0_EC         0x00000100
00151 #define ETH_TDES0_VF         0x00000080
00152 #define ETH_TDES0_CC         0x00000078
00153 #define ETH_TDES0_ED         0x00000004
00154 #define ETH_TDES0_UF         0x00000002
00155 #define ETH_TDES0_DB         0x00000001
00156 #define ETH_TDES1_TBS2       0x1FFF0000
00157 #define ETH_TDES1_TBS1       0x00001FFF
00158 #define ETH_TDES2_B1ADD      0xFFFFFFFF
00159 #define ETH_TDES3_B2ADD      0xFFFFFFFF
00160 #define ETH_TDES6_TTSL       0xFFFFFFFF
00161 #define ETH_TDES7_TTSH       0xFFFFFFFF
00162 
00163 //Receive DMA descriptor flags
00164 #define ETH_RDES0_OWN        0x80000000
00165 #define ETH_RDES0_AFM        0x40000000
00166 #define ETH_RDES0_FL         0x3FFF0000
00167 #define ETH_RDES0_ES         0x00008000
00168 #define ETH_RDES0_DE         0x00004000
00169 #define ETH_RDES0_SAF        0x00002000
00170 #define ETH_RDES0_LE         0x00001000
00171 #define ETH_RDES0_OE         0x00000800
00172 #define ETH_RDES0_VLAN       0x00000400
00173 #define ETH_RDES0_FS         0x00000200
00174 #define ETH_RDES0_LS         0x00000100
00175 #define ETH_RDES0_TSA        0x00000080
00176 #define ETH_RDES0_LCO        0x00000040
00177 #define ETH_RDES0_FT         0x00000020
00178 #define ETH_RDES0_RWT        0x00000010
00179 #define ETH_RDES0_RE         0x00000008
00180 #define ETH_RDES0_DBE        0x00000004
00181 #define ETH_RDES0_CE         0x00000002
00182 #define ETH_RDES0_ESA        0x00000001
00183 #define ETH_RDES1_RBS2       0x1FFF0000
00184 #define ETH_RDES1_RER        0x00008000
00185 #define ETH_RDES1_RCH        0x00004000
00186 #define ETH_RDES1_RBS1       0x00001FFF
00187 #define ETH_RDES2_B1ADD      0xFFFFFFFF
00188 #define ETH_RDES3_B2ADD      0xFFFFFFFF
00189 #define ETH_RDES4_PTPVERSION 0x00002000
00190 #define ETH_RDES4_PTPTYPE    0x00001000
00191 #define ETH_RDES4_MT         0x00000F00
00192 #define ETH_RDES4_IPV6       0x00000080
00193 #define ETH_RDES4_IPV4       0x00000040
00194 #define ETH_RDES6_RTSL       0xFFFFFFFF
00195 #define ETH_RDES7_RTSH       0xFFFFFFFF
00196 
00197 
00198 /**
00199  * @brief Enhanced TX DMA descriptor
00200  **/
00201 
00202 typedef struct
00203 {
00204    uint32_t tdes0;
00205    uint32_t tdes1;
00206    uint32_t tdes2;
00207    uint32_t tdes3;
00208    uint32_t tdes4;
00209    uint32_t tdes5;
00210    uint32_t tdes6;
00211    uint32_t tdes7;
00212 } Lpc43xxTxDmaDesc;
00213 
00214 
00215 /**
00216  * @brief Enhanced RX DMA descriptor
00217  **/
00218 
00219 typedef struct
00220 {
00221    uint32_t rdes0;
00222    uint32_t rdes1;
00223    uint32_t rdes2;
00224    uint32_t rdes3;
00225    uint32_t rdes4;
00226    uint32_t rdes5;
00227    uint32_t rdes6;
00228    uint32_t rdes7;
00229 } Lpc43xxRxDmaDesc;
00230 
00231 
00232 //LPC43xx Ethernet MAC driver
00233 extern const NicDriver lpc43xxEthDriver;
00234 
00235 //LPC43xx Ethernet MAC related functions
00236 error_t lpc43xxEthInit(NetInterface *interface);
00237 void lpc43xxEthInitGpio(NetInterface *interface);
00238 void lpc43xxEthInitDmaDesc(NetInterface *interface);
00239 
00240 void lpc43xxEthTick(NetInterface *interface);
00241 
00242 void lpc43xxEthEnableIrq(NetInterface *interface);
00243 void lpc43xxEthDisableIrq(NetInterface *interface);
00244 void lpc43xxEthEventHandler(NetInterface *interface);
00245 
00246 error_t lpc43xxEthSendPacket(NetInterface *interface,
00247    const NetBuffer *buffer, size_t offset);
00248 
00249 error_t lpc43xxEthReceivePacket(NetInterface *interface);
00250 
00251 error_t lpc43xxEthSetMulticastFilter(NetInterface *interface);
00252 error_t lpc43xxEthUpdateMacConfig(NetInterface *interface);
00253 
00254 void lpc43xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00255 uint16_t lpc43xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00256 
00257 uint32_t lpc43xxEthCalcCrc(const void *data, size_t length);
00258 
00259 #endif
00260