lpc23xx_eth.h

00001 /**
00002  * @file lpc23xx_eth.h
00003  * @brief LPC2300 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _LPC23XX_ETH_H
00030 #define _LPC23XX_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef LPC23XX_ETH_TX_BUFFER_COUNT
00037    #define LPC23XX_ETH_TX_BUFFER_COUNT 2
00038 #elif (LPC23XX_ETH_TX_BUFFER_COUNT < 1)
00039    #error LPC23XX_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef LPC23XX_ETH_TX_BUFFER_SIZE
00044    #define LPC23XX_ETH_TX_BUFFER_SIZE 1536
00045 #elif (LPC23XX_ETH_TX_BUFFER_SIZE != 1536)
00046    #error LPC23XX_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef LPC23XX_ETH_RX_BUFFER_COUNT
00051    #define LPC23XX_ETH_RX_BUFFER_COUNT 4
00052 #elif (LPC23XX_ETH_RX_BUFFER_COUNT < 1)
00053    #error LPC23XX_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef LPC23XX_ETH_RX_BUFFER_SIZE
00058    #define LPC23XX_ETH_RX_BUFFER_SIZE 1536
00059 #elif (LPC23XX_ETH_RX_BUFFER_SIZE != 1536)
00060    #error LPC23XX_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Ethernet interrupt priority
00064 #ifndef LPC23XX_ETH_IRQ_PRIORITY
00065    #define LPC23XX_ETH_IRQ_PRIORITY 15
00066 #elif (LPC23XX_ETH_IRQ_PRIORITY < 0)
00067    #error LPC23XX_ETH_IRQ_PRIORITY parameter is not valid
00068 #endif
00069 
00070 //MAC1 register
00071 #define MAC1_SOFT_RESET                0x00008000
00072 #define MAC1_SIMULATION_RESET          0x00004000
00073 #define MAC1_RESET_MCS_RX              0x00000800
00074 #define MAC1_RESET_RX                  0x00000400
00075 #define MAC1_RESET_MCS_TX              0x00000200
00076 #define MAC1_RESET_TX                  0x00000100
00077 #define MAC1_LOOPBACK                  0x00000010
00078 #define MAC1_TX_FLOW_CONTROL           0x00000008
00079 #define MAC1_RX_FLOW_CONTROL           0x00000004
00080 #define MAC1_PASS_ALL_FRAMES           0x00000002
00081 #define MAC1_RECEIVE_ENABLE            0x00000001
00082 
00083 //MAC2 register
00084 #define MAC2_EXCESS_DEFER              0x00004000
00085 #define MAC2_BACK_PRESSURE_NO_BACKOFF  0x00002000
00086 #define MAC2_NO_BACKOFF                0x00001000
00087 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200
00088 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100
00089 #define MAC2_AUTO_DETECT_PAD_ENABLE    0x00000080
00090 #define MAC2_VLAN_PAD_ENABLE           0x00000040
00091 #define MAC2_PAD_CRC_ENABLE            0x00000020
00092 #define MAC2_CRC_ENABLE                0x00000010
00093 #define MAC2_DELAYED_CRC               0x00000008
00094 #define MAC2_HUGE_FRAME_ENABLE         0x00000004
00095 #define MAC2_FRAME_LENGTH_CHECKING     0x00000002
00096 #define MAC2_FULL_DUPLEX               0x00000001
00097 
00098 //IPGT register
00099 #define IPGT_BACK_TO_BACK_IPG          0x0000007F
00100 #define IPGT_HALF_DUPLEX               0x00000012
00101 #define IPGT_FULL_DUPLEX               0x00000015
00102 
00103 //IPGR register
00104 #define IPGR_NON_BACK_TO_BACK_IPG1     0x00007F00
00105 #define IPGR_NON_BACK_TO_BACK_IPG2     0x0000007F
00106 #define IPGR_DEFAULT_VALUE             0x00000C12
00107 
00108 //CLRT register
00109 #define CLRT_COLLISION_WINDOW          0x00003F00
00110 #define CLRT_RETRANSMISSION_MAXIMUM    0x00003F00
00111 #define CLRT_DEFAULT_VALUE             0x0000370F
00112 
00113 //MAXF register
00114 #define MAXF_MAXIMUM_FRAME_LENGTH      0x0000FFFF
00115 
00116 //SUPP register
00117 #define SUPP_SPEED                     0x00000100
00118 
00119 //TEST register
00120 #define TEST_BACKPRESSURE              0x00000004
00121 #define TEST_PAUSE                     0x00000002
00122 #define TEST_SHORTCUT_PAUSE_QUANTA     0x00000001
00123 
00124 //MCFG register
00125 #define MCFG_RESET_MII_MGMT            0x00008000
00126 #define MCFG_CLOCK SELECT              0x0000001C
00127 #define MCFG_SUPPRESS_PREAMBLE         0x00000002
00128 #define MCFG_SCAN_INCREMENT            0x00000001
00129 
00130 #define MCFG_CLOCK_SELECT_DIV4         0x00000000
00131 #define MCFG_CLOCK_SELECT_DIV6         0x00000008
00132 #define MCFG_CLOCK_SELECT_DIV8         0x0000000C
00133 #define MCFG_CLOCK_SELECT_DIV10        0x00000010
00134 #define MCFG_CLOCK_SELECT_DIV14        0x00000014
00135 #define MCFG_CLOCK_SELECT_DIV20        0x00000018
00136 #define MCFG_CLOCK_SELECT_DIV28        0x0000001C
00137 
00138 //MCMD register
00139 #define MCMD_SCAN                      0x00000002
00140 #define MCMD_READ                      0x00000001
00141 
00142 //MADR register
00143 #define MADR_PHY_ADDRESS               0x00001F00
00144 #define MADR_REGISTER_ADDRESS          0x0000001F
00145 
00146 //MWTD register
00147 #define MWTD_WRITE_DATA                0x0000FFFF
00148 
00149 //MRDD register
00150 #define MRDD_READ_DATA                 0x0000FFFF
00151 
00152 //MIND register
00153 #define MIND_MII_LINK_FAIL             0x00000008
00154 #define MIND_NOT_VALID                 0x00000004
00155 #define MIND_SCANNING                  0x00000002
00156 #define MIND_BUSY                      0x00000001
00157 
00158 //Command register
00159 #define COMMAND_FULL_DUPLEX            0x00000400
00160 #define COMMAND_RMII                   0x00000200
00161 #define COMMAND_TX_FLOW_CONTROL        0x00000100
00162 #define COMMAND_PASS_RX_FILTER         0x00000080
00163 #define COMMAND_PASS_RUNT_FRAME        0x00000040
00164 #define COMMAND_RX_RESET               0x00000020
00165 #define COMMAND_TX_RESET               0x00000010
00166 #define COMMAND_REG_RESET              0x00000008
00167 #define COMMAND_TX_ENABLE              0x00000002
00168 #define COMMAND_RX_ENABLE              0x00000001
00169 
00170 //Status register
00171 #define STATUS_TX                      0x00000002
00172 #define STATUS_RX                      0x00000001
00173 
00174 //TSV0 register
00175 #define TSV0_VLAN                      0x80000000
00176 #define TSV0_BACKPRESSURE              0x40000000
00177 #define TSV0_PAUSE                     0x20000000
00178 #define TSV0_CONTROL_FRAME             0x10000000
00179 #define TSV0_TOTAL_BYTES               0x0FFFF000
00180 #define TSV0_UNDERRUN                  0x00000800
00181 #define TSV0_GIANT                     0x00000400
00182 #define TSV0_LATE_COLLISION            0x00000200
00183 #define TSV0_EXCESSIVE_COLLISION       0x00000100
00184 #define TSV0_EXCESSIVE_DEFER           0x00000080
00185 #define TSV0_PACKET_DEFER              0x00000040
00186 #define TSV0_BROADCAST                 0x00000020
00187 #define TSV0_MULTICAST                 0x00000010
00188 #define TSV0_DONE                      0x00000008
00189 #define TSV0_LENGTH_OUT_OF_RANGE       0x00000004
00190 #define TSV0_LENGTH_CHECK_ERROR        0x00000002
00191 #define TSV0_CRC_ERROR                 0x00000001
00192 
00193 //TSV1 register
00194 #define TSV1_TRANSMIT_COLLISION_COUNT  0x000F0000
00195 #define TSV1_TRANSMIT_BYTE_COUNT       0x0000FFFF
00196 
00197 //RSV register
00198 #define RSV_VLAN                       0x40000000
00199 #define RSV_UNSUPPORTED_OPCODE         0x20000000
00200 #define RSV_PAUSE                      0x10000000
00201 #define RSV_CONTROL_FRAME              0x08000000
00202 #define RSV_DRIBBLE_NIBBLE             0x04000000
00203 #define RSV_BROADCAST                  0x02000000
00204 #define RSV_MULTICAST                  0x01000000
00205 #define RSV_RECEIVE_OK                 0x00800000
00206 #define RSV_LENGTH_OUT_OF_RANGE        0x00400000
00207 #define RSV_LENGTH_CHECK_ERROR         0x00200000
00208 #define RSV_CRC_ERROR                  0x00100000
00209 #define RSV_RECEIVE_CODE_VIOLATION     0x00080000
00210 #define RSV_CARRIER_EVENT_PREV_SEEN    0x00040000
00211 #define RSV_RXDV_EVENT_PREV_SEEN       0x00020000
00212 #define RSV_PACKET_PREVIOUSLY_IGNORED  0x00010000
00213 #define RSV_RECEIVED_BYTE_COUNT        0x0000FFFF
00214 
00215 //FlowControlCounter register
00216 #define FCC_PAUSE_TIMER                0xFFFF0000
00217 #define FCC_MIRROR_COUNTER             0x0000FFFF
00218 
00219 //FlowControlStatus register
00220 #define FCS_MIRROR_COUNTER_CURRENT     0x0000FFFF
00221 
00222 //RxFilterCtrl register
00223 #define RFC_RX_FILTER_EN_WOL           0x00002000
00224 #define RFC_MAGIC_PACKET_EN_WOL        0x00001000
00225 #define RFC_ACCEPT_PERFECT_EN          0x00000020
00226 #define RFC_ACCEPT_MULTICAST_HASH_EN   0x00000010
00227 #define RFC_ACCEPT_UNICAST_HASH_EN     0x00000008
00228 #define RFC_ACCEPT_MULTICAST_EN        0x00000004
00229 #define RFC_ACCEPT_BROADCAST_EN        0x00000002
00230 #define RFC_ACCEPT_UNICAST_EN          0x00000001
00231 
00232 //RxFilterWoLStatus and RxFilterWoLClear registers
00233 #define RFWS_MAGIC_PACKET_WOL          0x00000100
00234 #define RFWS_RX_FILTER_WOL             0x00000080
00235 #define RFWS_ACCEPT_PERFECT_WOL        0x00000020
00236 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010
00237 #define RFWS_ACCEPT_UNICAST_HASH_WOL   0x00000008
00238 #define RFWS_ACCEPT_MULTICAST_WOL      0x00000004
00239 #define RFWS_ACCEPT_BROADCAST_WOL      0x00000002
00240 #define RFWS_ACCEPT_UNICAST_WOL        0x00000001
00241 
00242 //IntStatus, IntEnable, IntClear and IntSet registers
00243 #define INT_WAKEUP                     0x00002000
00244 #define INT_SOFT_INT                   0x00001000
00245 #define INT_TX_DONE                    0x00000080
00246 #define INT_TX_FINISHED                0x00000040
00247 #define INT_TX_ERROR                   0x00000020
00248 #define INT_TX_UNDERRUN                0x00000010
00249 #define INT_RX_DONE                    0x00000008
00250 #define INT_RX_FINISHED                0x00000004
00251 #define INT_RX_ERROR                   0x00000002
00252 #define INT_RX_OVERRUN                 0x00000001
00253 
00254 //Transmit descriptor control word
00255 #define TX_CTRL_INTERRUPT              0x80000000
00256 #define TX_CTRL_LAST                   0x40000000
00257 #define TX_CTRL_CRC                    0x20000000
00258 #define TX_CTRL_PAD                    0x10000000
00259 #define TX_CTRL_HUGE                   0x08000000
00260 #define TX_CTRL_OVERRIDE               0x04000000
00261 #define TX_CTRL_SIZE                   0x000007FF
00262 
00263 //Transmit status information word
00264 #define TX_STATUS_ERROR                0x80000000
00265 #define TX_STATUS_NO_DESCRIPTOR        0x40000000
00266 #define TX_STATUS_UNDERRUN             0x20000000
00267 #define TX_STATUS_LATE_COLLISION       0x10000000
00268 #define TX_STATUS_EXCESSIVE_COLLISION  0x08000000
00269 #define TX_STATUS_EXCESSIVE_DEFER      0x04000000
00270 #define TX_STATUS_DEFER                0x02000000
00271 #define TX_STATUS_COLLISION_COUNT      0x01E00000
00272 
00273 //Receive descriptor control word
00274 #define RX_CTRL_INTERRUPT              0x80000000
00275 #define RX_CTRL_SIZE                   0x000007FF
00276 
00277 //Receive status information word
00278 #define RX_STATUS_ERROR                0x80000000
00279 #define RX_STATUS_LAST_FLAG            0x40000000
00280 #define RX_STATUS_NO_DESCRIPTOR        0x20000000
00281 #define RX_STATUS_OVERRUN              0x10000000
00282 #define RX_STATUS_ALIGNMENT_ERROR      0x08000000
00283 #define RX_STATUS_RANGE_ERROR          0x04000000
00284 #define RX_STATUS_LENGTH_ERROR         0x02000000
00285 #define RX_STATUS_SYMBOL_ERROR         0x01000000
00286 #define RX_STATUS_CRC_ERROR            0x00800000
00287 #define RX_STATUS_BROADCAST            0x00400000
00288 #define RX_STATUS_MULTICAST            0x00200000
00289 #define RX_STATUS_FAIL_FILTER          0x00100000
00290 #define RX_STATUS_VLAN                 0x00080000
00291 #define RX_STATUS_CONTROL_FRAME        0x00040000
00292 #define RX_STATUS_SIZE                 0x000007FF
00293 
00294 //Receive status HashCRC word
00295 #define RX_HASH_CRC_DA                 0x001FF000
00296 #define RX_HASH_CRC_SA                 0x000001FF
00297 
00298 
00299 /**
00300  * @brief Transmit descriptor
00301  **/
00302 
00303 typedef struct
00304 {
00305    uint32_t packet;
00306    uint32_t control;
00307 } Lpc23xxTxDesc;
00308 
00309 
00310 /**
00311  * @brief Transmit status
00312  **/
00313 
00314 typedef struct
00315 {
00316    uint32_t info;
00317 } Lpc23xxTxStatus;
00318 
00319 
00320 /**
00321  * @brief Receive descriptor
00322  **/
00323 
00324 typedef struct
00325 {
00326    uint32_t packet;
00327    uint32_t control;
00328 } Lpc23xxRxDesc;
00329 
00330 
00331 /**
00332  * @brief Receive status
00333  **/
00334 
00335 typedef struct
00336 {
00337    uint32_t info;
00338    uint32_t hashCrc;
00339 } Lpc23xxRxStatus;
00340 
00341 
00342 //LPC23xx Ethernet MAC driver
00343 extern const NicDriver lpc23xxEthDriver;
00344 
00345 //LPC23xx Ethernet MAC related functions
00346 error_t lpc23xxEthInit(NetInterface *interface);
00347 void lpc23xxEthInitGpio(NetInterface *interface);
00348 void lpc23xxEthInitDesc(NetInterface *interface);
00349 
00350 void lpc23xxEthTick(NetInterface *interface);
00351 
00352 void lpc23xxEthEnableIrq(NetInterface *interface);
00353 void lpc23xxEthDisableIrq(NetInterface *interface);
00354 __irq void lpc23xxEthIrqHandler(void);
00355 void lpc23xxEthEventHandler(NetInterface *interface);
00356 
00357 error_t lpc23xxEthSendPacket(NetInterface *interface,
00358    const NetBuffer *buffer, size_t offset);
00359 
00360 error_t lpc23xxEthReceivePacket(NetInterface *interface);
00361 
00362 error_t lpc23xxEthSetMulticastFilter(NetInterface *interface);
00363 error_t lpc23xxEthUpdateMacConfig(NetInterface *interface);
00364 
00365 void lpc23xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00366 uint16_t lpc23xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00367 
00368 uint32_t lpc23xxEthCalcCrc(const void *data, size_t length);
00369 
00370 #endif
00371