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lpc176x_eth.h
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00001 /** 00002 * @file lpc176x_eth.h 00003 * @brief LPC1764/66/67/68/69 Ethernet MAC controller 00004 * 00005 * @section License 00006 * 00007 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved. 00008 * 00009 * This file is part of CycloneTCP Open. 00010 * 00011 * This program is free software; you can redistribute it and/or 00012 * modify it under the terms of the GNU General Public License 00013 * as published by the Free Software Foundation; either version 2 00014 * of the License, or (at your option) any later version. 00015 * 00016 * This program is distributed in the hope that it will be useful, 00017 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00019 * GNU General Public License for more details. 00020 * 00021 * You should have received a copy of the GNU General Public License 00022 * along with this program; if not, write to the Free Software Foundation, 00023 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00024 * 00025 * @author Oryx Embedded SARL (www.oryx-embedded.com) 00026 * @version 1.7.6 00027 **/ 00028 00029 #ifndef _LPC176X_ETH_H 00030 #define _LPC176X_ETH_H 00031 00032 //Dependencies 00033 #include "core/nic.h" 00034 00035 //Number of TX buffers 00036 #ifndef LPC176X_ETH_TX_BUFFER_COUNT 00037 #define LPC176X_ETH_TX_BUFFER_COUNT 2 00038 #elif (LPC176X_ETH_TX_BUFFER_COUNT < 1) 00039 #error LPC176X_ETH_TX_BUFFER_COUNT parameter is not valid 00040 #endif 00041 00042 //TX buffer size 00043 #ifndef LPC176X_ETH_TX_BUFFER_SIZE 00044 #define LPC176X_ETH_TX_BUFFER_SIZE 1536 00045 #elif (LPC176X_ETH_TX_BUFFER_SIZE != 1536) 00046 #error LPC176X_ETH_TX_BUFFER_SIZE parameter is not valid 00047 #endif 00048 00049 //Number of RX buffers 00050 #ifndef LPC176X_ETH_RX_BUFFER_COUNT 00051 #define LPC176X_ETH_RX_BUFFER_COUNT 4 00052 #elif (LPC176X_ETH_RX_BUFFER_COUNT < 1) 00053 #error LPC176X_ETH_RX_BUFFER_COUNT parameter is not valid 00054 #endif 00055 00056 //RX buffer size 00057 #ifndef LPC176X_ETH_RX_BUFFER_SIZE 00058 #define LPC176X_ETH_RX_BUFFER_SIZE 1536 00059 #elif (LPC176X_ETH_RX_BUFFER_SIZE != 1536) 00060 #error LPC176X_ETH_RX_BUFFER_SIZE parameter is not valid 00061 #endif 00062 00063 //Interrupt priority grouping 00064 #ifndef LPC176X_ETH_IRQ_PRIORITY_GROUPING 00065 #define LPC176X_ETH_IRQ_PRIORITY_GROUPING 2 00066 #elif (LPC176X_ETH_IRQ_PRIORITY_GROUPING < 0) 00067 #error LPC176X_ETH_IRQ_PRIORITY_GROUPING parameter is not valid 00068 #endif 00069 00070 //Ethernet interrupt group priority 00071 #ifndef LPC176X_ETH_IRQ_GROUP_PRIORITY 00072 #define LPC176X_ETH_IRQ_GROUP_PRIORITY 24 00073 #elif (LPC176X_ETH_IRQ_GROUP_PRIORITY < 0) 00074 #error LPC176X_ETH_IRQ_GROUP_PRIORITY parameter is not valid 00075 #endif 00076 00077 //Ethernet interrupt subpriority 00078 #ifndef LPC176X_ETH_IRQ_SUB_PRIORITY 00079 #define LPC176X_ETH_IRQ_SUB_PRIORITY 0 00080 #elif (LPC176X_ETH_IRQ_SUB_PRIORITY < 0) 00081 #error LPC176X_ETH_IRQ_SUB_PRIORITY parameter is not valid 00082 #endif 00083 00084 //MAC1 register 00085 #define MAC1_SOFT_RESET 0x00008000 00086 #define MAC1_SIMULATION_RESET 0x00004000 00087 #define MAC1_RESET_MCS_RX 0x00000800 00088 #define MAC1_RESET_RX 0x00000400 00089 #define MAC1_RESET_MCS_TX 0x00000200 00090 #define MAC1_RESET_TX 0x00000100 00091 #define MAC1_LOOPBACK 0x00000010 00092 #define MAC1_TX_FLOW_CONTROL 0x00000008 00093 #define MAC1_RX_FLOW_CONTROL 0x00000004 00094 #define MAC1_PASS_ALL_FRAMES 0x00000002 00095 #define MAC1_RECEIVE_ENABLE 0x00000001 00096 00097 //MAC2 register 00098 #define MAC2_EXCESS_DEFER 0x00004000 00099 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000 00100 #define MAC2_NO_BACKOFF 0x00001000 00101 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200 00102 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100 00103 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080 00104 #define MAC2_VLAN_PAD_ENABLE 0x00000040 00105 #define MAC2_PAD_CRC_ENABLE 0x00000020 00106 #define MAC2_CRC_ENABLE 0x00000010 00107 #define MAC2_DELAYED_CRC 0x00000008 00108 #define MAC2_HUGE_FRAME_ENABLE 0x00000004 00109 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002 00110 #define MAC2_FULL_DUPLEX 0x00000001 00111 00112 //IPGT register 00113 #define IPGT_BACK_TO_BACK_IPG 0x0000007F 00114 #define IPGT_HALF_DUPLEX 0x00000012 00115 #define IPGT_FULL_DUPLEX 0x00000015 00116 00117 //IPGR register 00118 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00 00119 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F 00120 #define IPGR_DEFAULT_VALUE 0x00000C12 00121 00122 //CLRT register 00123 #define CLRT_COLLISION_WINDOW 0x00003F00 00124 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00 00125 #define CLRT_DEFAULT_VALUE 0x0000370F 00126 00127 //MAXF register 00128 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF 00129 00130 //SUPP register 00131 #define SUPP_SPEED 0x00000100 00132 00133 //TEST register 00134 #define TEST_BACKPRESSURE 0x00000004 00135 #define TEST_PAUSE 0x00000002 00136 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001 00137 00138 //MCFG register 00139 #define MCFG_RESET_MII_MGMT 0x00008000 00140 #define MCFG_CLOCK SELECT 0x0000003C 00141 #define MCFG_SUPPRESS_PREAMBLE 0x00000002 00142 #define MCFG_SCAN_INCREMENT 0x00000001 00143 00144 #define MCFG_CLOCK_SELECT_DIV4 0x00000000 00145 #define MCFG_CLOCK_SELECT_DIV6 0x00000008 00146 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C 00147 #define MCFG_CLOCK_SELECT_DIV10 0x00000010 00148 #define MCFG_CLOCK_SELECT_DIV14 0x00000014 00149 #define MCFG_CLOCK_SELECT_DIV20 0x00000018 00150 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C 00151 #define MCFG_CLOCK_SELECT_DIV36 0x00000020 00152 #define MCFG_CLOCK_SELECT_DIV40 0x00000024 00153 #define MCFG_CLOCK_SELECT_DIV44 0x00000028 00154 #define MCFG_CLOCK_SELECT_DIV48 0x0000002C 00155 #define MCFG_CLOCK_SELECT_DIV52 0x00000030 00156 #define MCFG_CLOCK_SELECT_DIV56 0x00000034 00157 #define MCFG_CLOCK_SELECT_DIV60 0x00000038 00158 #define MCFG_CLOCK_SELECT_DIV64 0x0000003C 00159 00160 //MCMD register 00161 #define MCMD_SCAN 0x00000002 00162 #define MCMD_READ 0x00000001 00163 00164 //MADR register 00165 #define MADR_PHY_ADDRESS 0x00001F00 00166 #define MADR_REGISTER_ADDRESS 0x0000001F 00167 00168 //MWTD register 00169 #define MWTD_WRITE_DATA 0x0000FFFF 00170 00171 //MRDD register 00172 #define MRDD_READ_DATA 0x0000FFFF 00173 00174 //MIND register 00175 #define MIND_MII_LINK_FAIL 0x00000008 00176 #define MIND_NOT_VALID 0x00000004 00177 #define MIND_SCANNING 0x00000002 00178 #define MIND_BUSY 0x00000001 00179 00180 //Command register 00181 #define COMMAND_FULL_DUPLEX 0x00000400 00182 #define COMMAND_RMII 0x00000200 00183 #define COMMAND_TX_FLOW_CONTROL 0x00000100 00184 #define COMMAND_PASS_RX_FILTER 0x00000080 00185 #define COMMAND_PASS_RUNT_FRAME 0x00000040 00186 #define COMMAND_RX_RESET 0x00000020 00187 #define COMMAND_TX_RESET 0x00000010 00188 #define COMMAND_REG_RESET 0x00000008 00189 #define COMMAND_TX_ENABLE 0x00000002 00190 #define COMMAND_RX_ENABLE 0x00000001 00191 00192 //Status register 00193 #define STATUS_TX 0x00000002 00194 #define STATUS_RX 0x00000001 00195 00196 //TSV0 register 00197 #define TSV0_VLAN 0x80000000 00198 #define TSV0_BACKPRESSURE 0x40000000 00199 #define TSV0_PAUSE 0x20000000 00200 #define TSV0_CONTROL_FRAME 0x10000000 00201 #define TSV0_TOTAL_BYTES 0x0FFFF000 00202 #define TSV0_UNDERRUN 0x00000800 00203 #define TSV0_GIANT 0x00000400 00204 #define TSV0_LATE_COLLISION 0x00000200 00205 #define TSV0_EXCESSIVE_COLLISION 0x00000100 00206 #define TSV0_EXCESSIVE_DEFER 0x00000080 00207 #define TSV0_PACKET_DEFER 0x00000040 00208 #define TSV0_BROADCAST 0x00000020 00209 #define TSV0_MULTICAST 0x00000010 00210 #define TSV0_DONE 0x00000008 00211 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004 00212 #define TSV0_LENGTH_CHECK_ERROR 0x00000002 00213 #define TSV0_CRC_ERROR 0x00000001 00214 00215 //TSV1 register 00216 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000 00217 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF 00218 00219 //RSV register 00220 #define RSV_VLAN 0x40000000 00221 #define RSV_UNSUPPORTED_OPCODE 0x20000000 00222 #define RSV_PAUSE 0x10000000 00223 #define RSV_CONTROL_FRAME 0x08000000 00224 #define RSV_DRIBBLE_NIBBLE 0x04000000 00225 #define RSV_BROADCAST 0x02000000 00226 #define RSV_MULTICAST 0x01000000 00227 #define RSV_RECEIVE_OK 0x00800000 00228 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000 00229 #define RSV_LENGTH_CHECK_ERROR 0x00200000 00230 #define RSV_CRC_ERROR 0x00100000 00231 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000 00232 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000 00233 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000 00234 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000 00235 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF 00236 00237 //FlowControlCounter register 00238 #define FCC_PAUSE_TIMER 0xFFFF0000 00239 #define FCC_MIRROR_COUNTER 0x0000FFFF 00240 00241 //FlowControlStatus register 00242 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF 00243 00244 //RxFilterCtrl register 00245 #define RFC_RX_FILTER_EN_WOL 0x00002000 00246 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000 00247 #define RFC_ACCEPT_PERFECT_EN 0x00000020 00248 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010 00249 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008 00250 #define RFC_ACCEPT_MULTICAST_EN 0x00000004 00251 #define RFC_ACCEPT_BROADCAST_EN 0x00000002 00252 #define RFC_ACCEPT_UNICAST_EN 0x00000001 00253 00254 //RxFilterWoLStatus and RxFilterWoLClear registers 00255 #define RFWS_MAGIC_PACKET_WOL 0x00000100 00256 #define RFWS_RX_FILTER_WOL 0x00000080 00257 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020 00258 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010 00259 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008 00260 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004 00261 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002 00262 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001 00263 00264 //IntStatus, IntEnable, IntClear and IntSet registers 00265 #define INT_WAKEUP 0x00002000 00266 #define INT_SOFT_INT 0x00001000 00267 #define INT_TX_DONE 0x00000080 00268 #define INT_TX_FINISHED 0x00000040 00269 #define INT_TX_ERROR 0x00000020 00270 #define INT_TX_UNDERRUN 0x00000010 00271 #define INT_RX_DONE 0x00000008 00272 #define INT_RX_FINISHED 0x00000004 00273 #define INT_RX_ERROR 0x00000002 00274 #define INT_RX_OVERRUN 0x00000001 00275 00276 //Transmit descriptor control word 00277 #define TX_CTRL_INTERRUPT 0x80000000 00278 #define TX_CTRL_LAST 0x40000000 00279 #define TX_CTRL_CRC 0x20000000 00280 #define TX_CTRL_PAD 0x10000000 00281 #define TX_CTRL_HUGE 0x08000000 00282 #define TX_CTRL_OVERRIDE 0x04000000 00283 #define TX_CTRL_SIZE 0x000007FF 00284 00285 //Transmit status information word 00286 #define TX_STATUS_ERROR 0x80000000 00287 #define TX_STATUS_NO_DESCRIPTOR 0x40000000 00288 #define TX_STATUS_UNDERRUN 0x20000000 00289 #define TX_STATUS_LATE_COLLISION 0x10000000 00290 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000 00291 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000 00292 #define TX_STATUS_DEFER 0x02000000 00293 #define TX_STATUS_COLLISION_COUNT 0x01E00000 00294 00295 //Receive descriptor control word 00296 #define RX_CTRL_INTERRUPT 0x80000000 00297 #define RX_CTRL_SIZE 0x000007FF 00298 00299 //Receive status information word 00300 #define RX_STATUS_ERROR 0x80000000 00301 #define RX_STATUS_LAST_FLAG 0x40000000 00302 #define RX_STATUS_NO_DESCRIPTOR 0x20000000 00303 #define RX_STATUS_OVERRUN 0x10000000 00304 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000 00305 #define RX_STATUS_RANGE_ERROR 0x04000000 00306 #define RX_STATUS_LENGTH_ERROR 0x02000000 00307 #define RX_STATUS_SYMBOL_ERROR 0x01000000 00308 #define RX_STATUS_CRC_ERROR 0x00800000 00309 #define RX_STATUS_BROADCAST 0x00400000 00310 #define RX_STATUS_MULTICAST 0x00200000 00311 #define RX_STATUS_FAIL_FILTER 0x00100000 00312 #define RX_STATUS_VLAN 0x00080000 00313 #define RX_STATUS_CONTROL_FRAME 0x00040000 00314 #define RX_STATUS_SIZE 0x000007FF 00315 00316 //Receive status HashCRC word 00317 #define RX_HASH_CRC_DA 0x001FF000 00318 #define RX_HASH_CRC_SA 0x000001FF 00319 00320 00321 /** 00322 * @brief Transmit descriptor 00323 **/ 00324 00325 typedef struct 00326 { 00327 uint32_t packet; 00328 uint32_t control; 00329 } Lpc176xTxDesc; 00330 00331 00332 /** 00333 * @brief Transmit status 00334 **/ 00335 00336 typedef struct 00337 { 00338 uint32_t info; 00339 } Lpc176xTxStatus; 00340 00341 00342 /** 00343 * @brief Receive descriptor 00344 **/ 00345 00346 typedef struct 00347 { 00348 uint32_t packet; 00349 uint32_t control; 00350 } Lpc176xRxDesc; 00351 00352 00353 /** 00354 * @brief Receive status 00355 **/ 00356 00357 typedef struct 00358 { 00359 uint32_t info; 00360 uint32_t hashCrc; 00361 } Lpc176xRxStatus; 00362 00363 00364 //LPC176x Ethernet MAC driver 00365 extern const NicDriver lpc176xEthDriver; 00366 00367 //LPC176x Ethernet MAC related functions 00368 error_t lpc176xEthInit(NetInterface *interface); 00369 void lpc176xEthInitGpio(NetInterface *interface); 00370 void lpc176xEthInitDesc(NetInterface *interface); 00371 00372 void lpc176xEthTick(NetInterface *interface); 00373 00374 void lpc176xEthEnableIrq(NetInterface *interface); 00375 void lpc176xEthDisableIrq(NetInterface *interface); 00376 void lpc176xEthEventHandler(NetInterface *interface); 00377 00378 error_t lpc176xEthSendPacket(NetInterface *interface, 00379 const NetBuffer *buffer, size_t offset); 00380 00381 error_t lpc176xEthReceivePacket(NetInterface *interface); 00382 00383 error_t lpc176xEthSetMulticastFilter(NetInterface *interface); 00384 error_t lpc176xEthUpdateMacConfig(NetInterface *interface); 00385 00386 void lpc176xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data); 00387 uint16_t lpc176xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr); 00388 00389 uint32_t lpc176xEthCalcCrc(const void *data, size_t length); 00390 00391 #endif 00392
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