Webserver+3d print
Embed:
(wiki syntax)
Show/hide line numbers
lpc175x_eth.h
Go to the documentation of this file.
00001 /** 00002 * @file lpc175x_eth.h 00003 * @brief LPC1758 Ethernet MAC controller 00004 * 00005 * @section License 00006 * 00007 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved. 00008 * 00009 * This file is part of CycloneTCP Open. 00010 * 00011 * This program is free software; you can redistribute it and/or 00012 * modify it under the terms of the GNU General Public License 00013 * as published by the Free Software Foundation; either version 2 00014 * of the License, or (at your option) any later version. 00015 * 00016 * This program is distributed in the hope that it will be useful, 00017 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00019 * GNU General Public License for more details. 00020 * 00021 * You should have received a copy of the GNU General Public License 00022 * along with this program; if not, write to the Free Software Foundation, 00023 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00024 * 00025 * @author Oryx Embedded SARL (www.oryx-embedded.com) 00026 * @version 1.7.6 00027 **/ 00028 00029 #ifndef _LPC175X_ETH_H 00030 #define _LPC175X_ETH_H 00031 00032 //Dependencies 00033 #include "core/nic.h" 00034 00035 //Number of TX buffers 00036 #ifndef LPC175X_ETH_TX_BUFFER_COUNT 00037 #define LPC175X_ETH_TX_BUFFER_COUNT 2 00038 #elif (LPC175X_ETH_TX_BUFFER_COUNT < 1) 00039 #error LPC175X_ETH_TX_BUFFER_COUNT parameter is not valid 00040 #endif 00041 00042 //TX buffer size 00043 #ifndef LPC175X_ETH_TX_BUFFER_SIZE 00044 #define LPC175X_ETH_TX_BUFFER_SIZE 1536 00045 #elif (LPC175X_ETH_TX_BUFFER_SIZE != 1536) 00046 #error LPC175X_ETH_TX_BUFFER_SIZE parameter is not valid 00047 #endif 00048 00049 //Number of RX buffers 00050 #ifndef LPC175X_ETH_RX_BUFFER_COUNT 00051 #define LPC175X_ETH_RX_BUFFER_COUNT 4 00052 #elif (LPC175X_ETH_RX_BUFFER_COUNT < 1) 00053 #error LPC175X_ETH_RX_BUFFER_COUNT parameter is not valid 00054 #endif 00055 00056 //RX buffer size 00057 #ifndef LPC175X_ETH_RX_BUFFER_SIZE 00058 #define LPC175X_ETH_RX_BUFFER_SIZE 1536 00059 #elif (LPC175X_ETH_RX_BUFFER_SIZE != 1536) 00060 #error LPC175X_ETH_RX_BUFFER_SIZE parameter is not valid 00061 #endif 00062 00063 //Interrupt priority grouping 00064 #ifndef LPC175X_ETH_IRQ_PRIORITY_GROUPING 00065 #define LPC175X_ETH_IRQ_PRIORITY_GROUPING 2 00066 #elif (LPC175X_ETH_IRQ_PRIORITY_GROUPING < 0) 00067 #error LPC175X_ETH_IRQ_PRIORITY_GROUPING parameter is not valid 00068 #endif 00069 00070 //Ethernet interrupt group priority 00071 #ifndef LPC175X_ETH_IRQ_GROUP_PRIORITY 00072 #define LPC175X_ETH_IRQ_GROUP_PRIORITY 24 00073 #elif (LPC175X_ETH_IRQ_GROUP_PRIORITY < 0) 00074 #error LPC175X_ETH_IRQ_GROUP_PRIORITY parameter is not valid 00075 #endif 00076 00077 //Ethernet interrupt subpriority 00078 #ifndef LPC175X_ETH_IRQ_SUB_PRIORITY 00079 #define LPC175X_ETH_IRQ_SUB_PRIORITY 0 00080 #elif (LPC175X_ETH_IRQ_SUB_PRIORITY < 0) 00081 #error LPC175X_ETH_IRQ_SUB_PRIORITY parameter is not valid 00082 #endif 00083 00084 //MDC pin 00085 #ifndef LPC175X_ETH_MDC_GPIO 00086 #define LPC175X_ETH_MDC_GPIO LPC_GPIO2 00087 #endif 00088 00089 #ifndef LPC175X_ETH_MDC_MASK 00090 #define LPC175X_ETH_MDC_MASK (1 << 8) 00091 #endif 00092 00093 //MDIO pin 00094 #ifndef LPC175X_ETH_MDIO_GPIO 00095 #define LPC175X_ETH_MDIO_GPIO LPC_GPIO2 00096 #endif 00097 00098 #ifndef LPC175X_ETH_MDIO_MASK 00099 #define LPC175X_ETH_MDIO_MASK (1 << 9) 00100 #endif 00101 00102 //MAC1 register 00103 #define MAC1_SOFT_RESET 0x00008000 00104 #define MAC1_SIMULATION_RESET 0x00004000 00105 #define MAC1_RESET_MCS_RX 0x00000800 00106 #define MAC1_RESET_RX 0x00000400 00107 #define MAC1_RESET_MCS_TX 0x00000200 00108 #define MAC1_RESET_TX 0x00000100 00109 #define MAC1_LOOPBACK 0x00000010 00110 #define MAC1_TX_FLOW_CONTROL 0x00000008 00111 #define MAC1_RX_FLOW_CONTROL 0x00000004 00112 #define MAC1_PASS_ALL_FRAMES 0x00000002 00113 #define MAC1_RECEIVE_ENABLE 0x00000001 00114 00115 //MAC2 register 00116 #define MAC2_EXCESS_DEFER 0x00004000 00117 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000 00118 #define MAC2_NO_BACKOFF 0x00001000 00119 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200 00120 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100 00121 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080 00122 #define MAC2_VLAN_PAD_ENABLE 0x00000040 00123 #define MAC2_PAD_CRC_ENABLE 0x00000020 00124 #define MAC2_CRC_ENABLE 0x00000010 00125 #define MAC2_DELAYED_CRC 0x00000008 00126 #define MAC2_HUGE_FRAME_ENABLE 0x00000004 00127 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002 00128 #define MAC2_FULL_DUPLEX 0x00000001 00129 00130 //IPGT register 00131 #define IPGT_BACK_TO_BACK_IPG 0x0000007F 00132 #define IPGT_HALF_DUPLEX 0x00000012 00133 #define IPGT_FULL_DUPLEX 0x00000015 00134 00135 //IPGR register 00136 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00 00137 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F 00138 #define IPGR_DEFAULT_VALUE 0x00000C12 00139 00140 //CLRT register 00141 #define CLRT_COLLISION_WINDOW 0x00003F00 00142 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00 00143 #define CLRT_DEFAULT_VALUE 0x0000370F 00144 00145 //MAXF register 00146 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF 00147 00148 //SUPP register 00149 #define SUPP_SPEED 0x00000100 00150 00151 //TEST register 00152 #define TEST_BACKPRESSURE 0x00000004 00153 #define TEST_PAUSE 0x00000002 00154 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001 00155 00156 //MCFG register 00157 #define MCFG_RESET_MII_MGMT 0x00008000 00158 #define MCFG_CLOCK SELECT 0x0000003C 00159 #define MCFG_SUPPRESS_PREAMBLE 0x00000002 00160 #define MCFG_SCAN_INCREMENT 0x00000001 00161 00162 #define MCFG_CLOCK_SELECT_DIV4 0x00000000 00163 #define MCFG_CLOCK_SELECT_DIV6 0x00000008 00164 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C 00165 #define MCFG_CLOCK_SELECT_DIV10 0x00000010 00166 #define MCFG_CLOCK_SELECT_DIV14 0x00000014 00167 #define MCFG_CLOCK_SELECT_DIV20 0x00000018 00168 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C 00169 #define MCFG_CLOCK_SELECT_DIV36 0x00000020 00170 #define MCFG_CLOCK_SELECT_DIV40 0x00000024 00171 #define MCFG_CLOCK_SELECT_DIV44 0x00000028 00172 #define MCFG_CLOCK_SELECT_DIV48 0x0000002C 00173 #define MCFG_CLOCK_SELECT_DIV52 0x00000030 00174 #define MCFG_CLOCK_SELECT_DIV56 0x00000034 00175 #define MCFG_CLOCK_SELECT_DIV60 0x00000038 00176 #define MCFG_CLOCK_SELECT_DIV64 0x0000003C 00177 00178 //MCMD register 00179 #define MCMD_SCAN 0x00000002 00180 #define MCMD_READ 0x00000001 00181 00182 //MADR register 00183 #define MADR_PHY_ADDRESS 0x00001F00 00184 #define MADR_REGISTER_ADDRESS 0x0000001F 00185 00186 //MWTD register 00187 #define MWTD_WRITE_DATA 0x0000FFFF 00188 00189 //MRDD register 00190 #define MRDD_READ_DATA 0x0000FFFF 00191 00192 //MIND register 00193 #define MIND_MII_LINK_FAIL 0x00000008 00194 #define MIND_NOT_VALID 0x00000004 00195 #define MIND_SCANNING 0x00000002 00196 #define MIND_BUSY 0x00000001 00197 00198 //Command register 00199 #define COMMAND_FULL_DUPLEX 0x00000400 00200 #define COMMAND_RMII 0x00000200 00201 #define COMMAND_TX_FLOW_CONTROL 0x00000100 00202 #define COMMAND_PASS_RX_FILTER 0x00000080 00203 #define COMMAND_PASS_RUNT_FRAME 0x00000040 00204 #define COMMAND_RX_RESET 0x00000020 00205 #define COMMAND_TX_RESET 0x00000010 00206 #define COMMAND_REG_RESET 0x00000008 00207 #define COMMAND_TX_ENABLE 0x00000002 00208 #define COMMAND_RX_ENABLE 0x00000001 00209 00210 //Status register 00211 #define STATUS_TX 0x00000002 00212 #define STATUS_RX 0x00000001 00213 00214 //TSV0 register 00215 #define TSV0_VLAN 0x80000000 00216 #define TSV0_BACKPRESSURE 0x40000000 00217 #define TSV0_PAUSE 0x20000000 00218 #define TSV0_CONTROL_FRAME 0x10000000 00219 #define TSV0_TOTAL_BYTES 0x0FFFF000 00220 #define TSV0_UNDERRUN 0x00000800 00221 #define TSV0_GIANT 0x00000400 00222 #define TSV0_LATE_COLLISION 0x00000200 00223 #define TSV0_EXCESSIVE_COLLISION 0x00000100 00224 #define TSV0_EXCESSIVE_DEFER 0x00000080 00225 #define TSV0_PACKET_DEFER 0x00000040 00226 #define TSV0_BROADCAST 0x00000020 00227 #define TSV0_MULTICAST 0x00000010 00228 #define TSV0_DONE 0x00000008 00229 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004 00230 #define TSV0_LENGTH_CHECK_ERROR 0x00000002 00231 #define TSV0_CRC_ERROR 0x00000001 00232 00233 //TSV1 register 00234 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000 00235 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF 00236 00237 //RSV register 00238 #define RSV_VLAN 0x40000000 00239 #define RSV_UNSUPPORTED_OPCODE 0x20000000 00240 #define RSV_PAUSE 0x10000000 00241 #define RSV_CONTROL_FRAME 0x08000000 00242 #define RSV_DRIBBLE_NIBBLE 0x04000000 00243 #define RSV_BROADCAST 0x02000000 00244 #define RSV_MULTICAST 0x01000000 00245 #define RSV_RECEIVE_OK 0x00800000 00246 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000 00247 #define RSV_LENGTH_CHECK_ERROR 0x00200000 00248 #define RSV_CRC_ERROR 0x00100000 00249 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000 00250 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000 00251 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000 00252 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000 00253 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF 00254 00255 //FlowControlCounter register 00256 #define FCC_PAUSE_TIMER 0xFFFF0000 00257 #define FCC_MIRROR_COUNTER 0x0000FFFF 00258 00259 //FlowControlStatus register 00260 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF 00261 00262 //RxFilterCtrl register 00263 #define RFC_RX_FILTER_EN_WOL 0x00002000 00264 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000 00265 #define RFC_ACCEPT_PERFECT_EN 0x00000020 00266 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010 00267 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008 00268 #define RFC_ACCEPT_MULTICAST_EN 0x00000004 00269 #define RFC_ACCEPT_BROADCAST_EN 0x00000002 00270 #define RFC_ACCEPT_UNICAST_EN 0x00000001 00271 00272 //RxFilterWoLStatus and RxFilterWoLClear registers 00273 #define RFWS_MAGIC_PACKET_WOL 0x00000100 00274 #define RFWS_RX_FILTER_WOL 0x00000080 00275 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020 00276 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010 00277 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008 00278 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004 00279 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002 00280 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001 00281 00282 //IntStatus, IntEnable, IntClear and IntSet registers 00283 #define INT_WAKEUP 0x00002000 00284 #define INT_SOFT_INT 0x00001000 00285 #define INT_TX_DONE 0x00000080 00286 #define INT_TX_FINISHED 0x00000040 00287 #define INT_TX_ERROR 0x00000020 00288 #define INT_TX_UNDERRUN 0x00000010 00289 #define INT_RX_DONE 0x00000008 00290 #define INT_RX_FINISHED 0x00000004 00291 #define INT_RX_ERROR 0x00000002 00292 #define INT_RX_OVERRUN 0x00000001 00293 00294 //Transmit descriptor control word 00295 #define TX_CTRL_INTERRUPT 0x80000000 00296 #define TX_CTRL_LAST 0x40000000 00297 #define TX_CTRL_CRC 0x20000000 00298 #define TX_CTRL_PAD 0x10000000 00299 #define TX_CTRL_HUGE 0x08000000 00300 #define TX_CTRL_OVERRIDE 0x04000000 00301 #define TX_CTRL_SIZE 0x000007FF 00302 00303 //Transmit status information word 00304 #define TX_STATUS_ERROR 0x80000000 00305 #define TX_STATUS_NO_DESCRIPTOR 0x40000000 00306 #define TX_STATUS_UNDERRUN 0x20000000 00307 #define TX_STATUS_LATE_COLLISION 0x10000000 00308 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000 00309 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000 00310 #define TX_STATUS_DEFER 0x02000000 00311 #define TX_STATUS_COLLISION_COUNT 0x01E00000 00312 00313 //Receive descriptor control word 00314 #define RX_CTRL_INTERRUPT 0x80000000 00315 #define RX_CTRL_SIZE 0x000007FF 00316 00317 //Receive status information word 00318 #define RX_STATUS_ERROR 0x80000000 00319 #define RX_STATUS_LAST_FLAG 0x40000000 00320 #define RX_STATUS_NO_DESCRIPTOR 0x20000000 00321 #define RX_STATUS_OVERRUN 0x10000000 00322 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000 00323 #define RX_STATUS_RANGE_ERROR 0x04000000 00324 #define RX_STATUS_LENGTH_ERROR 0x02000000 00325 #define RX_STATUS_SYMBOL_ERROR 0x01000000 00326 #define RX_STATUS_CRC_ERROR 0x00800000 00327 #define RX_STATUS_BROADCAST 0x00400000 00328 #define RX_STATUS_MULTICAST 0x00200000 00329 #define RX_STATUS_FAIL_FILTER 0x00100000 00330 #define RX_STATUS_VLAN 0x00080000 00331 #define RX_STATUS_CONTROL_FRAME 0x00040000 00332 #define RX_STATUS_SIZE 0x000007FF 00333 00334 //Receive status HashCRC word 00335 #define RX_HASH_CRC_DA 0x001FF000 00336 #define RX_HASH_CRC_SA 0x000001FF 00337 00338 //Serial Management Interface 00339 #define SMI_SYNC 0xFFFFFFFF 00340 #define SMI_START 0x00000001 00341 #define SMI_WRITE 0x00000001 00342 #define SMI_READ 0x00000002 00343 #define SMI_TA 0x00000002 00344 00345 00346 /** 00347 * @brief Transmit descriptor 00348 **/ 00349 00350 typedef struct 00351 { 00352 uint32_t packet; 00353 uint32_t control; 00354 } Lpc175xTxDesc; 00355 00356 00357 /** 00358 * @brief Transmit status 00359 **/ 00360 00361 typedef struct 00362 { 00363 uint32_t info; 00364 } Lpc175xTxStatus; 00365 00366 00367 /** 00368 * @brief Receive descriptor 00369 **/ 00370 00371 typedef struct 00372 { 00373 uint32_t packet; 00374 uint32_t control; 00375 } Lpc175xRxDesc; 00376 00377 00378 /** 00379 * @brief Receive status 00380 **/ 00381 00382 typedef struct 00383 { 00384 uint32_t info; 00385 uint32_t hashCrc; 00386 } Lpc175xRxStatus; 00387 00388 00389 //LPC175x Ethernet MAC driver 00390 extern const NicDriver lpc175xEthDriver; 00391 00392 //LPC175x Ethernet MAC related functions 00393 error_t lpc175xEthInit(NetInterface *interface); 00394 void lpc175xEthInitGpio(NetInterface *interface); 00395 void lpc175xEthInitDesc(NetInterface *interface); 00396 00397 void lpc175xEthTick(NetInterface *interface); 00398 00399 void lpc175xEthEnableIrq(NetInterface *interface); 00400 void lpc175xEthDisableIrq(NetInterface *interface); 00401 void lpc175xEthEventHandler(NetInterface *interface); 00402 00403 error_t lpc175xEthSendPacket(NetInterface *interface, 00404 const NetBuffer *buffer, size_t offset); 00405 00406 error_t lpc175xEthReceivePacket(NetInterface *interface); 00407 00408 error_t lpc175xEthSetMulticastFilter(NetInterface *interface); 00409 error_t lpc175xEthUpdateMacConfig(NetInterface *interface); 00410 00411 void lpc175xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data); 00412 uint16_t lpc175xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr); 00413 00414 void lpc175xEthWriteSmi(uint32_t data, uint_t length); 00415 uint32_t lpc175xEthReadSmi(uint_t length); 00416 00417 uint32_t lpc175xEthCalcCrc(const void *data, size_t length); 00418 00419 #endif 00420
Generated on Tue Jul 12 2022 17:10:14 by
1.7.2