lan9303.h

00001 /**
00002  * @file lan9303.h
00003  * @brief LAN9303 Ethernet switch
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _LAN9303_H
00030 #define _LAN9303_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //LAN9303 ports
00036 #define LAN9303_PORT1               1
00037 #define LAN9303_PORT2               2
00038 
00039 //LAN9303 PHY registers
00040 #define LAN9303_PHY_REG_BMCR        0x00
00041 #define LAN9303_PHY_REG_BMSR        0x01
00042 #define LAN9303_PHY_REG_PHYIDR1     0x02
00043 #define LAN9303_PHY_REG_PHYIDR2     0x03
00044 #define LAN9303_PHY_REG_ANAR        0x04
00045 #define LAN9303_PHY_REG_ANLPAR      0x05
00046 #define LAN9303_PHY_REG_ANER        0x06
00047 #define LAN9303_PHY_REG_MCSR        0x11
00048 #define LAN9303_PHY_REG_SMR         0x12
00049 #define LAN9303_PHY_REG_SCSIR       0x1B
00050 #define LAN9303_PHY_REG_PISR        0x1D
00051 #define LAN9303_PHY_REG_PIMR        0x1E
00052 #define LAN9303_PHY_REG_PSCSR       0x1F
00053 
00054 //BMCR register
00055 #define BMCR_RESET                  (1 << 15)
00056 #define BMCR_LOOPBACK               (1 << 14)
00057 #define BMCR_SPEED_SEL              (1 << 13)
00058 #define BMCR_AN_EN                  (1 << 12)
00059 #define BMCR_POWER_DOWN             (1 << 11)
00060 #define BMCR_ISOLATE                (1 << 10)
00061 #define BMCR_RESTART_AN             (1 << 9)
00062 #define BMCR_DUPLEX_MODE            (1 << 8)
00063 #define BMCR_COL_TEST               (1 << 7)
00064 
00065 //BMSR register
00066 #define BMSR_100BT4                 (1 << 15)
00067 #define BMSR_100BTX_FD              (1 << 14)
00068 #define BMSR_100BTX                 (1 << 13)
00069 #define BMSR_10BT_FD                (1 << 12)
00070 #define BMSR_10BT                   (1 << 11)
00071 #define BMSR_100BT2_FD              (1 << 10)
00072 #define BMSR_100BT2                 (1 << 9)
00073 #define BMSR_EXTENTED_STATUS        (1 << 8)
00074 #define BMSR_AN_COMPLETE            (1 << 5)
00075 #define BMSR_REMOTE_FAULT           (1 << 4)
00076 #define BMSR_AN_ABLE                (1 << 3)
00077 #define BMSR_LINK_STATUS            (1 << 2)
00078 #define BMSR_JABBER_DETECT          (1 << 1)
00079 #define BMSR_EXTENDED_CAP           (1 << 0)
00080 
00081 //ANAR register
00082 #define ANAR_RF                     (1 << 13)
00083 #define ANAR_PAUSE1                 (1 << 11)
00084 #define ANAR_PAUSE0                 (1 << 10)
00085 #define ANAR_100BTX_FD              (1 << 8)
00086 #define ANAR_100BTX                 (1 << 7)
00087 #define ANAR_10BT_FD                (1 << 6)
00088 #define ANAR_10BT                   (1 << 5)
00089 #define ANAR_SELECTOR4              (1 << 4)
00090 #define ANAR_SELECTOR3              (1 << 3)
00091 #define ANAR_SELECTOR2              (1 << 2)
00092 #define ANAR_SELECTOR1              (1 << 1)
00093 #define ANAR_SELECTOR0              (1 << 0)
00094 
00095 //ANLPAR register
00096 #define ANLPAR_NP                   (1 << 15)
00097 #define ANLPAR_ACK                  (1 << 14)
00098 #define ANLPAR_RF                   (1 << 13)
00099 #define ANLPAR_PAUSE1               (1 << 11)
00100 #define ANLPAR_PAUSE0               (1 << 10)
00101 #define ANLPAR_100BT4               (1 << 9)
00102 #define ANLPAR_100BTX_FD            (1 << 8)
00103 #define ANLPAR_100BTX               (1 << 7)
00104 #define ANLPAR_10BT_FD              (1 << 6)
00105 #define ANLPAR_10BT                 (1 << 5)
00106 #define ANLPAR_SELECTOR4            (1 << 4)
00107 #define ANLPAR_SELECTOR3            (1 << 3)
00108 #define ANLPAR_SELECTOR2            (1 << 2)
00109 #define ANLPAR_SELECTOR1            (1 << 1)
00110 #define ANLPAR_SELECTOR0            (1 << 0)
00111 
00112 //ANER register
00113 #define ANER_PDF                    (1 << 4)
00114 #define ANER_LP_NP_ABLE             (1 << 3)
00115 #define ANER_NP_ABLE                (1 << 2)
00116 #define ANER_PAGE_RX                (1 << 1)
00117 #define ANER_LP_AN_ABLE             (1 << 0)
00118 
00119 //MCSR register
00120 #define MCSR_EDPWRDOWN              (1 << 13)
00121 #define MCSR_ENERGYON               (1 << 1)
00122 
00123 //SMR register
00124 #define SMR_MODE2                   (1 << 7)
00125 #define SMR_MODE1                   (1 << 6)
00126 #define SMR_MODE0                   (1 << 5)
00127 #define SMR_PHYAD4                  (1 << 4)
00128 #define SMR_PHYAD3                  (1 << 3)
00129 #define SMR_PHYAD2                  (1 << 2)
00130 #define SMR_PHYAD1                  (1 << 1)
00131 #define SMR_PHYAD0                  (1 << 0)
00132 
00133 //SCSIR register
00134 #define SCSIR_AMDIXCTRL             (1 << 15)
00135 #define SCSIR_AMDIXEN               (1 << 14)
00136 #define SCSIR_AMDIXSTATE            (1 << 13)
00137 #define SCSIR_SQEOFF                (1 << 11)
00138 #define SCSIR_VCOOFF_LP             (1 << 10)
00139 #define SCSIR_XPOL                  (1 << 4)
00140 
00141 //ISR register
00142 #define ISR_ENERGYON                (1 << 7)
00143 #define ISR_AN_COMPLETE             (1 << 6)
00144 #define ISR_REMOTE_FAULT            (1 << 5)
00145 #define ISR_LINK_DOWN               (1 << 4)
00146 #define ISR_AN_LP_ACK               (1 << 3)
00147 #define ISR_PD_FAULT                (1 << 2)
00148 #define ISR_AN_PAGE_RECEIVED        (1 << 1)
00149 
00150 //IMR register
00151 #define IMR_ENERGYON                (1 << 7)
00152 #define IMR_AN_COMPLETE             (1 << 6)
00153 #define IMR_REMOTE_FAULT            (1 << 5)
00154 #define IMR_LINK_DOWN               (1 << 4)
00155 #define IMR_AN_LP_ACK               (1 << 3)
00156 #define IMR_PD_FAULT                (1 << 2)
00157 #define IMR_AN_PAGE_RECEIVED        (1 << 1)
00158 
00159 //PSCSR register
00160 #define PSCSR_AUTODONE              (1 << 12)
00161 #define PSCSR_HCDSPEED2             (1 << 4)
00162 #define PSCSR_HCDSPEED1             (1 << 3)
00163 #define PSCSR_HCDSPEED0             (1 << 2)
00164 
00165 //Speed indication
00166 #define PSCSR_HCDSPEED_MASK         (7 << 2)
00167 #define PSCSR_HCDSPEED_10BT         (1 << 2)
00168 #define PSCSR_HCDSPEED_100BTX       (2 << 2)
00169 #define PSCSR_HCDSPEED_10BT_FD      (5 << 2)
00170 #define PSCSR_HCDSPEED_100BTX_FD    (6 << 2)
00171 
00172 //LAN9303 Ethernet switch driver
00173 extern const PhyDriver lan9303PhyDriver;
00174 
00175 //LAN9303 related functions
00176 error_t lan9303Init(NetInterface *interface);
00177 
00178 bool_t lan9303GetLinkState(NetInterface *interface, uint8_t port);
00179 
00180 void lan9303Tick(NetInterface *interface);
00181 
00182 void lan9303EnableIrq(NetInterface *interface);
00183 void lan9303DisableIrq(NetInterface *interface);
00184 
00185 void lan9303EventHandler(NetInterface *interface);
00186 
00187 void lan9303WritePhyReg(NetInterface *interface,
00188    uint8_t port, uint8_t address, uint16_t data);
00189 
00190 uint16_t lan9303ReadPhyReg(NetInterface *interface,
00191    uint8_t port, uint8_t address);
00192 
00193 void lan9303DumpPhyReg(NetInterface *interface, uint8_t port);
00194 
00195 void lan9303WriteSmiReg(NetInterface *interface, uint16_t address,
00196    uint32_t data);
00197 
00198 uint32_t lan9303ReadSmiReg(NetInterface *interface, uint16_t address);
00199 
00200 void lan9303DumpSmiReg(NetInterface *interface);
00201 
00202 #endif
00203