lan8742.h

00001 /**
00002  * @file lan8742.h
00003  * @brief LAN8742 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _LAN8742_H
00030 #define _LAN8742_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef LAN8742_PHY_ADDR
00037    #define LAN8742_PHY_ADDR 0
00038 #elif (LAN8742_PHY_ADDR < 0 || LAN8742_PHY_ADDR > 31)
00039    #error LAN8742_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //LAN8742 registers
00043 #define LAN8742_PHY_REG_BMCR        0x00
00044 #define LAN8742_PHY_REG_BMSR        0x01
00045 #define LAN8742_PHY_REG_PHYIDR1     0x02
00046 #define LAN8742_PHY_REG_PHYIDR2     0x03
00047 #define LAN8742_PHY_REG_ANAR        0x04
00048 #define LAN8742_PHY_REG_ANLPAR      0x05
00049 #define LAN8742_PHY_REG_ANER        0x06
00050 #define LAN8742_PHY_REG_ANNPTR      0x07
00051 #define LAN8742_PHY_REG_ANNPRR      0x08
00052 #define LAN8742_PHY_REG_MDDACR      0x0D
00053 #define LAN8742_PHY_REG_MDDAADR     0x0E
00054 #define LAN8742_PHY_REG_ENCTR       0x10
00055 #define LAN8742_PHY_REG_MCSR        0x11
00056 #define LAN8742_PHY_REG_SMR         0x12
00057 #define LAN8742_PHY_REG_TDRPDCR     0x18
00058 #define LAN8742_PHY_REG_TDRCSR      0x19
00059 #define LAN8742_PHY_REG_SECR        0x1A
00060 #define LAN8742_PHY_REG_SCSIR       0x1B
00061 #define LAN8742_PHY_REG_CLR         0x1C
00062 #define LAN8742_PHY_REG_ISR         0x1D
00063 #define LAN8742_PHY_REG_IMR         0x1E
00064 #define LAN8742_PHY_REG_PSCSR       0x1F
00065 
00066 //BMCR register
00067 #define BMCR_RESET                  (1 << 15)
00068 #define BMCR_LOOPBACK               (1 << 14)
00069 #define BMCR_SPEED_SEL              (1 << 13)
00070 #define BMCR_AN_EN                  (1 << 12)
00071 #define BMCR_POWER_DOWN             (1 << 11)
00072 #define BMCR_ISOLATE                (1 << 10)
00073 #define BMCR_RESTART_AN             (1 << 9)
00074 #define BMCR_DUPLEX_MODE            (1 << 8)
00075 #define BMCR_COL_TEST               (1 << 7)
00076 
00077 //BMSR register
00078 #define BMSR_100BT4                 (1 << 15)
00079 #define BMSR_100BTX_FD              (1 << 14)
00080 #define BMSR_100BTX                 (1 << 13)
00081 #define BMSR_10BT_FD                (1 << 12)
00082 #define BMSR_10BT                   (1 << 11)
00083 #define BMSR_100BT2_FD              (1 << 10)
00084 #define BMSR_100BT2                 (1 << 9)
00085 #define BMSR_EXTENTED_STATUS        (1 << 8)
00086 #define BMSR_AN_COMPLETE            (1 << 5)
00087 #define BMSR_REMOTE_FAULT           (1 << 4)
00088 #define BMSR_AN_ABLE                (1 << 3)
00089 #define BMSR_LINK_STATUS            (1 << 2)
00090 #define BMSR_JABBER_DETECT          (1 << 1)
00091 #define BMSR_EXTENDED_CAP           (1 << 0)
00092 
00093 //ANAR register
00094 #define ANAR_NP                     (1 << 15)
00095 #define ANAR_RF                     (1 << 13)
00096 #define ANAR_PAUSE1                 (1 << 11)
00097 #define ANAR_PAUSE0                 (1 << 10)
00098 #define ANAR_100BTX_FD              (1 << 8)
00099 #define ANAR_100BTX                 (1 << 7)
00100 #define ANAR_10BT_FD                (1 << 6)
00101 #define ANAR_10BT                   (1 << 5)
00102 #define ANAR_SELECTOR4              (1 << 4)
00103 #define ANAR_SELECTOR3              (1 << 3)
00104 #define ANAR_SELECTOR2              (1 << 2)
00105 #define ANAR_SELECTOR1              (1 << 1)
00106 #define ANAR_SELECTOR0              (1 << 0)
00107 
00108 //ANLPAR register
00109 #define ANLPAR_NP                   (1 << 15)
00110 #define ANLPAR_ACK                  (1 << 14)
00111 #define ANLPAR_RF                   (1 << 13)
00112 #define ANLPAR_PAUSE1               (1 << 11)
00113 #define ANLPAR_PAUSE0               (1 << 10)
00114 #define ANLPAR_100BT4               (1 << 9)
00115 #define ANLPAR_100BTX_FD            (1 << 8)
00116 #define ANLPAR_100BTX               (1 << 7)
00117 #define ANLPAR_10BT_FD              (1 << 6)
00118 #define ANLPAR_10BT                 (1 << 5)
00119 #define ANLPAR_SELECTOR4            (1 << 4)
00120 #define ANLPAR_SELECTOR3            (1 << 3)
00121 #define ANLPAR_SELECTOR2            (1 << 2)
00122 #define ANLPAR_SELECTOR1            (1 << 1)
00123 #define ANLPAR_SELECTOR0            (1 << 0)
00124 
00125 //ANER register
00126 #define ANER_RX_NP_LOC_ABLE         (1 << 6)
00127 #define ANER_RX_NP_STOR_LOC         (1 << 5)
00128 #define ANER_PDF                    (1 << 4)
00129 #define ANER_LP_NP_ABLE             (1 << 3)
00130 #define ANER_NP_ABLE                (1 << 2)
00131 #define ANER_PAGE_RX                (1 << 1)
00132 #define ANER_LP_AN_ABLE             (1 << 0)
00133 
00134 //ANNPTR register
00135 #define ANNPTR_NEXT_PAGE            (1 << 15)
00136 #define ANNPTR_MSG_PAGE             (1 << 13)
00137 #define ANNPTR_ACK2                 (1 << 12)
00138 #define ANNPTR_TOGGLE               (1 << 11)
00139 #define ANNPTR_MESSAGE10            (1 << 10)
00140 #define ANNPTR_MESSAGE9             (1 << 9)
00141 #define ANNPTR_MESSAGE8             (1 << 8)
00142 #define ANNPTR_MESSAGE7             (1 << 7)
00143 #define ANNPTR_MESSAGE6             (1 << 6)
00144 #define ANNPTR_MESSAGE5             (1 << 5)
00145 #define ANNPTR_MESSAGE4             (1 << 4)
00146 #define ANNPTR_MESSAGE3             (1 << 3)
00147 #define ANNPTR_MESSAGE2             (1 << 2)
00148 #define ANNPTR_MESSAGE1             (1 << 1)
00149 #define ANNPTR_MESSAGE0             (1 << 0)
00150 
00151 //ANNPRR register
00152 #define ANNPRR_NEXT_PAGE            (1 << 15)
00153 #define ANNPRR_ACK                  (1 << 14)
00154 #define ANNPRR_MSG_PAGE             (1 << 13)
00155 #define ANNPRR_ACK2                 (1 << 12)
00156 #define ANNPRR_TOGGLE               (1 << 11)
00157 #define ANNPRR_MESSAGE10            (1 << 10)
00158 #define ANNPRR_MESSAGE9             (1 << 9)
00159 #define ANNPRR_MESSAGE8             (1 << 8)
00160 #define ANNPRR_MESSAGE7             (1 << 7)
00161 #define ANNPRR_MESSAGE6             (1 << 6)
00162 #define ANNPRR_MESSAGE5             (1 << 5)
00163 #define ANNPRR_MESSAGE4             (1 << 4)
00164 #define ANNPRR_MESSAGE3             (1 << 3)
00165 #define ANNPRR_MESSAGE2             (1 << 2)
00166 #define ANNPRR_MESSAGE1             (1 << 1)
00167 #define ANNPRR_MESSAGE0             (1 << 0)
00168 
00169 //MDDACR register
00170 #define MDDACR_MMD_FUNCTION1        (1 << 15)
00171 #define MDDACR_MMD_FUNCTION0        (1 << 14)
00172 #define MDDACR_MMD_DEVAD4           (1 << 4)
00173 #define MDDACR_MMD_DEVAD3           (1 << 3)
00174 #define MDDACR_MMD_DEVAD2           (1 << 2)
00175 #define MDDACR_MMD_DEVAD1           (1 << 1)
00176 #define MDDACR_MMD_DEVAD0           (1 << 0)
00177 
00178 //ENCTR register
00179 #define ENCTR_EDPD_TX_NLP_EN        (1 << 15)
00180 #define ENCTR_EDPD_TX_NLP_ITS1      (1 << 14)
00181 #define ENCTR_EDPD_TX_NLP_ITS0      (1 << 13)
00182 #define ENCTR_EDPD_RX_NLP_WAKE_EN   (1 << 12)
00183 #define ENCTR_EDPD_RX_NLP_MIDS1     (1 << 11)
00184 #define ENCTR_EDPD_RX_NLP_MIDS0     (1 << 10)
00185 #define ENCTR_EDPD_EXT_CROSSOVER    (1 << 1)
00186 #define ENCTR_EXT_CROSSOVER_TIME    (1 << 0)
00187 
00188 //MCSR register
00189 #define MCSR_EDPWRDOWN              (1 << 13)
00190 #define MCSR_FARLOOPBACK            (1 << 9)
00191 #define MCSR_ALTINT                 (1 << 6)
00192 #define MCSR_ENERGYON               (1 << 1)
00193 
00194 //SMR register
00195 #define SMR_MODE2                   (1 << 7)
00196 #define SMR_MODE1                   (1 << 6)
00197 #define SMR_MODE0                   (1 << 5)
00198 #define SMR_PHYAD4                  (1 << 4)
00199 #define SMR_PHYAD3                  (1 << 3)
00200 #define SMR_PHYAD2                  (1 << 2)
00201 #define SMR_PHYAD1                  (1 << 1)
00202 #define SMR_PHYAD0                  (1 << 0)
00203 
00204 //TDRPDCR register
00205 #define TDRPDCR_DELAY_IN            (1 << 15)
00206 #define TDRPDCR_LINE_BREAK_COUNTER2 (1 << 14)
00207 #define TDRPDCR_LINE_BREAK_COUNTER1 (1 << 13)
00208 #define TDRPDCR_LINE_BREAK_COUNTER0 (1 << 12)
00209 #define TDRPDCR_PATTERN_HIGH5       (1 << 11)
00210 #define TDRPDCR_PATTERN_HIGH4       (1 << 10)
00211 #define TDRPDCR_PATTERN_HIGH3       (1 << 9)
00212 #define TDRPDCR_PATTERN_HIGH2       (1 << 8)
00213 #define TDRPDCR_PATTERN_HIGH1       (1 << 7)
00214 #define TDRPDCR_PATTERN_HIGH0       (1 << 6)
00215 #define TDRPDCR_PATTERN_LOW5        (1 << 5)
00216 #define TDRPDCR_PATTERN_LOW4        (1 << 4)
00217 #define TDRPDCR_PATTERN_LOW3        (1 << 3)
00218 #define TDRPDCR_PATTERN_LOW2        (1 << 2)
00219 #define TDRPDCR_PATTERN_LOW1        (1 << 1)
00220 #define TDRPDCR_PATTERN_LOW0        (1 << 0)
00221 
00222 //TDRCSR register
00223 #define TDRCSR_EN                   (1 << 15)
00224 #define TDRCSR_AD_FILTER_EN         (1 << 14)
00225 #define TDRCSR_CH_CABLE_TYPE1       (1 << 10)
00226 #define TDRCSR_CH_CABLE_TYPE0       (1 << 9)
00227 #define TDRCSR_CH_STATUS            (1 << 8)
00228 #define TDRCSR_CH_LENGTH7           (1 << 7)
00229 #define TDRCSR_CH_LENGTH6           (1 << 6)
00230 #define TDRCSR_CH_LENGTH5           (1 << 5)
00231 #define TDRCSR_CH_LENGTH4           (1 << 4)
00232 #define TDRCSR_CH_LENGTH3           (1 << 3)
00233 #define TDRCSR_CH_LENGTH2           (1 << 2)
00234 #define TDRCSR_CH_LENGTH1           (1 << 1)
00235 #define TDRCSR_CH_LENGTH0           (1 << 0)
00236 
00237 //SCSIR register
00238 #define SCSIR_AMDIXCTRL             (1 << 15)
00239 #define SCSIR_CH_SELECT             (1 << 13)
00240 #define SCSIR_SQEOFF                (1 << 11)
00241 #define SCSIR_XPOL                  (1 << 4)
00242 
00243 //CLR register
00244 #define CLR_CBLN3                   (1 << 15)
00245 #define CLR_CBLN2                   (1 << 14)
00246 #define CLR_CBLN1                   (1 << 13)
00247 #define CLR_CBLN0                   (1 << 12)
00248 
00249 //ISR register
00250 #define ISR_WOL                     (1 << 8)
00251 #define ISR_ENERGYON                (1 << 7)
00252 #define ISR_AN_COMPLETE             (1 << 6)
00253 #define ISR_REMOTE_FAULT            (1 << 5)
00254 #define ISR_LINK_DOWN               (1 << 4)
00255 #define ISR_AN_LP_ACK               (1 << 3)
00256 #define ISR_PD_FAULT                (1 << 2)
00257 #define ISR_AN_PAGE_RECEIVED        (1 << 1)
00258 
00259 //IMR register
00260 #define IMR_WOL                     (1 << 8)
00261 #define IMR_ENERGYON                (1 << 7)
00262 #define IMR_AN_COMPLETE             (1 << 6)
00263 #define IMR_REMOTE_FAULT            (1 << 5)
00264 #define IMR_LINK_DOWN               (1 << 4)
00265 #define IMR_AN_LP_ACK               (1 << 3)
00266 #define IMR_PD_FAULT                (1 << 2)
00267 #define IMR_AN_PAGE_RECEIVED        (1 << 1)
00268 
00269 //PSCSR register
00270 #define PSCSR_AUTODONE              (1 << 12)
00271 #define PSCSR_HCDSPEED2             (1 << 4)
00272 #define PSCSR_HCDSPEED1             (1 << 3)
00273 #define PSCSR_HCDSPEED0             (1 << 2)
00274 
00275 //Speed indication
00276 #define PSCSR_HCDSPEED_MASK         (7 << 2)
00277 #define PSCSR_HCDSPEED_10BT         (1 << 2)
00278 #define PSCSR_HCDSPEED_100BTX       (2 << 2)
00279 #define PSCSR_HCDSPEED_10BT_FD      (5 << 2)
00280 #define PSCSR_HCDSPEED_100BTX_FD    (6 << 2)
00281 
00282 //LAN8742 Ethernet PHY driver
00283 extern const PhyDriver lan8742PhyDriver;
00284 
00285 //LAN8742 related functions
00286 error_t lan8742Init(NetInterface *interface);
00287 
00288 void lan8742Tick(NetInterface *interface);
00289 
00290 void lan8742EnableIrq(NetInterface *interface);
00291 void lan8742DisableIrq(NetInterface *interface);
00292 
00293 void lan8742EventHandler(NetInterface *interface);
00294 
00295 void lan8742WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00296 uint16_t lan8742ReadPhyReg(NetInterface *interface, uint8_t address);
00297 
00298 void lan8742DumpPhyReg(NetInterface *interface);
00299 
00300 #endif
00301