lan8720.h

00001 /**
00002  * @file lan8720.h
00003  * @brief LAN8720 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _LAN8720_H
00030 #define _LAN8720_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef LAN8720_PHY_ADDR
00037    #define LAN8720_PHY_ADDR 0
00038 #elif (LAN8720_PHY_ADDR < 0 || LAN8720_PHY_ADDR > 31)
00039    #error LAN8720_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //LAN8720 registers
00043 #define LAN8720_PHY_REG_BMCR        0x00
00044 #define LAN8720_PHY_REG_BMSR        0x01
00045 #define LAN8720_PHY_REG_PHYIDR1     0x02
00046 #define LAN8720_PHY_REG_PHYIDR2     0x03
00047 #define LAN8720_PHY_REG_ANAR        0x04
00048 #define LAN8720_PHY_REG_ANLPAR      0x05
00049 #define LAN8720_PHY_REG_ANER        0x06
00050 #define LAN8720_PHY_REG_SRR         0x10
00051 #define LAN8720_PHY_REG_MCSR        0x11
00052 #define LAN8720_PHY_REG_SMR         0x12
00053 #define LAN8720_PHY_REG_SECR        0x1A
00054 #define LAN8720_PHY_REG_SCSIR       0x1B
00055 #define LAN8720_PHY_REG_SITCR       0x1C
00056 #define LAN8720_PHY_REG_ISR         0x1D
00057 #define LAN8720_PHY_REG_IMR         0x1E
00058 #define LAN8720_PHY_REG_PSCSR       0x1F
00059 
00060 //BMCR register
00061 #define BMCR_RESET                  (1 << 15)
00062 #define BMCR_LOOPBACK               (1 << 14)
00063 #define BMCR_SPEED_SEL              (1 << 13)
00064 #define BMCR_AN_EN                  (1 << 12)
00065 #define BMCR_POWER_DOWN             (1 << 11)
00066 #define BMCR_ISOLATE                (1 << 10)
00067 #define BMCR_RESTART_AN             (1 << 9)
00068 #define BMCR_DUPLEX_MODE            (1 << 8)
00069 #define BMCR_COL_TEST               (1 << 7)
00070 
00071 //BMSR register
00072 #define BMSR_100BT4                 (1 << 15)
00073 #define BMSR_100BTX_FD              (1 << 14)
00074 #define BMSR_100BTX                 (1 << 13)
00075 #define BMSR_10BT_FD                (1 << 12)
00076 #define BMSR_10BT                   (1 << 11)
00077 #define BMSR_AN_COMPLETE            (1 << 5)
00078 #define BMSR_REMOTE_FAULT           (1 << 4)
00079 #define BMSR_AN_ABLE                (1 << 3)
00080 #define BMSR_LINK_STATUS            (1 << 2)
00081 #define BMSR_JABBER_DETECT          (1 << 1)
00082 #define BMSR_EXTENDED_CAP           (1 << 0)
00083 
00084 //ANAR register
00085 #define ANAR_NP                     (1 << 15)
00086 #define ANAR_RF                     (1 << 13)
00087 #define ANAR_PAUSE1                 (1 << 11)
00088 #define ANAR_PAUSE0                 (1 << 10)
00089 #define ANAR_100BT4                 (1 << 9)
00090 #define ANAR_100BTX_FD              (1 << 8)
00091 #define ANAR_100BTX                 (1 << 7)
00092 #define ANAR_10BT_FD                (1 << 6)
00093 #define ANAR_10BT                   (1 << 5)
00094 #define ANAR_SELECTOR4              (1 << 4)
00095 #define ANAR_SELECTOR3              (1 << 3)
00096 #define ANAR_SELECTOR2              (1 << 2)
00097 #define ANAR_SELECTOR1              (1 << 1)
00098 #define ANAR_SELECTOR0              (1 << 0)
00099 
00100 //ANLPAR register
00101 #define ANLPAR_NP                   (1 << 15)
00102 #define ANLPAR_ACK                  (1 << 14)
00103 #define ANLPAR_RF                   (1 << 13)
00104 #define ANLPAR_PAUSE                (1 << 10)
00105 #define ANLPAR_100BT4               (1 << 9)
00106 #define ANLPAR_100BTX_FD            (1 << 8)
00107 #define ANLPAR_100BTX               (1 << 7)
00108 #define ANLPAR_10BT_FD              (1 << 6)
00109 #define ANLPAR_10BT                 (1 << 5)
00110 #define ANLPAR_SELECTOR4            (1 << 4)
00111 #define ANLPAR_SELECTOR3            (1 << 3)
00112 #define ANLPAR_SELECTOR2            (1 << 2)
00113 #define ANLPAR_SELECTOR1            (1 << 1)
00114 #define ANLPAR_SELECTOR0            (1 << 0)
00115 
00116 //ANER register
00117 #define ANER_PDF                    (1 << 4)
00118 #define ANER_LP_NP_ABLE             (1 << 3)
00119 #define ANER_NP_ABLE                (1 << 2)
00120 #define ANER_PAGE_RX                (1 << 1)
00121 #define ANER_LP_AN_ABLE             (1 << 0)
00122 
00123 //SRR register
00124 #define SRR_SILICON_REVISON3        (1 << 9)
00125 #define SRR_SILICON_REVISON2        (1 << 8)
00126 #define SRR_SILICON_REVISON1        (1 << 7)
00127 #define SRR_SILICON_REVISON0        (1 << 6)
00128 
00129 //MCSR register
00130 #define MCSR_EDPWRDOWN              (1 << 13)
00131 #define MCSR_LOWSQEN                (1 << 11)
00132 #define MCSR_MDPREBP                (1 << 10)
00133 #define MCSR_FARLOOPBACK            (1 << 9)
00134 #define MCSR_ALTINT                 (1 << 6)
00135 #define MCSR_PHYADBP                (1 << 3)
00136 #define MCSR_FORCE_GOOD_LINK_STATUS (1 << 2)
00137 #define MCSR_ENERGYON               (1 << 1)
00138 
00139 //SMR register
00140 #define SMR_MODE2                   (1 << 7)
00141 #define SMR_MODE1                   (1 << 6)
00142 #define SMR_MODE0                   (1 << 5)
00143 #define SMR_PHYAD4                  (1 << 4)
00144 #define SMR_PHYAD3                  (1 << 3)
00145 #define SMR_PHYAD2                  (1 << 2)
00146 #define SMR_PHYAD1                  (1 << 1)
00147 #define SMR_PHYAD0                  (1 << 0)
00148 
00149 //SCSIR register
00150 #define SCSIR_AMDIXCTRL            (1 << 15)
00151 #define SCSIR_CH_SELECT            (1 << 13)
00152 #define SCSIR_SQEOFF               (1 << 11)
00153 #define SCSIR_XPOL                 (1 << 4)
00154 
00155 //ISR register
00156 #define ISR_ENERGYON                (1 << 7)
00157 #define ISR_AN_COMPLETE             (1 << 6)
00158 #define ISR_REMOTE_FAULT            (1 << 5)
00159 #define ISR_LINK_DOWN               (1 << 4)
00160 #define ISR_AN_LP_ACK               (1 << 3)
00161 #define ISR_PD_FAULT                (1 << 2)
00162 #define ISR_AN_PAGE_RECEIVED        (1 << 1)
00163 
00164 //IMR register
00165 #define IMR_ENERGYON                (1 << 7)
00166 #define IMR_AN_COMPLETE             (1 << 6)
00167 #define IMR_REMOTE_FAULT            (1 << 5)
00168 #define IMR_LINK_DOWN               (1 << 4)
00169 #define IMR_AN_LP_ACK               (1 << 3)
00170 #define IMR_PD_FAULT                (1 << 2)
00171 #define IMR_AN_PAGE_RECEIVED        (1 << 1)
00172 
00173 //PSCSR register
00174 #define PSCSR_AUTODONE              (1 << 12)
00175 #define PSCSR_GPO2                  (1 << 9)
00176 #define PSCSR_GPO1                  (1 << 8)
00177 #define PSCSR_GPO0                  (1 << 7)
00178 #define PSCSR_ENABLE_4B5B           (1 << 6)
00179 #define PSCSR_HCDSPEED2             (1 << 4)
00180 #define PSCSR_HCDSPEED1             (1 << 3)
00181 #define PSCSR_HCDSPEED0             (1 << 2)
00182 #define PSCSR_SCRAMBLE_DISABLE      (1 << 0)
00183 
00184 //Speed indication
00185 #define PSCSR_HCDSPEED_MASK         (7 << 2)
00186 #define PSCSR_HCDSPEED_10BT         (1 << 2)
00187 #define PSCSR_HCDSPEED_100BTX       (2 << 2)
00188 #define PSCSR_HCDSPEED_10BT_FD      (5 << 2)
00189 #define PSCSR_HCDSPEED_100BTX_FD    (6 << 2)
00190 
00191 //LAN8720 Ethernet PHY driver
00192 extern const PhyDriver lan8720PhyDriver;
00193 
00194 //LAN8720 related functions
00195 error_t lan8720Init(NetInterface *interface);
00196 
00197 void lan8720Tick(NetInterface *interface);
00198 
00199 void lan8720EnableIrq(NetInterface *interface);
00200 void lan8720DisableIrq(NetInterface *interface);
00201 
00202 void lan8720EventHandler(NetInterface *interface);
00203 
00204 void lan8720WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00205 uint16_t lan8720ReadPhyReg(NetInterface *interface, uint8_t address);
00206 
00207 void lan8720DumpPhyReg(NetInterface *interface);
00208 
00209 #endif
00210