Sergey Pastor
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ksz8851.h
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00001 /** 00002 * @file ksz8851.h 00003 * @brief KSZ8851 Ethernet controller 00004 * 00005 * @section License 00006 * 00007 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved. 00008 * 00009 * This file is part of CycloneTCP Open. 00010 * 00011 * This program is free software; you can redistribute it and/or 00012 * modify it under the terms of the GNU General Public License 00013 * as published by the Free Software Foundation; either version 2 00014 * of the License, or (at your option) any later version. 00015 * 00016 * This program is distributed in the hope that it will be useful, 00017 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00019 * GNU General Public License for more details. 00020 * 00021 * You should have received a copy of the GNU General Public License 00022 * along with this program; if not, write to the Free Software Foundation, 00023 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00024 * 00025 * @author Oryx Embedded SARL (www.oryx-embedded.com) 00026 * @version 1.7.6 00027 **/ 00028 00029 #ifndef _KSZ8851_H 00030 #define _KSZ8851_H 00031 00032 //SPI interface support 00033 #ifndef KSZ8851_SPI_SUPPORT 00034 #define KSZ8851_SPI_SUPPORT ENABLED 00035 #elif (KSZ8851_SPI_SUPPORT != ENABLED && KSZ8851_SPI_SUPPORT != DISABLED) 00036 #error KSZ8851_SPI_SUPPORT parameter is not valid 00037 #endif 00038 00039 //KSZ8851 data register 00040 #ifndef KSZ8851_DATA_REG 00041 #define KSZ8851_DATA_REG *((volatile uint16_t *) 0x60000000) 00042 #endif 00043 00044 //KSZ8851 command register 00045 #ifndef KSZ8851_CMD_REG 00046 #define KSZ8851_CMD_REG *((volatile uint16_t *) 0x60000004) 00047 #endif 00048 00049 //Device ID 00050 #define KSZ8851_REV_A2_ID 0x8870 00051 #define KSZ8851_REV_A3_ID 0x8872 00052 00053 //SPI command set 00054 #define KSZ8851_CMD_RD_REG 0x00 00055 #define KSZ8851_CMD_WR_REG 0x40 00056 #define KSZ8851_CMD_RD_FIFO 0x80 00057 #define KSZ8851_CMD_WR_FIFO 0xC0 00058 00059 //Byte enable bits 00060 #if (KSZ8851_SPI_SUPPORT == ENABLED) 00061 #define KSZ8851_CMD_B0 0x04 00062 #define KSZ8851_CMD_B1 0x08 00063 #define KSZ8851_CMD_B2 0x10 00064 #define KSZ8851_CMD_B3 0x20 00065 #else 00066 #define KSZ8851_CMD_B0 0x1000 00067 #define KSZ8851_CMD_B1 0x2000 00068 #define KSZ8851_CMD_B2 0x4000 00069 #define KSZ8851_CMD_B3 0x8000 00070 #endif 00071 00072 //KSZ8851 registers 00073 #define KSZ8851_REG_CCR 0x08 00074 #define KSZ8851_REG_MARL 0x10 00075 #define KSZ8851_REG_MARM 0x12 00076 #define KSZ8851_REG_MARH 0x14 00077 #define KSZ8851_REG_OBCR 0x20 00078 #define KSZ8851_REG_EEPCR 0x22 00079 #define KSZ8851_REG_MBIR 0x24 00080 #define KSZ8851_REG_GRR 0x26 00081 #define KSZ8851_REG_WFCR 0x2A 00082 #define KSZ8851_REG_WF0CRC0 0x30 00083 #define KSZ8851_REG_WF0CRC1 0x32 00084 #define KSZ8851_REG_WF0BM0 0x34 00085 #define KSZ8851_REG_WF0BM1 0x36 00086 #define KSZ8851_REG_WF0BM2 0x38 00087 #define KSZ8851_REG_WF0BM3 0x3A 00088 #define KSZ8851_REG_WF1CRC0 0x40 00089 #define KSZ8851_REG_WF1CRC1 0x42 00090 #define KSZ8851_REG_WF1BM0 0x44 00091 #define KSZ8851_REG_WF1BM1 0x46 00092 #define KSZ8851_REG_WF1BM2 0x48 00093 #define KSZ8851_REG_WF1BM3 0x4A 00094 #define KSZ8851_REG_WF2CRC0 0x50 00095 #define KSZ8851_REG_WF2CRC1 0x52 00096 #define KSZ8851_REG_WF2BM0 0x54 00097 #define KSZ8851_REG_WF2BM1 0x56 00098 #define KSZ8851_REG_WF2BM2 0x58 00099 #define KSZ8851_REG_WF2BM3 0x5A 00100 #define KSZ8851_REG_WF3CRC0 0x60 00101 #define KSZ8851_REG_WF3CRC1 0x62 00102 #define KSZ8851_REG_WF3BM0 0x64 00103 #define KSZ8851_REG_WF3BM1 0x66 00104 #define KSZ8851_REG_WF3BM2 0x68 00105 #define KSZ8851_REG_WF3BM3 0x6A 00106 #define KSZ8851_REG_TXCR 0x70 00107 #define KSZ8851_REG_TXSR 0x72 00108 #define KSZ8851_REG_RXCR1 0x74 00109 #define KSZ8851_REG_RXCR2 0x76 00110 #define KSZ8851_REG_TXMIR 0x78 00111 #define KSZ8851_REG_RXFHSR 0x7C 00112 #define KSZ8851_REG_RXFHBCR 0x7E 00113 #define KSZ8851_REG_TXQCR 0x80 00114 #define KSZ8851_REG_RXQCR 0x82 00115 #define KSZ8851_REG_TXFDPR 0x84 00116 #define KSZ8851_REG_RXFDPR 0x86 00117 #define KSZ8851_REG_RXDTTR 0x8C 00118 #define KSZ8851_REG_RXDBCTR 0x8E 00119 #define KSZ8851_REG_IER 0x90 00120 #define KSZ8851_REG_ISR 0x92 00121 #define KSZ8851_REG_RXFCTR 0x9C 00122 #define KSZ8851_REG_TXNTFSR 0x9E 00123 #define KSZ8851_REG_MAHTR0 0xA0 00124 #define KSZ8851_REG_MAHTR1 0xA2 00125 #define KSZ8851_REG_MAHTR2 0xA4 00126 #define KSZ8851_REG_MAHTR3 0xA6 00127 #define KSZ8851_REG_FCLWR 0xB0 00128 #define KSZ8851_REG_FCHWR 0xB2 00129 #define KSZ8851_REG_FCOWR 0xB4 00130 #define KSZ8851_REG_CIDER 0xC0 00131 #define KSZ8851_REG_CGCR 0xC6 00132 #define KSZ8851_REG_IACR 0xC8 00133 #define KSZ8851_REG_IADLR 0xD0 00134 #define KSZ8851_REG_IADHR 0xD2 00135 #define KSZ8851_REG_PMECR 0xD4 00136 #define KSZ8851_REG_GSWUTR 0xD6 00137 #define KSZ8851_REG_PHYRR 0xD8 00138 #define KSZ8851_REG_P1MBCR 0xE4 00139 #define KSZ8851_REG_P1MBSR 0xE6 00140 #define KSZ8851_REG_PHY1ILR 0xE8 00141 #define KSZ8851_REG_PHY1IHR 0xEA 00142 #define KSZ8851_REG_P1ANAR 0xEC 00143 #define KSZ8851_REG_P1ANLPR 0xEE 00144 #define KSZ8851_REG_P1SCLMD 0xF4 00145 #define KSZ8851_REG_P1CR 0xF6 00146 #define KSZ8851_REG_P1SR 0xF8 00147 00148 //CCR register 00149 #define CCR_BUS_ENDIAN_MODE 0x0400 00150 #define CCR_EEPROM_PRESENCE 0x0200 00151 #define CCR_SPI_MODE 0x0100 00152 #define CCR_8_BIT_DATA_BUS 0x0080 00153 #define CCR_16_BIT_DATA_BUS 0x0040 00154 #define CCR_32_BIT_DATA_BUS 0x0020 00155 #define CCR_BUS_SHARED_MODE 0x0010 00156 #define CCR_128_PIN_PACKAGE 0x0008 00157 #define CCR_48_PIN_PACKAGE 0x0002 00158 #define CCR_32_PIN_PACKAGE 0x0001 00159 00160 //OBCR register 00161 #define OBCR_OUT_DRIVE_STRENGTH 0x0040 00162 #define OBCR_SPI_SO_DELAY2 0x0020 00163 #define OBCR_SPI_SO_DELAY1 0x0010 00164 #define OBCR_SPI_SO_DELAY0 0x0008 00165 #define OBCR_BUS_CLOCK_SEL 0x0004 00166 #define OBCR_BUS_CLOCK_DIV1 0x0002 00167 #define OBCR_BUS_CLOCK_DIV0 0x0001 00168 00169 //EEPCR register 00170 #define EEPCR_EESA 0x0010 00171 #define EEPCR_EESB 0x0008 00172 #define EEPCR_EECB2 0x0004 00173 #define EEPCR_EECB1 0x0002 00174 #define EEPCR_EECB0 0x0001 00175 00176 //MBIR register 00177 #define MBIR_TXMBF 0x1000 00178 #define MBIR_TXMBFA 0x0800 00179 #define MBIR_TXMBFC2 0x0400 00180 #define MBIR_TXMBFC1 0x0200 00181 #define MBIR_TXMBFC0 0x0100 00182 #define MBIR_RXMBF 0x0010 00183 #define MBIR_RXMBFA 0x0008 00184 #define MBIR_RXMBFC2 0x0004 00185 #define MBIR_RXMBFC1 0x0002 00186 #define MBIR_RXMBFC0 0x0001 00187 00188 //GRR register 00189 #define GRR_QMU_MODULE_SOFT_RST 0x0002 00190 #define GRR_GLOBAL_SOFT_RST 0x0001 00191 00192 //WFCR register 00193 #define WFCR_MPRXE 0x0080 00194 #define WFCR_WF3E 0x0008 00195 #define WFCR_WF2E 0x0004 00196 #define WFCR_WF1E 0x0002 00197 #define WFCR_WF0E 0x0001 00198 00199 //TXCR register 00200 #define TXCR_TCGICMP 0x0100 00201 #define TXCR_TCGUDP 0x0080 00202 #define TXCR_TCGTCP 0x0040 00203 #define TXCR_TCGIP 0x0020 00204 #define TXCR_FTXQ 0x0010 00205 #define TXCR_TXFCE 0x0008 00206 #define TXCR_TXPE 0x0004 00207 #define TXCR_TXCE 0x0002 00208 #define TXCR_TXE 0x0001 00209 00210 //TXSR register 00211 #define TXSR_TXLC 0x2000 00212 #define TXSR_TXMC 0x1000 00213 #define TXSR_TXFID5 0x0020 00214 #define TXSR_TXFID4 0x0010 00215 #define TXSR_TXFID3 0x0008 00216 #define TXSR_TXFID2 0x0004 00217 #define TXSR_TXFID1 0x0002 00218 #define TXSR_TXFID0 0x0001 00219 00220 //RXCR1 register 00221 #define RXCR1_FRXQ 0x8000 00222 #define RXCR1_RXUDPFCC 0x4000 00223 #define RXCR1_RXTCPFCC 0x2000 00224 #define RXCR1_RXIPFCC 0x1000 00225 #define RXCR1_RXPAFMA 0x0800 00226 #define RXCR1_RXFCE 0x0400 00227 #define RXCR1_RXEFE 0x0200 00228 #define RXCR1_RXMAFMA 0x0100 00229 #define RXCR1_RXBE 0x0080 00230 #define RXCR1_RXME 0x0040 00231 #define RXCR1_RXUE 0x0020 00232 #define RXCR1_RXAE 0x0010 00233 #define RXCR1_RXINVF 0x0002 00234 #define RXCR1_RXE 0x0001 00235 00236 //RXCR2 register 00237 #define RXCR2_SRDBL2 0x0080 00238 #define RXCR2_SRDBL1 0x0040 00239 #define RXCR2_SRDBL0 0x0020 00240 #define RXCR2_IUFFP 0x0010 00241 #define RXCR2_RXIUFCEZ 0x0008 00242 #define RXCR2_UDPLFE 0x0004 00243 #define RXCR2_RXICMPFCC 0x0002 00244 #define RXCR2_RXSAF 0x0001 00245 00246 //TXMIR register 00247 #define TXMIR_TXMA_MASK 0x1FFF 00248 00249 //RXFHSR register 00250 #define RXFHSR_RXFV 0x8000 00251 #define RXFHSR_RXICMPFCS 0x2000 00252 #define RXFHSR_RXIPFCS 0x1000 00253 #define RXFHSR_RXTCPFCS 0x0800 00254 #define RXFHSR_RXUDPFCS 0x0400 00255 #define RXFHSR_RXBF 0x0080 00256 #define RXFHSR_RXMF 0x0040 00257 #define RXFHSR_RXUF 0x0020 00258 #define RXFHSR_RXMR 0x0010 00259 #define RXFHSR_RXFT 0x0008 00260 #define RXFHSR_RXFTL 0x0004 00261 #define RXFHSR_RXRF 0x0002 00262 #define RXFHSR_RXCE 0x0001 00263 00264 //RXFHBCR register 00265 #define RXFHBCR_RXBC_MASK 0x0FFF 00266 00267 //TXQCR register 00268 #define TXQCR_AETFE 0x0004 00269 #define TXQCR_TXQMAM 0x0002 00270 #define TXQCR_METFE 0x0001 00271 00272 //RXQCR register 00273 #define RXQCR_RXDTTS 0x1000 00274 #define RXQCR_RXDBCTS 0x0800 00275 #define RXQCR_RXFCTS 0x0400 00276 #define RXQCR_RXIPHTOE 0x0200 00277 #define RXQCR_RXDTTE 0x0080 00278 #define RXQCR_RXDBCTE 0x0040 00279 #define RXQCR_RXFCTE 0x0020 00280 #define RXQCR_ADRFE 0x0010 00281 #define RXQCR_SDA 0x0008 00282 #define RXQCR_RRXEF 0x0001 00283 00284 //TXFDPR register 00285 #define TXFDPR_TXFPAI 0x4000 00286 00287 //RXFDPR register 00288 #define RXFDPR_RXFPAI 0x4000 00289 00290 //IER register 00291 #define IER_LCIE 0x8000 00292 #define IER_TXIE 0x4000 00293 #define IER_RXIE 0x2000 00294 #define IER_RXOIE 0x0800 00295 #define IER_TXPSIE 0x0200 00296 #define IER_RXPSIE 0x0100 00297 #define IER_TXSAIE 0x0040 00298 #define IER_RXWFDIE 0x0020 00299 #define IER_RXMPDIE 0x0010 00300 #define IER_LDIE 0x0008 00301 #define IER_EDIE 0x0004 00302 #define IER_SPIBEIE 0x0002 00303 #define IER_DEDIE 0x0001 00304 00305 //ISR register 00306 #define ISR_LCIS 0x8000 00307 #define ISR_TXIS 0x4000 00308 #define ISR_RXIS 0x2000 00309 #define ISR_RXOIS 0x0800 00310 #define ISR_TXPSIS 0x0200 00311 #define ISR_RXPSIS 0x0100 00312 #define ISR_TXSAIS 0x0040 00313 #define ISR_RXWFDIS 0x0020 00314 #define ISR_RXMPDIS 0x0010 00315 #define ISR_LDIS 0x0008 00316 #define ISR_EDIS 0x0004 00317 #define ISR_SPIBEIS 0x0002 00318 00319 //CGCR register 00320 #define CGCR_LEDSEL0 0x0200 00321 00322 //IACR register 00323 #define IACR_READ_ENABLE 0x1000 00324 #define IACR_TABLE_SELECT1 0x0800 00325 #define IACR_TABLE_SELECT0 0x0400 00326 00327 //PMECR register 00328 #define PMECR_PME_DELAY_EN 0x4000 00329 #define PMECR_PME_POLARITY 0x1000 00330 #define PMECR_PME_WUP_FRAME_EN 0x0800 00331 #define PMECR_PME_MAGIC_EN 0x0400 00332 #define PMECR_PME_LINK_UP_EN 0x0200 00333 #define PMECR_PME_ENERGY_EN 0x0100 00334 #define PMECR_AUTO_WUP_EN 0x0080 00335 #define PMECR_WUP_NORMAL_OP_MODE 0x0040 00336 #define PMECR_WUP_FROM_WUP_FRAME 0x0020 00337 #define PMECR_WUP_FROM_MAGIC 0x0010 00338 #define PMECR_WUP_FROM_LINK_UP 0x0008 00339 #define PMECR_WUP_FROM_ENERGY 0x0004 00340 #define PMECR_PWR_MODE1 0x0002 00341 #define PMECR_PWR_MODE0 0x0001 00342 00343 //PHYRR register 00344 #define PHYRR_PHY_RESET 0x0001 00345 00346 //P1MBCR register 00347 #define P1MBCR_LOCAL_LOOPBACK 0x4000 00348 #define P1MBCR_FORCE_100 0x2000 00349 #define P1MBCR_AN_ENABLE 0x1000 00350 #define P1MBCR_RESTART_AN 0x0200 00351 #define P1MBCR_FORCE_FULL_DUPLEX 0x0100 00352 #define P1MBCR_HP_MDIX 0x0020 00353 #define P1MBCR_FORCE_MDIX 0x0010 00354 #define P1MBCR_DISABLE_MDIX 0x0008 00355 #define P1MBCR_DISABLE_TRANSMIT 0x0002 00356 #define P1MBCR_DISABLE_LED 0x0001 00357 00358 //P1MBSR register 00359 #define P1MBSR_T4_CAPABLE 0x8000 00360 #define P1MBSR_100_FD_CAPABLE 0x4000 00361 #define P1MBSR_100_CAPABLE 0x2000 00362 #define P1MBSR_10_FD_CAPABLE 0x1000 00363 #define P1MBSR_10_CAPABLE 0x0800 00364 #define P1MBSR_PREAMBLE_SUPPR 0x0040 00365 #define P1MBSR_AN_COMPLETE 0x0020 00366 #define P1MBSR_AN_CAPABLE 0x0008 00367 #define P1MBSR_LINK_STATUS 0x0004 00368 #define P1MBSR_JABBER_TEST 0x0002 00369 #define P1MBSR_EXTENDED_CAPABLE 0x0001 00370 00371 //P1ANAR register 00372 #define P1ANAR_NEXT_PAGE 0x8000 00373 #define P1ANAR_REMOTE_FAULT 0x2000 00374 #define P1ANAR_ADV_PAUSE 0x0400 00375 #define P1ANAR_ADV_100_FD 0x0100 00376 #define P1ANAR_ADV_100 0x0080 00377 #define P1ANAR_ADV_10_FD 0x0040 00378 #define P1ANAR_ADV_10 0x0020 00379 #define P1ANAR_SELECTOR_FIELD4 0x0010 00380 #define P1ANAR_SELECTOR_FIELD3 0x0008 00381 #define P1ANAR_SELECTOR_FIELD2 0x0004 00382 #define P1ANAR_SELECTOR_FIELD1 0x0002 00383 #define P1ANAR_SELECTOR_FIELD0 0x0001 00384 00385 //P1ANLPR register 00386 #define P1ANLPR_NEXT_PAGE 0x8000 00387 #define P1ANLPR_LP_ACK 0x4000 00388 #define P1ANLPR_REMOTE_FAULT 0x2000 00389 #define P1ANLPR_ADV_PAUSE 0x0400 00390 #define P1ANLPR_ADV_100_FD 0x0100 00391 #define P1ANLPR_ADV_100 0x0080 00392 #define P1ANLPR_ADV_10_FD 0x0040 00393 #define P1ANLPR_ADV_10 0x0020 00394 00395 //P1SCLMD register 00396 #define P1SCLMD_VCT_RESULT1 0x4000 00397 #define P1SCLMD_VCT_RESULT0 0x2000 00398 #define P1SCLMD_VCT_EN 0x1000 00399 #define P1SCLMD_FORCE_LNK 0x0800 00400 #define P1SCLMD_REMOTE_LOOPBACK 0x0200 00401 00402 //P1CR register 00403 #define P1CR_LED_OFF 0x8000 00404 #define P1CR_TX_DISABLE 0x4000 00405 #define P1CR_RESTART_AN 0x2000 00406 #define P1CR_DISABLE_AUTO_MDIX 0x0400 00407 #define P1CR_FORCE_MDIX 0x0200 00408 #define P1CR_AN_ENABLE 0x0080 00409 #define P1CR_FORCE_SPEED 0x0040 00410 #define P1CR_FORCE_DUPLEX 0x0020 00411 #define P1CR_ADV_PAUSE 0x0010 00412 #define P1CR_ADV_100_FD 0x0008 00413 #define P1CR_ADV_100 0x0004 00414 #define P1CR_ADV_10_FD 0x0002 00415 #define P1CR_ADV_10 0x0001 00416 00417 //P1SR register 00418 #define P1SR_HP_MDIX 0x8000 00419 #define P1SR_REVERSED_POLARITY 0x2000 00420 #define P1SR_OPERATION_SPEED 0x0400 00421 #define P1SR_OPERATION_DUPLEX 0x0200 00422 #define P1SR_MDIX_STATUS 0x0080 00423 #define P1SR_AN_DONE 0x0040 00424 #define P1SR_LINK_GOOD 0x0020 00425 #define P1SR_PARTNER_ADV_PAUSE 0x0010 00426 #define P1SR_PARTNER_ADV_100_FD 0x0008 00427 #define P1SR_PARTNER_ADV_100 0x0004 00428 #define P1SR_PARTNER_ADV_10_FD 0x0002 00429 #define P1SR_PARTNER_ADV_10 0x0001 00430 00431 //Transmit control word 00432 #define TX_CTRL_TXIC 0x8000 00433 #define TX_CTRL_TXFID 0x003F 00434 00435 00436 /** 00437 * @brief TX packet header 00438 **/ 00439 00440 typedef __start_packed struct 00441 { 00442 uint16_t controlWord; 00443 uint16_t byteCount; 00444 } __end_packed Ksz8851TxHeader; 00445 00446 00447 /** 00448 * @brief RX packet header 00449 **/ 00450 00451 typedef __start_packed struct 00452 { 00453 uint16_t statusWord; 00454 uint16_t byteCount; 00455 } __end_packed Ksz8851RxHeader; 00456 00457 00458 /** 00459 * @brief KSZ8851 driver context 00460 **/ 00461 00462 typedef struct 00463 { 00464 uint_t frameId; ///<Identify a frame and its associated status 00465 uint8_t *txBuffer; ///<Transmit buffer 00466 uint8_t *rxBuffer; ///<Receive buffer 00467 } Ksz8851Context; 00468 00469 00470 //KSZ8851 driver 00471 extern const NicDriver ksz8851Driver; 00472 00473 //KSZ8851 related functions 00474 error_t ksz8851Init(NetInterface *interface); 00475 00476 void ksz8851Tick(NetInterface *interface); 00477 00478 void ksz8851EnableIrq(NetInterface *interface); 00479 void ksz8851DisableIrq(NetInterface *interface); 00480 bool_t ksz8851IrqHandler(NetInterface *interface); 00481 void ksz8851EventHandler(NetInterface *interface); 00482 00483 error_t ksz8851SendPacket(NetInterface *interface, 00484 const NetBuffer *buffer, size_t offset); 00485 00486 error_t ksz8851ReceivePacket(NetInterface *interface); 00487 00488 error_t ksz8851SetMulticastFilter(NetInterface *interface); 00489 00490 void ksz8851WriteReg(NetInterface *interface, uint8_t address, uint16_t data); 00491 uint16_t ksz8851ReadReg(NetInterface *interface, uint8_t address); 00492 00493 void ksz8851WriteFifo(NetInterface *interface, const uint8_t *data, size_t length); 00494 void ksz8851ReadFifo(NetInterface *interface, uint8_t *data, size_t length); 00495 00496 void ksz8851SetBit(NetInterface *interface, uint8_t address, uint16_t mask); 00497 void ksz8851ClearBit(NetInterface *interface, uint8_t address, uint16_t mask); 00498 00499 uint32_t ksz8851CalcCrc(const void *data, size_t length); 00500 00501 void ksz8851DumpReg(NetInterface *interface); 00502 00503 #endif 00504
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