ksz8091.h

00001 /**
00002  * @file ksz8091.h
00003  * @brief KSZ8091 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _KSZ8091_H
00030 #define _KSZ8091_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef KSZ8091_PHY_ADDR
00037    #define KSZ8091_PHY_ADDR 7
00038 #elif (KSZ8091_PHY_ADDR < 0 || KSZ8091_PHY_ADDR > 31)
00039    #error KSZ8091_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //KSZ8091 registers
00043 #define KSZ8091_PHY_REG_BMCR        0x00
00044 #define KSZ8091_PHY_REG_BMSR        0x01
00045 #define KSZ8091_PHY_REG_PHYIDR1     0x02
00046 #define KSZ8091_PHY_REG_PHYIDR2     0x03
00047 #define KSZ8091_PHY_REG_ANAR        0x04
00048 #define KSZ8091_PHY_REG_ANLPAR      0x05
00049 #define KSZ8091_PHY_REG_ANER        0x06
00050 #define KSZ8091_PHY_REG_ANNPTR      0x07
00051 #define KSZ8091_PHY_REG_LPNPAR      0x08
00052 #define KSZ8091_PHY_REG_MMDCON      0x0D
00053 #define KSZ8091_PHY_REG_MMDDATA     0x0E
00054 #define KSZ8091_PHY_REG_DRC         0x10
00055 #define KSZ8091_PHY_REG_AFECON1     0x11
00056 #define KSZ8091_PHY_REG_AFECON4     0x13
00057 #define KSZ8091_PHY_REG_RXERCTR     0x15
00058 #define KSZ8091_PHY_REG_OMSO        0x16
00059 #define KSZ8091_PHY_REG_OMSS        0x17
00060 #define KSZ8091_PHY_REG_EXCON       0x18
00061 #define KSZ8091_PHY_REG_ICSR        0x1B
00062 #define KSZ8091_PHY_REG_LINKMDCS    0x1D
00063 #define KSZ8091_PHY_REG_PHYCON1     0x1E
00064 #define KSZ8091_PHY_REG_PHYCON2     0x1F
00065 
00066 //BMCR register
00067 #define BMCR_RESET                  (1 << 15)
00068 #define BMCR_LOOPBACK               (1 << 14)
00069 #define BMCR_SPEED_SEL              (1 << 13)
00070 #define BMCR_AN_EN                  (1 << 12)
00071 #define BMCR_POWER_DOWN             (1 << 11)
00072 #define BMCR_ISOLATE                (1 << 10)
00073 #define BMCR_RESTART_AN             (1 << 9)
00074 #define BMCR_DUPLEX_MODE            (1 << 8)
00075 #define BMCR_COL_TEST               (1 << 7)
00076 
00077 //BMSR register
00078 #define BMSR_100BT4                 (1 << 15)
00079 #define BMSR_100BTX_FD              (1 << 14)
00080 #define BMSR_100BTX                 (1 << 13)
00081 #define BMSR_10BT_FD                (1 << 12)
00082 #define BMSR_10BT                   (1 << 11)
00083 #define BMSR_NO_PREAMBLE            (1 << 6)
00084 #define BMSR_AN_COMPLETE            (1 << 5)
00085 #define BMSR_REMOTE_FAULT           (1 << 4)
00086 #define BMSR_AN_ABLE                (1 << 3)
00087 #define BMSR_LINK_STATUS            (1 << 2)
00088 #define BMSR_JABBER_DETECT          (1 << 1)
00089 #define BMSR_EXTENDED_CAP           (1 << 0)
00090 
00091 //ANAR register
00092 #define ANAR_NEXT_PAGE              (1 << 15)
00093 #define ANAR_REMOTE_FAULT           (1 << 13)
00094 #define ANAR_PAUSE1                 (1 << 11)
00095 #define ANAR_PAUSE0                 (1 << 10)
00096 #define ANAR_100BT4                 (1 << 9)
00097 #define ANAR_100BTX_FD              (1 << 8)
00098 #define ANAR_100BTX                 (1 << 7)
00099 #define ANAR_10BT_FD                (1 << 6)
00100 #define ANAR_10BT                   (1 << 5)
00101 #define ANAR_SELECTOR4              (1 << 4)
00102 #define ANAR_SELECTOR3              (1 << 3)
00103 #define ANAR_SELECTOR2              (1 << 2)
00104 #define ANAR_SELECTOR1              (1 << 1)
00105 #define ANAR_SELECTOR0              (1 << 0)
00106 
00107 //ANLPAR register
00108 #define ANLPAR_NEXT_PAGE            (1 << 15)
00109 #define ANLPAR_LP_ACK               (1 << 14)
00110 #define ANLPAR_REMOTE_FAULT         (1 << 13)
00111 #define ANLPAR_PAUSE1               (1 << 11)
00112 #define ANLPAR_PAUSE0               (1 << 10)
00113 #define ANLPAR_100BT4               (1 << 9)
00114 #define ANLPAR_100BTX_FD            (1 << 8)
00115 #define ANLPAR_100BTX               (1 << 7)
00116 #define ANLPAR_10BT_FD              (1 << 6)
00117 #define ANLPAR_10BT                 (1 << 5)
00118 #define ANLPAR_SELECTOR4            (1 << 4)
00119 #define ANLPAR_SELECTOR3            (1 << 3)
00120 #define ANLPAR_SELECTOR2            (1 << 2)
00121 #define ANLPAR_SELECTOR1            (1 << 1)
00122 #define ANLPAR_SELECTOR0            (1 << 0)
00123 
00124 //ANER register
00125 #define ANER_PAR_DET_FAULT          (1 << 4)
00126 #define ANER_LP_NEXT_PAGE_ABLE      (1 << 3)
00127 #define ANER_NEXT_PAGE_ABLE         (1 << 2)
00128 #define ANER_PAGE_RECEIVED          (1 << 1)
00129 #define ANER_LP_AN_ABLE             (1 << 0)
00130 
00131 //ANNPTR register
00132 #define ANNPTR_NEXT_PAGE            (1 << 15)
00133 #define ANNPTR_MSG_PAGE             (1 << 13)
00134 #define ANNPTR_ACK2                 (1 << 12)
00135 #define ANNPTR_TOGGLE               (1 << 11)
00136 #define ANNPTR_MESSAGE10            (1 << 10)
00137 #define ANNPTR_MESSAGE9             (1 << 9)
00138 #define ANNPTR_MESSAGE8             (1 << 8)
00139 #define ANNPTR_MESSAGE7             (1 << 7)
00140 #define ANNPTR_MESSAGE6             (1 << 6)
00141 #define ANNPTR_MESSAGE5             (1 << 5)
00142 #define ANNPTR_MESSAGE4             (1 << 4)
00143 #define ANNPTR_MESSAGE3             (1 << 3)
00144 #define ANNPTR_MESSAGE2             (1 << 2)
00145 #define ANNPTR_MESSAGE1             (1 << 1)
00146 #define ANNPTR_MESSAGE0             (1 << 0)
00147 
00148 //LPNPAR register
00149 #define LPNPAR_NEXT_PAGE            (1 << 15)
00150 #define LPNPAR_ACK                  (1 << 14)
00151 #define LPNPAR_MSG_PAGE             (1 << 13)
00152 #define LPNPAR_ACK2                 (1 << 12)
00153 #define LPNPAR_TOGGLE               (1 << 11)
00154 #define LPNPAR_MESSAGE10            (1 << 10)
00155 #define LPNPAR_MESSAGE9             (1 << 9)
00156 #define LPNPAR_MESSAGE8             (1 << 8)
00157 #define LPNPAR_MESSAGE7             (1 << 7)
00158 #define LPNPAR_MESSAGE6             (1 << 6)
00159 #define LPNPAR_MESSAGE5             (1 << 5)
00160 #define LPNPAR_MESSAGE4             (1 << 4)
00161 #define LPNPAR_MESSAGE3             (1 << 3)
00162 #define LPNPAR_MESSAGE2             (1 << 2)
00163 #define LPNPAR_MESSAGE1             (1 << 1)
00164 #define LPNPAR_MESSAGE0             (1 << 0)
00165 
00166 //MMDCON register
00167 #define MMDCON_OP_MODE1             (1 << 15)
00168 #define MMDCON_OP_MODE0             (1 << 14)
00169 #define MMDCON_DEVICE_ADDR4         (1 << 4)
00170 #define MMDCON_DEVICE_ADDR3         (1 << 3)
00171 #define MMDCON_DEVICE_ADDR2         (1 << 2)
00172 #define MMDCON_DEVICE_ADDR1         (1 << 1)
00173 #define MMDCON_DEVICE_ADDR0         (1 << 0)
00174 
00175 //DRC register
00176 #define DRC_PLL_OFF                 (1 << 4)
00177 
00178 //AFECON1 register
00179 #define AFECON1_SLOW_OSC_MODE_EN    (1 << 5)
00180 
00181 //AFECON4 register
00182 #define AFECON4_10BT_MODE           (1 << 4)
00183 
00184 //OMSO register
00185 #define OMSO_PME_ENABLE             (1 << 15)
00186 #define OMSO_BCAST_OFF_OVERRIDE     (1 << 9)
00187 #define OMSO_RMII_BTB_OVERRIDE      (1 << 6)
00188 #define OMSO_NAND_TREE_OVERRIDE     (1 << 5)
00189 #define OMSO_RMII_OVERRIDE          (1 << 1)
00190 
00191 //OMSS register
00192 #define OMSS_PHYAD2                 (1 << 15)
00193 #define OMSS_PHYAD1                 (1 << 14)
00194 #define OMSS_PHYAD0                 (1 << 13)
00195 #define OMSS_RMII_STATUS            (1 << 1)
00196 
00197 //EXCON register
00198 #define EXCON_EDPD_DIS              (1 << 11)
00199 
00200 //ICSR register
00201 #define ICSR_JABBER_IE              (1 << 15)
00202 #define ICSR_RECEIVE_ERROR_IE       (1 << 14)
00203 #define ICSR_PAGE_RECEIVED_IE       (1 << 13)
00204 #define ICSR_PAR_DET_FAULT_IE       (1 << 12)
00205 #define ICSR_LP_ACK_IE              (1 << 11)
00206 #define ICSR_LINK_DOWN_IE           (1 << 10)
00207 #define ICSR_REMOTE_FAULT_IE        (1 << 9)
00208 #define ICSR_LINK_UP_IE             (1 << 8)
00209 #define ICSR_JABBER_IF              (1 << 7)
00210 #define ICSR_RECEIVE_ERROR_IF       (1 << 6)
00211 #define ICSR_PAGE_RECEIVED_IF       (1 << 5)
00212 #define ICSR_PAR_DET_FAULT_IF       (1 << 4)
00213 #define ICSR_LP_ACK_IF              (1 << 3)
00214 #define ICSR_LINK_DOWN_IF           (1 << 2)
00215 #define ICSR_REMOTE_FAULT_IF        (1 << 1)
00216 #define ICSR_LINK_UP_IF             (1 << 0)
00217 
00218 //LINKMDCS register
00219 #define LINKMDCS_CABLE_DIAG_EN      (1 << 15)
00220 #define LINKMDCS_CABLE_DIAG_RES1    (1 << 14)
00221 #define LINKMDCS_CABLE_DIAG_RES0    (1 << 13)
00222 #define LINKMDCS_SHORT_CABLE        (1 << 12)
00223 #define LINKMDCS_CABLE_FAULT_CNT8   (1 << 8)
00224 #define LINKMDCS_CABLE_FAULT_CNT7   (1 << 7)
00225 #define LINKMDCS_CABLE_FAULT_CNT6   (1 << 6)
00226 #define LINKMDCS_CABLE_FAULT_CNT5   (1 << 5)
00227 #define LINKMDCS_CABLE_FAULT_CNT4   (1 << 4)
00228 #define LINKMDCS_CABLE_FAULT_CNT3   (1 << 3)
00229 #define LINKMDCS_CABLE_FAULT_CNT2   (1 << 2)
00230 #define LINKMDCS_CABLE_FAULT_CNT1   (1 << 1)
00231 #define LINKMDCS_CABLE_FAULT_CNT0   (1 << 0)
00232 
00233 //PHYCON1 register
00234 #define PHYCON1_PAUSE_EN            (1 << 9)
00235 #define PHYCON1_LINK_STATUS         (1 << 8)
00236 #define PHYCON1_POL_STATUS          (1 << 7)
00237 #define PHYCON1_MDIX_STATE          (1 << 5)
00238 #define PHYCON1_ENERGY_DETECT       (1 << 4)
00239 #define PHYCON1_ISOLATE             (1 << 3)
00240 #define PHYCON1_OP_MODE2            (1 << 2)
00241 #define PHYCON1_OP_MODE1            (1 << 1)
00242 #define PHYCON1_OP_MODE0            (1 << 0)
00243 
00244 //Operation mode indication
00245 #define PHYCON1_OP_MODE_MASK        (7 << 0)
00246 #define PHYCON1_OP_MODE_AN          (0 << 0)
00247 #define PHYCON1_OP_MODE_10BT        (1 << 0)
00248 #define PHYCON1_OP_MODE_100BTX      (2 << 0)
00249 #define PHYCON1_OP_MODE_10BT_FD     (5 << 0)
00250 #define PHYCON1_OP_MODE_100BTX_FD   (6 << 0)
00251 
00252 //PHYCON2 register
00253 #define PHYCON2_HP_MDIX             (1 << 15)
00254 #define PHYCON2_MDIX_SEL            (1 << 14)
00255 #define PHYCON2_PAIR_SWAP_DIS       (1 << 13)
00256 #define PHYCON2_FORCE_LINK          (1 << 11)
00257 #define PHYCON2_POWER_SAVING        (1 << 10)
00258 #define PHYCON2_INT_LEVEL           (1 << 9)
00259 #define PHYCON2_JABBER_EN           (1 << 8)
00260 #define PHYCON2_RMII_REF_CLK_SEL    (1 << 7)
00261 #define PHYCON2_LED_MODE1           (1 << 5)
00262 #define PHYCON2_LED_MODE0           (1 << 4)
00263 #define PHYCON2_TX_DIS              (1 << 3)
00264 #define PHYCON2_REMOTE_LOOPBACK     (1 << 2)
00265 #define PHYCON2_SCRAMBLER_DIS       (1 << 0)
00266 
00267 //KSZ8091 Ethernet PHY driver
00268 extern const PhyDriver ksz8091PhyDriver;
00269 
00270 //KSZ8091 related functions
00271 error_t ksz8091Init(NetInterface *interface);
00272 
00273 void ksz8091Tick(NetInterface *interface);
00274 
00275 void ksz8091EnableIrq(NetInterface *interface);
00276 void ksz8091DisableIrq(NetInterface *interface);
00277 
00278 void ksz8091EventHandler(NetInterface *interface);
00279 
00280 void ksz8091WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00281 uint16_t ksz8091ReadPhyReg(NetInterface *interface, uint8_t address);
00282 
00283 void ksz8091DumpPhyReg(NetInterface *interface);
00284 
00285 #endif
00286