ksz8081.h

00001 /**
00002  * @file ksz8081.h
00003  * @brief KSZ8081 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _KSZ8081_H
00030 #define _KSZ8081_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef KSZ8081_PHY_ADDR
00037    #define KSZ8081_PHY_ADDR 0
00038 #elif (KSZ8081_PHY_ADDR < 0 || KSZ8081_PHY_ADDR > 31)
00039    #error KSZ8081_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //KSZ8081 registers
00043 #define KSZ8081_PHY_REG_BMCR        0x00
00044 #define KSZ8081_PHY_REG_BMSR        0x01
00045 #define KSZ8081_PHY_REG_PHYIDR1     0x02
00046 #define KSZ8081_PHY_REG_PHYIDR2     0x03
00047 #define KSZ8081_PHY_REG_ANAR        0x04
00048 #define KSZ8081_PHY_REG_ANLPAR      0x05
00049 #define KSZ8081_PHY_REG_ANER        0x06
00050 #define KSZ8081_PHY_REG_ANNPTR      0x07
00051 #define KSZ8081_PHY_REG_LPNPAR      0x08
00052 #define KSZ8081_PHY_REG_DRC         0x10
00053 #define KSZ8081_PHY_REG_AFECON1     0x11
00054 #define KSZ8081_PHY_REG_RXERCTR     0x15
00055 #define KSZ8081_PHY_REG_OMSO        0x16
00056 #define KSZ8081_PHY_REG_OMSS        0x17
00057 #define KSZ8081_PHY_REG_EXCON       0x18
00058 #define KSZ8081_PHY_REG_ICSR        0x1B
00059 #define KSZ8081_PHY_REG_LINKMDCS    0x1D
00060 #define KSZ8081_PHY_REG_PHYCON1     0x1E
00061 #define KSZ8081_PHY_REG_PHYCON2     0x1F
00062 
00063 //BMCR register
00064 #define BMCR_RESET                  (1 << 15)
00065 #define BMCR_LOOPBACK               (1 << 14)
00066 #define BMCR_SPEED_SEL              (1 << 13)
00067 #define BMCR_AN_EN                  (1 << 12)
00068 #define BMCR_POWER_DOWN             (1 << 11)
00069 #define BMCR_ISOLATE                (1 << 10)
00070 #define BMCR_RESTART_AN             (1 << 9)
00071 #define BMCR_DUPLEX_MODE            (1 << 8)
00072 #define BMCR_COL_TEST               (1 << 7)
00073 
00074 //BMSR register
00075 #define BMSR_100BT4                 (1 << 15)
00076 #define BMSR_100BTX_FD              (1 << 14)
00077 #define BMSR_100BTX                 (1 << 13)
00078 #define BMSR_10BT_FD                (1 << 12)
00079 #define BMSR_10BT                   (1 << 11)
00080 #define BMSR_NO_PREAMBLE            (1 << 6)
00081 #define BMSR_AN_COMPLETE            (1 << 5)
00082 #define BMSR_REMOTE_FAULT           (1 << 4)
00083 #define BMSR_AN_ABLE                (1 << 3)
00084 #define BMSR_LINK_STATUS            (1 << 2)
00085 #define BMSR_JABBER_DETECT          (1 << 1)
00086 #define BMSR_EXTENDED_CAP           (1 << 0)
00087 
00088 //ANAR register
00089 #define ANAR_NEXT_PAGE              (1 << 15)
00090 #define ANAR_REMOTE_FAULT           (1 << 13)
00091 #define ANAR_PAUSE1                 (1 << 11)
00092 #define ANAR_PAUSE0                 (1 << 10)
00093 #define ANAR_100BT4                 (1 << 9)
00094 #define ANAR_100BTX_FD              (1 << 8)
00095 #define ANAR_100BTX                 (1 << 7)
00096 #define ANAR_10BT_FD                (1 << 6)
00097 #define ANAR_10BT                   (1 << 5)
00098 #define ANAR_SELECTOR4              (1 << 4)
00099 #define ANAR_SELECTOR3              (1 << 3)
00100 #define ANAR_SELECTOR2              (1 << 2)
00101 #define ANAR_SELECTOR1              (1 << 1)
00102 #define ANAR_SELECTOR0              (1 << 0)
00103 
00104 //ANLPAR register
00105 #define ANLPAR_NEXT_PAGE            (1 << 15)
00106 #define ANLPAR_LP_ACK               (1 << 14)
00107 #define ANLPAR_REMOTE_FAULT         (1 << 13)
00108 #define ANLPAR_PAUSE1               (1 << 11)
00109 #define ANLPAR_PAUSE0               (1 << 10)
00110 #define ANLPAR_100BT4               (1 << 9)
00111 #define ANLPAR_100BTX_FD            (1 << 8)
00112 #define ANLPAR_100BTX               (1 << 7)
00113 #define ANLPAR_10BT_FD              (1 << 6)
00114 #define ANLPAR_10BT                 (1 << 5)
00115 #define ANLPAR_SELECTOR4            (1 << 4)
00116 #define ANLPAR_SELECTOR3            (1 << 3)
00117 #define ANLPAR_SELECTOR2            (1 << 2)
00118 #define ANLPAR_SELECTOR1            (1 << 1)
00119 #define ANLPAR_SELECTOR0            (1 << 0)
00120 
00121 //ANER register
00122 #define ANER_PAR_DET_FAULT          (1 << 4)
00123 #define ANER_LP_NEXT_PAGE_ABLE      (1 << 3)
00124 #define ANER_NEXT_PAGE_ABLE         (1 << 2)
00125 #define ANER_PAGE_RECEIVED          (1 << 1)
00126 #define ANER_LP_AN_ABLE             (1 << 0)
00127 
00128 //ANNPTR register
00129 #define ANNPTR_NEXT_PAGE            (1 << 15)
00130 #define ANNPTR_MSG_PAGE             (1 << 13)
00131 #define ANNPTR_ACK2                 (1 << 12)
00132 #define ANNPTR_TOGGLE               (1 << 11)
00133 #define ANNPTR_MESSAGE10            (1 << 10)
00134 #define ANNPTR_MESSAGE9             (1 << 9)
00135 #define ANNPTR_MESSAGE8             (1 << 8)
00136 #define ANNPTR_MESSAGE7             (1 << 7)
00137 #define ANNPTR_MESSAGE6             (1 << 6)
00138 #define ANNPTR_MESSAGE5             (1 << 5)
00139 #define ANNPTR_MESSAGE4             (1 << 4)
00140 #define ANNPTR_MESSAGE3             (1 << 3)
00141 #define ANNPTR_MESSAGE2             (1 << 2)
00142 #define ANNPTR_MESSAGE1             (1 << 1)
00143 #define ANNPTR_MESSAGE0             (1 << 0)
00144 
00145 //LPNPAR register
00146 #define LPNPAR_NEXT_PAGE            (1 << 15)
00147 #define LPNPAR_ACK                  (1 << 14)
00148 #define LPNPAR_MSG_PAGE             (1 << 13)
00149 #define LPNPAR_ACK2                 (1 << 12)
00150 #define LPNPAR_TOGGLE               (1 << 11)
00151 #define LPNPAR_MESSAGE10            (1 << 10)
00152 #define LPNPAR_MESSAGE9             (1 << 9)
00153 #define LPNPAR_MESSAGE8             (1 << 8)
00154 #define LPNPAR_MESSAGE7             (1 << 7)
00155 #define LPNPAR_MESSAGE6             (1 << 6)
00156 #define LPNPAR_MESSAGE5             (1 << 5)
00157 #define LPNPAR_MESSAGE4             (1 << 4)
00158 #define LPNPAR_MESSAGE3             (1 << 3)
00159 #define LPNPAR_MESSAGE2             (1 << 2)
00160 #define LPNPAR_MESSAGE1             (1 << 1)
00161 #define LPNPAR_MESSAGE0             (1 << 0)
00162 
00163 //DRC register
00164 #define DRC_PLL_OFF                 (1 << 4)
00165 
00166 //AFECON1 register
00167 #define AFECON1_SLOW_OSC_MODE_EN    (1 << 5)
00168 
00169 //OMSO register
00170 #define OMSO_BCAST_OFF_OVERRIDE     (1 << 9)
00171 #define OMSO_MII_BTB_OVERRIDE       (1 << 7)
00172 #define OMSO_RMII_BTB_OVERRIDE      (1 << 6)
00173 #define OMSO_NAND_TREE_OVERRIDE     (1 << 5)
00174 #define OMSO_RMII_OVERRIDE          (1 << 1)
00175 #define OMSO_MII_OVERRIDE           (1 << 0)
00176 
00177 //OMSS register
00178 #define OMSS_PHYAD2                 (1 << 15)
00179 #define OMSS_PHYAD1                 (1 << 14)
00180 #define OMSS_PHYAD0                 (1 << 13)
00181 #define OMSS_RMII_STATUS            (1 << 1)
00182 
00183 //EXCON register
00184 #define EXCON_EDPD_DIS              (1 << 11)
00185 
00186 //ICSR register
00187 #define ICSR_JABBER_IE              (1 << 15)
00188 #define ICSR_RECEIVE_ERROR_IE       (1 << 14)
00189 #define ICSR_PAGE_RECEIVED_IE       (1 << 13)
00190 #define ICSR_PAR_DET_FAULT_IE       (1 << 12)
00191 #define ICSR_LP_ACK_IE              (1 << 11)
00192 #define ICSR_LINK_DOWN_IE           (1 << 10)
00193 #define ICSR_REMOTE_FAULT_IE        (1 << 9)
00194 #define ICSR_LINK_UP_IE             (1 << 8)
00195 #define ICSR_JABBER_IF              (1 << 7)
00196 #define ICSR_RECEIVE_ERROR_IF       (1 << 6)
00197 #define ICSR_PAGE_RECEIVED_IF       (1 << 5)
00198 #define ICSR_PAR_DET_FAULT_IF       (1 << 4)
00199 #define ICSR_LP_ACK_IF              (1 << 3)
00200 #define ICSR_LINK_DOWN_IF           (1 << 2)
00201 #define ICSR_REMOTE_FAULT_IF        (1 << 1)
00202 #define ICSR_LINK_UP_IF             (1 << 0)
00203 
00204 //LINKMDCS register
00205 #define LINKMDCS_CABLE_DIAG_EN      (1 << 15)
00206 #define LINKMDCS_CABLE_DIAG_RES1    (1 << 14)
00207 #define LINKMDCS_CABLE_DIAG_RES0    (1 << 13)
00208 #define LINKMDCS_SHORT_CABLE        (1 << 12)
00209 #define LINKMDCS_CABLE_FAULT_CNT8   (1 << 8)
00210 #define LINKMDCS_CABLE_FAULT_CNT7   (1 << 7)
00211 #define LINKMDCS_CABLE_FAULT_CNT6   (1 << 6)
00212 #define LINKMDCS_CABLE_FAULT_CNT5   (1 << 5)
00213 #define LINKMDCS_CABLE_FAULT_CNT4   (1 << 4)
00214 #define LINKMDCS_CABLE_FAULT_CNT3   (1 << 3)
00215 #define LINKMDCS_CABLE_FAULT_CNT2   (1 << 2)
00216 #define LINKMDCS_CABLE_FAULT_CNT1   (1 << 1)
00217 #define LINKMDCS_CABLE_FAULT_CNT0   (1 << 0)
00218 
00219 //PHYCON1 register
00220 #define PHYCON1_PAUSE_EN            (1 << 9)
00221 #define PHYCON1_LINK_STATUS         (1 << 8)
00222 #define PHYCON1_POL_STATUS          (1 << 7)
00223 #define PHYCON1_MDIX_STATE          (1 << 5)
00224 #define PHYCON1_ENERGY_DETECT       (1 << 4)
00225 #define PHYCON1_ISOLATE             (1 << 3)
00226 #define PHYCON1_OP_MODE2            (1 << 2)
00227 #define PHYCON1_OP_MODE1            (1 << 1)
00228 #define PHYCON1_OP_MODE0            (1 << 0)
00229 
00230 //Operation mode indication
00231 #define PHYCON1_OP_MODE_MASK        (7 << 0)
00232 #define PHYCON1_OP_MODE_AN          (0 << 0)
00233 #define PHYCON1_OP_MODE_10BT        (1 << 0)
00234 #define PHYCON1_OP_MODE_100BTX      (2 << 0)
00235 #define PHYCON1_OP_MODE_10BT_FD     (5 << 0)
00236 #define PHYCON1_OP_MODE_100BTX_FD   (6 << 0)
00237 
00238 //PHYCON2 register
00239 #define PHYCON2_HP_MDIX             (1 << 15)
00240 #define PHYCON2_MDIX_SEL            (1 << 14)
00241 #define PHYCON2_PAIR_SWAP_DIS       (1 << 13)
00242 #define PHYCON2_FORCE_LINK          (1 << 11)
00243 #define PHYCON2_POWER_SAVING        (1 << 10)
00244 #define PHYCON2_INT_LEVEL           (1 << 9)
00245 #define PHYCON2_JABBER_EN           (1 << 8)
00246 #define PHYCON2_RMII_REF_CLK_SEL    (1 << 7)
00247 #define PHYCON2_LED_MODE1           (1 << 5)
00248 #define PHYCON2_LED_MODE0           (1 << 4)
00249 #define PHYCON2_TX_DIS              (1 << 3)
00250 #define PHYCON2_REMOTE_LOOPBACK     (1 << 2)
00251 #define PHYCON2_SCRAMBLER_DIS       (1 << 0)
00252 
00253 //KSZ8081 Ethernet PHY driver
00254 extern const PhyDriver ksz8081PhyDriver;
00255 
00256 //KSZ8081 related functions
00257 error_t ksz8081Init(NetInterface *interface);
00258 
00259 void ksz8081Tick(NetInterface *interface);
00260 
00261 void ksz8081EnableIrq(NetInterface *interface);
00262 void ksz8081DisableIrq(NetInterface *interface);
00263 
00264 void ksz8081EventHandler(NetInterface *interface);
00265 
00266 void ksz8081WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00267 uint16_t ksz8081ReadPhyReg(NetInterface *interface, uint8_t address);
00268 
00269 void ksz8081DumpPhyReg(NetInterface *interface);
00270 
00271 #endif
00272