system_stm32f7xx.c

00001 /**
00002   ******************************************************************************
00003   * @file    Templates/system_stm32f7xx.c
00004   * @author  MCD Application Team
00005   * @version V1.0.1
00006   * @date    22-April-2016
00007   * @brief   - CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
00008   *          - This file is dedicated only for STM32F746 NUCLEO 144 boards.
00009   *
00010   *   This file provides two functions and one global variable to be called from
00011   *   user application:
00012   *      - SystemInit(): This function is called at startup just after reset and
00013   *                      before branch to main program. This call is made inside
00014   *                      the "startup_stm32f7xx.s" file.
00015   *
00016   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00017   *                                  by the user application to setup the SysTick
00018   *                                  timer or configure other parameters.
00019   *
00020   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00021   *                                 be called whenever the core clock is changed
00022   *                                 during program execution.
00023   *
00024   *
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
00029   *
00030   * Redistribution and use in source and binary forms, with or without modification,
00031   * are permitted provided that the following conditions are met:
00032   *   1. Redistributions of source code must retain the above copyright notice,
00033   *      this list of conditions and the following disclaimer.
00034   *   2. Redistributions in binary form must reproduce the above copyright notice,
00035   *      this list of conditions and the following disclaimer in the documentation
00036   *      and/or other materials provided with the distribution.
00037   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00038   *      may be used to endorse or promote products derived from this software
00039   *      without specific prior written permission.
00040   *
00041   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00042   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00043   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00044   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00045   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00046   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00047   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00048   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00049   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00050   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00051   *
00052   ******************************************************************************
00053   */
00054 
00055 /** @addtogroup CMSIS
00056   * @{
00057   */
00058 
00059 /** @addtogroup stm32f7xx_system
00060   * @{
00061   */
00062 
00063 /** @addtogroup STM32F7xx_System_Private_Includes
00064   * @{
00065   */
00066 
00067 #include "stm32f7xx.h"
00068 
00069 #if !defined  (HSE_VALUE)
00070   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
00071 #endif /* HSE_VALUE */
00072 
00073 #if !defined  (HSI_VALUE)
00074   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
00075 #endif /* HSI_VALUE */
00076 
00077 /**
00078   * @}
00079   */
00080 
00081 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
00082   * @{
00083   */
00084 
00085 /**
00086   * @}
00087   */
00088 
00089 /** @addtogroup STM32F7xx_System_Private_Defines
00090   * @{
00091   */
00092 
00093 /************************* Miscellaneous Configuration ************************/
00094 /*!< Uncomment the following line if you need to relocate your vector Table in
00095      Internal SRAM. */
00096 /* #define VECT_TAB_SRAM */
00097 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
00098                                    This value must be a multiple of 0x200. */
00099 /******************************************************************************/
00100 
00101 /**
00102   * @}
00103   */
00104 
00105 /** @addtogroup STM32F7xx_System_Private_Macros
00106   * @{
00107   */
00108 
00109 /**
00110   * @}
00111   */
00112 
00113 /** @addtogroup STM32F7xx_System_Private_Variables
00114   * @{
00115   */
00116 
00117   /* This variable is updated in three ways:
00118       1) by calling CMSIS function SystemCoreClockUpdate()
00119       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
00120       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
00121          Note: If you use this function to configure the system clock; then there
00122                is no need to call the 2 first functions listed above, since SystemCoreClock
00123                variable is updated automatically.
00124   */
00125   uint32_t SystemCoreClock = 16000000;
00126   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00127   const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
00128 
00129 /**
00130   * @}
00131   */
00132 
00133 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
00134   * @{
00135   */
00136 
00137 /**
00138   * @}
00139   */
00140 
00141 /** @addtogroup STM32F7xx_System_Private_Functions
00142   * @{
00143   */
00144 
00145 /**
00146   * @brief  Setup the microcontroller system
00147   *         Initialize the Embedded Flash Interface, the PLL and update the
00148   *         SystemFrequency variable.
00149   * @param  None
00150   * @retval None
00151   */
00152 void SystemInit(void)
00153 {
00154   /* FPU settings ------------------------------------------------------------*/
00155   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
00156     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
00157   #endif
00158   /* Reset the RCC clock configuration to the default reset state ------------*/
00159   /* Set HSION bit */
00160   RCC->CR |= (uint32_t)0x00000001;
00161 
00162   /* Reset CFGR register */
00163   RCC->CFGR = 0x00000000;
00164 
00165   /* Reset HSEON, CSSON and PLLON bits */
00166   RCC->CR &= (uint32_t)0xFEF6FFFF;
00167 
00168   /* Reset PLLCFGR register */
00169   RCC->PLLCFGR = 0x24003010;
00170 
00171   /* Reset HSEBYP bit */
00172   RCC->CR &= (uint32_t)0xFFFBFFFF;
00173 
00174   /* Disable all interrupts */
00175   RCC->CIR = 0x00000000;
00176 
00177   /* Configure the Vector Table location add offset address ------------------*/
00178 #ifdef VECT_TAB_SRAM
00179   //SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
00180 #else
00181   //SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
00182 #endif
00183 }
00184 
00185 /**
00186    * @brief  Update SystemCoreClock variable according to Clock Register Values.
00187   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00188   *         be used by the user application to setup the SysTick timer or configure
00189   *         other parameters.
00190   *
00191   * @note   Each time the core clock (HCLK) changes, this function must be called
00192   *         to update SystemCoreClock variable value. Otherwise, any configuration
00193   *         based on this variable will be incorrect.
00194   *
00195   * @note   - The system frequency computed by this function is not the real
00196   *           frequency in the chip. It is calculated based on the predefined
00197   *           constant and the selected clock source:
00198   *
00199   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00200   *
00201   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00202   *
00203   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00204   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
00205   *
00206   *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
00207   *             16 MHz) but the real value may vary depending on the variations
00208   *             in voltage and temperature.
00209   *
00210   *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
00211   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
00212   *              frequency of the crystal used. Otherwise, this function may
00213   *              have wrong result.
00214   *
00215   *         - The result of this function could be not correct when using fractional
00216   *           value for HSE crystal.
00217   *
00218   * @param  None
00219   * @retval None
00220   */
00221 void SystemCoreClockUpdate(void)
00222 {
00223   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
00224 
00225   /* Get SYSCLK source -------------------------------------------------------*/
00226   tmp = RCC->CFGR & RCC_CFGR_SWS;
00227 
00228   switch (tmp)
00229   {
00230     case 0x00:  /* HSI used as system clock source */
00231       SystemCoreClock = HSI_VALUE;
00232       break;
00233     case 0x04:  /* HSE used as system clock source */
00234       SystemCoreClock = HSE_VALUE;
00235       break;
00236     case 0x08:  /* PLL used as system clock source */
00237 
00238       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
00239          SYSCLK = PLL_VCO / PLL_P
00240          */
00241       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
00242       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
00243 
00244       if (pllsource != 0)
00245       {
00246         /* HSE used as PLL clock source */
00247         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
00248       }
00249       else
00250       {
00251         /* HSI used as PLL clock source */
00252         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
00253       }
00254 
00255       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
00256       SystemCoreClock = pllvco/pllp;
00257       break;
00258     default:
00259       SystemCoreClock = HSI_VALUE;
00260       break;
00261   }
00262   /* Compute HCLK frequency --------------------------------------------------*/
00263   /* Get HCLK prescaler */
00264   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00265   /* HCLK frequency */
00266   SystemCoreClock >>= tmp;
00267 }
00268 
00269 /**
00270   * @}
00271   */
00272 
00273 /**
00274   * @}
00275   */
00276 
00277 /**
00278   * @}
00279   */
00280 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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