fm4_eth.h

00001 /**
00002  * @file fm4_eth.h
00003  * @brief Spansion FM4 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _FM4_ETH_H
00030 #define _FM4_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef FM4_ETH_TX_BUFFER_COUNT
00037    #define FM4_ETH_TX_BUFFER_COUNT 3
00038 #elif (FM4_ETH_TX_BUFFER_COUNT < 1)
00039    #error FM4_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef FM4_ETH_TX_BUFFER_SIZE
00044    #define FM4_ETH_TX_BUFFER_SIZE 1536
00045 #elif (FM4_ETH_TX_BUFFER_SIZE != 1536)
00046    #error FM4_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef FM4_ETH_RX_BUFFER_COUNT
00051    #define FM4_ETH_RX_BUFFER_COUNT 6
00052 #elif (FM4_ETH_RX_BUFFER_COUNT < 1)
00053    #error FM4_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef FM4_ETH_RX_BUFFER_SIZE
00058    #define FM4_ETH_RX_BUFFER_SIZE 1536
00059 #elif (FM4_ETH_RX_BUFFER_SIZE != 1536)
00060    #error FM4_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Interrupt priority grouping
00064 #ifndef FM4_ETH_IRQ_PRIORITY_GROUPING
00065    #define FM4_ETH_IRQ_PRIORITY_GROUPING 3
00066 #elif (FM4_ETH_IRQ_PRIORITY_GROUPING < 0)
00067    #error FM4_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
00068 #endif
00069 
00070 //Ethernet interrupt group priority
00071 #ifndef FM4_ETH_IRQ_GROUP_PRIORITY
00072    #define FM4_ETH_IRQ_GROUP_PRIORITY 12
00073 #elif (FM4_ETH_IRQ_GROUP_PRIORITY < 0)
00074    #error FM4_ETH_IRQ_GROUP_PRIORITY parameter is not valid
00075 #endif
00076 
00077 //Ethernet interrupt subpriority
00078 #ifndef FM4_ETH_IRQ_SUB_PRIORITY
00079    #define FM4_ETH_IRQ_SUB_PRIORITY 0
00080 #elif (FM4_ETH_IRQ_SUB_PRIORITY < 0)
00081    #error FM4_ETH_IRQ_SUB_PRIORITY parameter is not valid
00082 #endif
00083 
00084 //Transmit DMA descriptor flags
00085 #define ETH_TDES0_OWN    0x80000000
00086 #define ETH_TDES0_IC     0x40000000
00087 #define ETH_TDES0_LS     0x20000000
00088 #define ETH_TDES0_FS     0x10000000
00089 #define ETH_TDES0_DC     0x08000000
00090 #define ETH_TDES0_DP     0x04000000
00091 #define ETH_TDES0_TTSE   0x02000000
00092 #define ETH_TDES0_CIC    0x00C00000
00093 #define ETH_TDES0_TER    0x00200000
00094 #define ETH_TDES0_TCH    0x00100000
00095 #define ETH_TDES0_TTSS   0x00020000
00096 #define ETH_TDES0_IHE    0x00010000
00097 #define ETH_TDES0_ES     0x00008000
00098 #define ETH_TDES0_JT     0x00004000
00099 #define ETH_TDES0_FF     0x00002000
00100 #define ETH_TDES0_IPE    0x00001000
00101 #define ETH_TDES0_LCA    0x00000800
00102 #define ETH_TDES0_NC     0x00000400
00103 #define ETH_TDES0_LCO    0x00000200
00104 #define ETH_TDES0_EC     0x00000100
00105 #define ETH_TDES0_VF     0x00000080
00106 #define ETH_TDES0_CC     0x00000078
00107 #define ETH_TDES0_ED     0x00000004
00108 #define ETH_TDES0_UF     0x00000002
00109 #define ETH_TDES0_DB     0x00000001
00110 #define ETH_TDES1_TBS2   0x1FFF0000
00111 #define ETH_TDES1_TBS1   0x00001FFF
00112 #define ETH_TDES2_B1AP   0xFFFFFFFF
00113 #define ETH_TDES3_B2AP   0xFFFFFFFF
00114 #define ETH_TDES6_TTSL   0xFFFFFFFF
00115 #define ETH_TDES7_TTSH   0xFFFFFFFF
00116 
00117 //Receive DMA descriptor flags
00118 #define ETH_RDES0_OWN    0x80000000
00119 #define ETH_RDES0_AFM    0x40000000
00120 #define ETH_RDES0_FL     0x3FFF0000
00121 #define ETH_RDES0_ES     0x00008000
00122 #define ETH_RDES0_DE     0x00004000
00123 #define ETH_RDES0_SAF    0x00002000
00124 #define ETH_RDES0_LE     0x00001000
00125 #define ETH_RDES0_OE     0x00000800
00126 #define ETH_RDES0_VLAN   0x00000400
00127 #define ETH_RDES0_FS     0x00000200
00128 #define ETH_RDES0_LS     0x00000100
00129 #define ETH_RDES0_TS     0x00000080
00130 #define ETH_RDES0_LCO    0x00000040
00131 #define ETH_RDES0_FT     0x00000020
00132 #define ETH_RDES0_RWT    0x00000010
00133 #define ETH_RDES0_RE     0x00000008
00134 #define ETH_RDES0_DBE    0x00000004
00135 #define ETH_RDES0_CE     0x00000002
00136 #define ETH_RDES0_ESA    0x00000001
00137 #define ETH_RDES1_DIC    0x80000000
00138 #define ETH_RDES1_RBS2   0x1FFF0000
00139 #define ETH_RDES1_RER    0x00008000
00140 #define ETH_RDES1_RCH    0x00004000
00141 #define ETH_RDES1_RBS1   0x00001FFF
00142 #define ETH_RDES2_B1AP  0xFFFFFFFF
00143 #define ETH_RDES3_B2AP  0xFFFFFFFF
00144 #define ETH_RDES4_TD     0x00004000
00145 #define ETH_RDES4_PV     0x00002000
00146 #define ETH_RDES4_PFT    0x00001000
00147 #define ETH_RDES4_MT     0x00000F00
00148 #define ETH_RDES4_IP6R   0x00000080
00149 #define ETH_RDES4_IP4R   0x00000040
00150 #define ETH_RDES4_IPCB   0x00000020
00151 #define ETH_RDES4_IPE    0x00000010
00152 #define ETH_RDES4_IPHE   0x00000008
00153 #define ETH_RDES4_IPT    0x00000007
00154 #define ETH_RDES6_RTSL   0xFFFFFFFF
00155 #define ETH_RDES7_RTSH   0xFFFFFFFF
00156 
00157 
00158 /**
00159  * @brief Enhanced TX DMA descriptor
00160  **/
00161 
00162 typedef struct
00163 {
00164    uint32_t tdes0;
00165    uint32_t tdes1;
00166    uint32_t tdes2;
00167    uint32_t tdes3;
00168    uint32_t tdes4;
00169    uint32_t tdes5;
00170    uint32_t tdes6;
00171    uint32_t tdes7;
00172 } Fm4TxDmaDesc;
00173 
00174 
00175 /**
00176  * @brief Enhanced RX DMA descriptor
00177  **/
00178 
00179 typedef struct
00180 {
00181    uint32_t rdes0;
00182    uint32_t rdes1;
00183    uint32_t rdes2;
00184    uint32_t rdes3;
00185    uint32_t rdes4;
00186    uint32_t rdes5;
00187    uint32_t rdes6;
00188    uint32_t rdes7;
00189 } Fm4RxDmaDesc;
00190 
00191 
00192 //Spansion FM4 Ethernet MAC driver
00193 extern const NicDriver fm4EthDriver;
00194 
00195 //Spansion FM4 Ethernet MAC related functions
00196 error_t fm4EthInit(NetInterface *interface);
00197 void fm4EthInitGpio(NetInterface *interface);
00198 void fm4EthInitDmaDesc(NetInterface *interface);
00199 
00200 void fm4EthTick(NetInterface *interface);
00201 
00202 void fm4EthEnableIrq(NetInterface *interface);
00203 void fm4EthDisableIrq(NetInterface *interface);
00204 void fm4EthEventHandler(NetInterface *interface);
00205 
00206 error_t fm4EthSendPacket(NetInterface *interface,
00207    const NetBuffer *buffer, size_t offset);
00208 
00209 error_t fm4EthReceivePacket(NetInterface *interface);
00210 
00211 error_t fm4EthSetMulticastFilter(NetInterface *interface);
00212 error_t fm4EthUpdateMacConfig(NetInterface *interface);
00213 
00214 void fm4EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00215 uint16_t fm4EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00216 
00217 uint32_t fm4EthCalcCrc(const void *data, size_t length);
00218 
00219 #endif
00220