f28m35x_eth.h

00001 /**
00002  * @file f28m35x_eth.h
00003  * @brief F28M35x Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _F28M35X_ETH_H
00030 #define _F28M35X_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Interrupt priority grouping
00036 #ifndef F28M35X_ETH_IRQ_PRIORITY_GROUPING
00037    #define F28M35X_ETH_IRQ_PRIORITY_GROUPING 3
00038 #elif (F28M35X_ETH_IRQ_PRIORITY_GROUPING < 0)
00039    #error F28M35X_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
00040 #endif
00041 
00042 //Ethernet interrupt priority
00043 #ifndef F28M35X_ETH_IRQ_PRIORITY
00044    #define F28M35X_ETH_IRQ_PRIORITY 192
00045 #elif (F28M35X_ETH_IRQ_PRIORITY < 0)
00046    #error F28M35X_ETH_IRQ_PRIORITY parameter is not valid
00047 #endif
00048 
00049 //F28M35x Ethernet MAC registers
00050 #define MAC_RIS_R    HWREG(ETH_BASE + MAC_O_RIS)
00051 #define MAC_IACK_R   HWREG(ETH_BASE + MAC_O_IACK)
00052 #define MAC_IM_R     HWREG(ETH_BASE + MAC_O_IM)
00053 #define MAC_RCTL_R   HWREG(ETH_BASE + MAC_O_RCTL)
00054 #define MAC_TCTL_R   HWREG(ETH_BASE + MAC_O_TCTL)
00055 #define MAC_DATA_R   HWREG(ETH_BASE + MAC_O_DATA)
00056 #define MAC_IA0_R    HWREG(ETH_BASE + MAC_O_IA0)
00057 #define MAC_IA1_R    HWREG(ETH_BASE + MAC_O_IA1)
00058 #define MAC_THR_R    HWREG(ETH_BASE + MAC_O_THR)
00059 #define MAC_MCTL_R   HWREG(ETH_BASE + MAC_O_MCTL)
00060 #define MAC_MDV_R    HWREG(ETH_BASE + MAC_O_MDV)
00061 #define MAC_MAR_R    HWREG(ETH_BASE + 0x28)
00062 #define MAC_MTXD_R   HWREG(ETH_BASE + MAC_O_MTXD)
00063 #define MAC_MRXD_R   HWREG(ETH_BASE + MAC_O_MRXD)
00064 #define MAC_NP_R     HWREG(ETH_BASE + MAC_O_NP)
00065 #define MAC_TR_R     HWREG(ETH_BASE + MAC_O_TR)
00066 #define MAC_TS_R     HWREG(ETH_BASE + MAC_O_TS)
00067 
00068 //F28M35x Ethernet MAC driver
00069 extern const NicDriver f28m35xEthDriver;
00070 
00071 //F28M35x Ethernet MAC related functions
00072 error_t f28m35xEthInit(NetInterface *interface);
00073 void f28m35xEthInitGpio(NetInterface *interface);
00074 
00075 void f28m35xEthTick(NetInterface *interface);
00076 
00077 void f28m35xEthEnableIrq(NetInterface *interface);
00078 void f28m35xEthDisableIrq(NetInterface *interface);
00079 void f28m35xEthIrqHandler(void);
00080 void f28m35xEthEventHandler(NetInterface *interface);
00081 
00082 error_t f28m35xEthSendPacket(NetInterface *interface,
00083    const NetBuffer *buffer, size_t offset);
00084 
00085 error_t f28m35xEthReceivePacket(NetInterface *interface);
00086 
00087 error_t f28m35xEthSetMulticastFilter(NetInterface *interface);
00088 error_t f28m35xEthUpdateMacConfig(NetInterface *interface);
00089 
00090 void f28m35xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00091 uint16_t f28m35xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00092 
00093 #endif
00094