enc624j600.h

00001 /**
00002  * @file enc624j600.h
00003  * @brief ENC624J600/ENC424J600 Ethernet controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _ENC624J600_H
00030 #define _ENC624J600_H
00031 
00032 //Receive and transmit buffers
00033 #define ENC624J600_TX_BUFFER_START 0x0000
00034 #define ENC624J600_TX_BUFFER_STOP  0x17FE
00035 #define ENC624J600_RX_BUFFER_START 0x1800
00036 #define ENC624J600_RX_BUFFER_STOP  0x5FFE
00037 
00038 //SPI command set
00039 #define ENC624J600_CMD_B0SEL       0xC0 //Bank 0 Select
00040 #define ENC624J600_CMD_B1SEL       0xC2 //Bank 1 Select
00041 #define ENC624J600_CMD_B2SEL       0xC4 //Bank 2 Select
00042 #define ENC624J600_CMD_B3SEL       0xC6 //Bank 3 Select
00043 #define ENC624J600_CMD_SETETHRST   0xCA //System Reset
00044 #define ENC624J600_CMD_FCDISABLE   0xE0 //Flow Control Disable
00045 #define ENC624J600_CMD_FCSINGLE    0xE2 //Flow Control Single
00046 #define ENC624J600_CMD_FCMULTIPLE  0xE4 //Flow Control Multiple
00047 #define ENC624J600_CMD_FCCLEAR     0xE6 //Flow Control Clear
00048 #define ENC624J600_CMD_SETPKTDEC   0xCC //Decrement Packet Counter
00049 #define ENC624J600_CMD_DMASTOP     0xD2 //DMA Stop
00050 #define ENC624J600_CMD_DMACKSUM    0xD8 //DMA Start Checksum
00051 #define ENC624J600_CMD_DMACKSUMS   0xDA //DMA Start Checksum with Seed
00052 #define ENC624J600_CMD_DMACOPY     0xDC //DMA Start Copy
00053 #define ENC624J600_CMD_DMACOPYS    0xDE //DMA Start Copy and Checksum with Seed
00054 #define ENC624J600_CMD_SETTXRTS    0xD4 //Request Packet Transmission
00055 #define ENC624J600_CMD_ENABLERX    0xE8 //Enable RX
00056 #define ENC624J600_CMD_DISABLERX   0xEA //Disable RX
00057 #define ENC624J600_CMD_SETEIE      0xEC //Enable Interrupts
00058 #define ENC624J600_CMD_CLREIE      0xEE //Disable Interrupts
00059 #define ENC624J600_CMD_RBSEL       0xC8 //Read Bank Select
00060 #define ENC624J600_CMD_WGPRDPT     0x60 //Write EGPRDPT
00061 #define ENC624J600_CMD_RGPRDPT     0x62 //Read EGPRDPT
00062 #define ENC624J600_CMD_WRXRDPT     0x64 //Write ERXRDPT
00063 #define ENC624J600_CMD_RRXRDPT     0x66 //Read ERXRDPT
00064 #define ENC624J600_CMD_WUDARDPT    0x68 //Write EUDARDPT
00065 #define ENC624J600_CMD_RUDARDPT    0x6A //Read EUDARDPT
00066 #define ENC624J600_CMD_WGPWRPT     0x6C //Write EGPWRPT
00067 #define ENC624J600_CMD_RGPWRPT     0x6E //Read EGPWRPT
00068 #define ENC624J600_CMD_WRXWRPT     0x70 //Write ERXWRPT
00069 #define ENC624J600_CMD_RRXWRPT     0x72 //Read ERXWRPT
00070 #define ENC624J600_CMD_WUDAWRPT    0x74 //Write EUDAWRPT
00071 #define ENC624J600_CMD_RUDAWRPT    0x76 //Read EUDAWRPT
00072 #define ENC624J600_CMD_RCR         0x00 //Read Control Register
00073 #define ENC624J600_CMD_WCR         0x40 //Write Control Register
00074 #define ENC624J600_CMD_RCRU        0x20 //Read Control Register Unbanked
00075 #define ENC624J600_CMD_WCRU        0x22 //Write Control Register Unbanked
00076 #define ENC624J600_CMD_BFS         0x80 //Bit Field Set
00077 #define ENC624J600_CMD_BFC         0xA0 //Bit Field Clear
00078 #define ENC624J600_CMD_BFSU        0x24 //Bit Field Set Unbanked
00079 #define ENC624J600_CMD_BFCU        0x26 //Bit Field Clear Unbanked
00080 #define ENC624J600_CMD_RGPDATA     0x28 //Read EGPDATA
00081 #define ENC624J600_CMD_WGPDATA     0x2A //Write EGPDATA
00082 #define ENC624J600_CMD_RRXDATA     0x2C //Read ERXDATA
00083 #define ENC624J600_CMD_WRXDATA     0x2E //Write ERXDATA
00084 #define ENC624J600_CMD_RUDADATA    0x30 //Read EUDADATA
00085 #define ENC624J600_CMD_WUDADATA    0x32 //Write EUDADATA
00086 
00087 //ENC624J600 registers
00088 #define ENC624J600_REG_ETXST       0x00
00089 #define ENC624J600_REG_ETXLEN      0x02
00090 #define ENC624J600_REG_ERXST       0x04
00091 #define ENC624J600_REG_ERXTAIL     0x06
00092 #define ENC624J600_REG_ERXHEAD     0x08
00093 #define ENC624J600_REG_EDMAST      0x0A
00094 #define ENC624J600_REG_EDMALEN     0x0C
00095 #define ENC624J600_REG_EDMADST     0x0E
00096 #define ENC624J600_REG_EDMACS      0x10
00097 #define ENC624J600_REG_ETXSTAT     0x12
00098 #define ENC624J600_REG_ETXWIRE     0x14
00099 #define ENC624J600_REG_EUDAST      0x16
00100 #define ENC624J600_REG_EUDAND      0x18
00101 #define ENC624J600_REG_ESTAT       0x1A
00102 #define ENC624J600_REG_EIR         0x1C
00103 #define ENC624J600_REG_ECON1       0x1E
00104 #define ENC624J600_REG_EHT1        0x20
00105 #define ENC624J600_REG_EHT2        0x22
00106 #define ENC624J600_REG_EHT3        0x24
00107 #define ENC624J600_REG_EHT4        0x26
00108 #define ENC624J600_REG_EPMM1       0x28
00109 #define ENC624J600_REG_EPMM2       0x2A
00110 #define ENC624J600_REG_EPMM3       0x2C
00111 #define ENC624J600_REG_EPMM4       0x2E
00112 #define ENC624J600_REG_EPMCS       0x30
00113 #define ENC624J600_REG_EPMO        0x32
00114 #define ENC624J600_REG_ERXFCON     0x34
00115 #define ENC624J600_REG_MACON1      0x40
00116 #define ENC624J600_REG_MACON2      0x42
00117 #define ENC624J600_REG_MABBIPG     0x44
00118 #define ENC624J600_REG_MAIPG       0x46
00119 #define ENC624J600_REG_MACLCON     0x48
00120 #define ENC624J600_REG_MAMXFL      0x4A
00121 #define ENC624J600_REG_MICMD       0x52
00122 #define ENC624J600_REG_MIREGADR    0x54
00123 #define ENC624J600_REG_MAADR3      0x60
00124 #define ENC624J600_REG_MAADR2      0x62
00125 #define ENC624J600_REG_MAADR1      0x64
00126 #define ENC624J600_REG_MIWR        0x66
00127 #define ENC624J600_REG_MIRD        0x68
00128 #define ENC624J600_REG_MISTAT      0x6A
00129 #define ENC624J600_REG_EPAUS       0x6C
00130 #define ENC624J600_REG_ECON2       0x6E
00131 #define ENC624J600_REG_ERXWM       0x70
00132 #define ENC624J600_REG_EIE         0x72
00133 #define ENC624J600_REG_EIDLED      0x74
00134 #define ENC624J600_REG_EGPDATA     0x80
00135 #define ENC624J600_REG_ERXDATA     0x82
00136 #define ENC624J600_REG_EUDADATA    0x84
00137 #define ENC624J600_REG_EGPRDPT     0x86
00138 #define ENC624J600_REG_EGPWRPT     0x88
00139 #define ENC624J600_REG_ERXRDPT     0x8A
00140 #define ENC624J600_REG_ERXWRPT     0x8C
00141 #define ENC624J600_REG_EUDARDPT    0x8E
00142 #define ENC624J600_REG_EUDAWRPT    0x90
00143 
00144 //ENC624J600 PHY registers
00145 #define ENC624J600_PHY_REG_PHCON1  0x00
00146 #define ENC624J600_PHY_REG_PHSTAT1 0x01
00147 #define ENC624J600_PHY_REG_PHANA   0x04
00148 #define ENC624J600_PHY_REG_PHANLPA 0x05
00149 #define ENC624J600_PHY_REG_PHANE   0x06
00150 #define ENC624J600_PHY_REG_PHCON2  0x11
00151 #define ENC624J600_PHY_REG_PHSTAT2 0x1B
00152 #define ENC624J600_PHY_REG_PHSTAT3 0x1F
00153 
00154 //ESTAT register
00155 #define ESTAT_INT                  0x8000
00156 #define ESTAT_FCIDLE               0x4000
00157 #define ESTAT_RXBUSY               0x2000
00158 #define ESTAT_CLKRDY               0x1000
00159 #define ESTAT_R11                  0x0800
00160 #define ESTAT_PHYDPX               0x0400
00161 #define ESTAT_R9                   0x0200
00162 #define ESTAT_PHYLNK               0x0100
00163 #define ESTAT_PKTCNT               0x00FF
00164 
00165 //EIR register
00166 #define EIR_CRYPTEN                0x8000
00167 #define EIR_MODEXIF                0x4000
00168 #define EIR_HASHIF                 0x2000
00169 #define EIR_AESIF                  0x1000
00170 #define EIR_LINKIF                 0x0800
00171 #define EIR_R10                    0x0400
00172 #define EIR_R9                     0x0200
00173 #define EIR_R8                     0x0100
00174 #define EIR_R7                     0x0080
00175 #define EIR_PKTIF                  0x0040
00176 #define EIR_DMAIF                  0x0020
00177 #define EIR_R4                     0x0010
00178 #define EIR_TXIF                   0x0008
00179 #define EIR_TXABTIF                0x0004
00180 #define EIR_RXABTIF                0x0002
00181 #define EIR_PCFULIF                0x0001
00182 
00183 //ECON1 register
00184 #define ECON1_MODEXST              0x8000
00185 #define ECON1_HASHEN               0x4000
00186 #define ECON1_HASHOP               0x2000
00187 #define ECON1_HASHLST              0x1000
00188 #define ECON1_AESST                0x0800
00189 #define ECON1_AESOP1               0x0400
00190 #define ECON1_AESOP0               0x0200
00191 #define ECON1_PKTDEC               0x0100
00192 #define ECON1_FCOP1                0x0080
00193 #define ECON1_FCOP0                0x0040
00194 #define ECON1_DMAST                0x0020
00195 #define ECON1_DMACPY               0x0010
00196 #define ECON1_DMACSSD              0x0008
00197 #define ECON1_DMANOCS              0x0004
00198 #define ECON1_TXRTS                0x0002
00199 #define ECON1_RXEN                 0x0001
00200 
00201 //ETXSTAT register
00202 #define ETXSTAT_R12                0x1000
00203 #define ETXSTAT_R11                0x0800
00204 #define ETXSTAT_LATECOL            0x0400
00205 #define ETXSTAT_MAXCOL             0x0200
00206 #define ETXSTAT_EXDEFER            0x0100
00207 #define ETXSTAT_DEFER              0x0080
00208 #define ETXSTAT_R6                 0x0040
00209 #define ETXSTAT_R5                 0x0020
00210 #define ETXSTAT_CRCBAD             0x0010
00211 #define ETXSTAT_COLCNT             0x000F
00212 
00213 //ERXFCON register
00214 #define ERXFCON_HTEN               0x8000
00215 #define ERXFCON_MPEN               0x4000
00216 #define ERXFCON_NOTPM              0x1000
00217 #define ERXFCON_PMEN3              0x0800
00218 #define ERXFCON_PMEN2              0x0400
00219 #define ERXFCON_PMEN1              0x0200
00220 #define ERXFCON_PMEN0              0x0100
00221 #define ERXFCON_CRCEEN             0x0080
00222 #define ERXFCON_CRCEN              0x0040
00223 #define ERXFCON_RUNTEEN            0x0020
00224 #define ERXFCON_RUNTEN             0x0010
00225 #define ERXFCON_UCEN               0x0008
00226 #define ERXFCON_NOTMEEN            0x0004
00227 #define ERXFCON_MCEN               0x0002
00228 #define ERXFCON_BCEN               0x0001
00229 
00230 //MACON1 register
00231 #define MACON1_R15                 0x8000
00232 #define MACON1_R14                 0x4000
00233 #define MACON1_R11                 0x0800
00234 #define MACON1_R10                 0x0400
00235 #define MACON1_R9                  0x0200
00236 #define MACON1_R8                  0x0100
00237 #define MACON1_LOOPBK              0x0010
00238 #define MACON1_R3                  0x0008
00239 #define MACON1_RXPAUS              0x0004
00240 #define MACON1_PASSALL             0x0002
00241 #define MACON1_R0                  0x0001
00242 
00243 //MACON2 register
00244 #define MACON2_DEFER               0x4000
00245 #define MACON2_BPEN                0x2000
00246 #define MACON2_NOBKOFF             0x1000
00247 #define MACON2_R9                  0x0200
00248 #define MACON2_R8                  0x0100
00249 #define MACON2_PADCFG2             0x0080
00250 #define MACON2_PADCFG1             0x0040
00251 #define MACON2_PADCFG0             0x0020
00252 #define MACON2_TXCRCEN             0x0010
00253 #define MACON2_PHDREN              0x0008
00254 #define MACON2_HFRMEN              0x0004
00255 #define MACON2_R1                  0x0002
00256 #define MACON2_FULDPX              0x0001
00257 
00258 //MABBIPG register
00259 #define MABBIPG_BBIPG              0x007F
00260 
00261 //MAIPG register
00262 #define MAIPG_R14                  0x4000
00263 #define MAIPG_R13                  0x2000
00264 #define MAIPG_R12                  0x1000
00265 #define MAIPG_R11                  0x0800
00266 #define MAIPG_R10                  0x0400
00267 #define MAIPG_R9                   0x0200
00268 #define MAIPG_R8                   0x0100
00269 #define MAIPG_IPG                  0x007F
00270 
00271 //MACLCON register
00272 #define MACLCON_R13                0x2000
00273 #define MACLCON_R12                0x1000
00274 #define MACLCON_R11                0x0800
00275 #define MACLCON_R10                0x0400
00276 #define MACLCON_R9                 0x0200
00277 #define MACLCON_R8                 0x0100
00278 #define MACLCON_MAXRET             0x000F
00279 
00280 //MICMD register
00281 #define MICMD_MIISCAN              0x0002
00282 #define MICMD_MIIRD                0x0001
00283 
00284 //MIREGADR register
00285 #define MIREGADR_R12               0x1000
00286 #define MIREGADR_R11               0x0800
00287 #define MIREGADR_R10               0x0400
00288 #define MIREGADR_R9                0x0200
00289 #define MIREGADR_R8                0x0100
00290 #define MIREGADR_PHREG             0x001F
00291 
00292 //MISTAT register
00293 #define MISTAT_R3                  0x0008
00294 #define MISTAT_NVALID              0x0004
00295 #define MISTAT_SCAN                0x0002
00296 #define MISTAT_BUSY                0x0001
00297 
00298 //ECON2 register
00299 #define ECON2_ETHEN                0x8000
00300 #define ECON2_STRCH                0x4000
00301 #define ECON2_TXMAC                0x2000
00302 #define ECON2_SHA1MD5              0x1000
00303 #define ECON2_COCON3               0x0800
00304 #define ECON2_COCON2               0x0400
00305 #define ECON2_COCON1               0x0200
00306 #define ECON2_COCON0               0x0100
00307 #define ECON2_AUTOFC               0x0080
00308 #define ECON2_TXRST                0x0040
00309 #define ECON2_RXRST                0x0020
00310 #define ECON2_ETHRST               0x0010
00311 #define ECON2_MODLEN1              0x0008
00312 #define ECON2_MODLEN0              0x0004
00313 #define ECON2_AESLEN1              0x0002
00314 #define ECON2_AESLEN0              0x0001
00315 
00316 //ERXWM register
00317 #define ERXWM_RXFWM                0xFF00
00318 #define ERXWM_RXEWM                0x00FF
00319 
00320 //EIE register
00321 #define EIE_INTIE                  0x8000
00322 #define EIE_MODEXIE                0x4000
00323 #define EIE_HASHIE                 0x2000
00324 #define EIE_AESIE                  0x1000
00325 #define EIE_LINKIE                 0x0800
00326 #define EIE_R10                    0x0400
00327 #define EIE_R9                     0x0200
00328 #define EIE_R8                     0x0100
00329 #define EIE_R7                     0x0080
00330 #define EIE_PKTIE                  0x0040
00331 #define EIE_DMAIE                  0x0020
00332 #define EIE_R4                     0x0010
00333 #define EIE_TXIE                   0x0008
00334 #define EIE_TXABTIE                0x0004
00335 #define EIE_RXABTIE                0x0002
00336 #define EIE_PCFULIE                0x0001
00337 
00338 //EIDLED register
00339 #define EIDLED_LACFG3              0x8000
00340 #define EIDLED_LACFG2              0x4000
00341 #define EIDLED_LACFG1              0x2000
00342 #define EIDLED_LACFG0              0x1000
00343 #define EIDLED_LBCFG3              0x0800
00344 #define EIDLED_LBCFG2              0x0400
00345 #define EIDLED_LBCFG1              0x0200
00346 #define EIDLED_LBCFG0              0x0100
00347 #define EIDLED_DEVID               0x00FF
00348 
00349 //PHCON1 register
00350 #define PHCON1_PRST                0x8000
00351 #define PHCON1_PLOOPBK             0x4000
00352 #define PHCON1_SPD100              0x2000
00353 #define PHCON1_ANEN                0x1000
00354 #define PHCON1_PSLEEP              0x0800
00355 #define PHCON1_RENEG               0x0200
00356 #define PHCON1_PFULDPX             0x0100
00357 
00358 //PHSTAT1 register
00359 #define PHSTAT1_FULL100            0x4000
00360 #define PHSTAT1_HALF100            0x2000
00361 #define PHSTAT1_FULL10             0x1000
00362 #define PHSTAT1_HALF10             0x0800
00363 #define PHSTAT1_ANDONE             0x0020
00364 #define PHSTAT1_LRFAULT            0x0010
00365 #define PHSTAT1_ANABLE             0x0008
00366 #define PHSTAT1_LLSTAT             0x0004
00367 #define PHSTAT1_EXTREGS            0x0001
00368 
00369 //PHANA register
00370 #define PHANA_ADNP                 0x8000
00371 #define PHANA_ADFAULT              0x2000
00372 #define PHANA_ADPAUS1              0x0800
00373 #define PHANA_ADPAUS0              0x0400
00374 #define PHANA_AD100FD              0x0100
00375 #define PHANA_AD100                0x0080
00376 #define PHANA_AD10FD               0x0040
00377 #define PHANA_AD10                 0x0020
00378 #define PHANA_ADIEEE4              0x0010
00379 #define PHANA_ADIEEE3              0x0008
00380 #define PHANA_ADIEEE2              0x0004
00381 #define PHANA_ADIEEE1              0x0002
00382 #define PHANA_ADIEEE0              0x0001
00383 
00384 //PHANLPA register
00385 #define PHANLPA_LPNP               0x8000
00386 #define PHANLPA_LPACK              0x4000
00387 #define PHANLPA_LPFAULT            0x2000
00388 #define PHANLPA_LPPAUS1            0x0800
00389 #define PHANLPA_LPPAUS0            0x0400
00390 #define PHANLPA_LP100T4            0x0200
00391 #define PHANLPA_LP100FD            0x0100
00392 #define PHANLPA_LP100              0x0080
00393 #define PHANLPA_LP10FD             0x0040
00394 #define PHANLPA_LP10               0x0020
00395 #define PHANLPA_LPIEEE             0x001F
00396 #define PHANLPA_LPIEEE4            0x0010
00397 #define PHANLPA_LPIEEE3            0x0008
00398 #define PHANLPA_LPIEEE2            0x0004
00399 #define PHANLPA_LPIEEE1            0x0002
00400 #define PHANLPA_LPIEEE0            0x0001
00401 
00402 //PHANE register
00403 #define PHANE_PDFLT                0x0010
00404 #define PHANE_LPARCD               0x0002
00405 #define PHANE_LPANABL              0x0001
00406 
00407 //PHCON2 register
00408 #define PHCON2_EDPWRDN             0x2000
00409 #define PHCON2_EDTHRES             0x0800
00410 #define PHCON2_FRCLNK              0x0004
00411 #define PHCON2_EDSTAT              0x0002
00412 
00413 //PHSTAT2 register
00414 #define PHSTAT2_PLRITY             0x0010
00415 
00416 //PHSTAT3 register
00417 #define PHSTAT3_SPDDPX2            0x0010
00418 #define PHSTAT3_SPDDPX1            0x0008
00419 #define PHSTAT3_SPDDPX0            0x0004
00420 
00421 //Receive status vector
00422 #define RSV_UNICAST_FILTER         0x00100000
00423 #define RSV_PATTERN_MATCH_FILTER   0x00080000
00424 #define RSV_MAGIC_PACKET_FILTER    0x00040000
00425 #define RSV_HASH_FILTER            0x00020000
00426 #define RSV_NOT_ME_FILTER          0x00010000
00427 #define RSV_RUNT_FILTER            0x00008000
00428 #define RSV_VLAN_TYPE              0x00004000
00429 #define RSV_UNKNOWN_OPCODE         0x00002000
00430 #define RSV_PAUSE_CONTROL_FRAME    0x00001000
00431 #define RSV_CONTROL_FRAME          0x00000800
00432 #define RSV_DRIBBLE_NIBBLE         0x00000400
00433 #define RSV_BROADCAST_PACKET       0x00000200
00434 #define RSV_MULTICAST_PACKET       0x00000100
00435 #define RSV_RECEIVED_OK            0x00000080
00436 #define RSV_LENGTH_OUT_OF_RANGE    0x00000040
00437 #define RSV_LENGTH_CHECK_ERROR     0x00000020
00438 #define RSV_CRC_ERROR              0x00000010
00439 #define RSV_CARRIER_EVENT          0x00000004
00440 #define RSV_PACKET_IGNORED         0x00000001
00441 
00442 
00443 /**
00444  * @brief ENC624J600 driver context
00445  **/
00446 
00447 typedef struct
00448 {
00449    uint16_t nextPacket; ///<Next packet in the receive buffer
00450    uint8_t *rxBuffer;   ///<Receive buffer
00451 } Enc624j600Context;
00452 
00453 
00454 //ENC624J600 driver
00455 extern const NicDriver enc624j600Driver;
00456 
00457 //ENC624J600 related functions
00458 error_t enc624j600Init(NetInterface *interface);
00459 
00460 void enc624j600Tick(NetInterface *interface);
00461 
00462 void enc624j600EnableIrq(NetInterface *interface);
00463 void enc624j600DisableIrq(NetInterface *interface);
00464 bool_t enc624j600IrqHandler(NetInterface *interface);
00465 void enc624j600EventHandler(NetInterface *interface);
00466 
00467 error_t enc624j600SendPacket(NetInterface *interface,
00468    const NetBuffer *buffer, size_t offset);
00469 
00470 error_t enc624j600ReceivePacket(NetInterface *interface);
00471 
00472 error_t enc624j600SetMulticastFilter(NetInterface *interface);
00473 void enc624j600UpdateMacConfig(NetInterface *interface);
00474 
00475 error_t enc624j600SoftReset(NetInterface *interface);
00476 
00477 void enc624j600WriteReg(NetInterface *interface, uint8_t address, uint16_t data);
00478 uint16_t enc624j600ReadReg(NetInterface *interface, uint8_t address);
00479 
00480 void enc624j600WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00481 uint16_t enc624j600ReadPhyReg(NetInterface *interface, uint8_t address);
00482 
00483 void enc624j600WriteBuffer(NetInterface *interface,
00484    uint8_t opcode, const NetBuffer *buffer, size_t offset);
00485 
00486 void enc624j600ReadBuffer(NetInterface *interface,
00487    uint8_t opcode, uint8_t *data, size_t length);
00488 
00489 void enc624j600SetBit(NetInterface *interface, uint8_t address, uint16_t mask);
00490 void enc624j600ClearBit(NetInterface *interface, uint8_t address, uint16_t mask);
00491 
00492 uint32_t enc624j600CalcCrc(const void *data, size_t length);
00493 
00494 void enc624j600DumpReg(NetInterface *interface);
00495 void enc624j600DumpPhyReg(NetInterface *interface);
00496 
00497 #endif
00498