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enc28j60.h
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00001 /** 00002 * @file enc28j60.h 00003 * @brief ENC28J60 Ethernet controller 00004 * 00005 * @section License 00006 * 00007 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved. 00008 * 00009 * This file is part of CycloneTCP Open. 00010 * 00011 * This program is free software; you can redistribute it and/or 00012 * modify it under the terms of the GNU General Public License 00013 * as published by the Free Software Foundation; either version 2 00014 * of the License, or (at your option) any later version. 00015 * 00016 * This program is distributed in the hope that it will be useful, 00017 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00019 * GNU General Public License for more details. 00020 * 00021 * You should have received a copy of the GNU General Public License 00022 * along with this program; if not, write to the Free Software Foundation, 00023 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00024 * 00025 * @author Oryx Embedded SARL (www.oryx-embedded.com) 00026 * @version 1.7.6 00027 **/ 00028 00029 #ifndef _ENC28J60_H 00030 #define _ENC28J60_H 00031 00032 //Full-duplex support 00033 #ifndef ENC28J60_FULL_DUPLEX_SUPPORT 00034 #define ENC28J60_FULL_DUPLEX_SUPPORT ENABLED 00035 #elif (ENC28J60_FULL_DUPLEX_SUPPORT != ENABLED && ENC28J60_FULL_DUPLEX_SUPPORT != DISABLED) 00036 #error ENC28J60_FULL_DUPLEX_SUPPORT parameter is not valid 00037 #endif 00038 00039 //Silicon revision identifiers 00040 #define ENC28J60_REV_B1 0x02 00041 #define ENC28J60_REV_B4 0x04 00042 #define ENC28J60_REV_B5 0x05 00043 #define ENC28J60_REV_B7 0x06 00044 00045 //Receive and transmit buffers 00046 #define ENC28J60_RX_BUFFER_START 0x0000 00047 #define ENC28J60_RX_BUFFER_STOP 0x17FF 00048 #define ENC28J60_TX_BUFFER_START 0x1800 00049 #define ENC28J60_TX_BUFFER_STOP 0x1FFF 00050 00051 //SPI command set 00052 #define ENC28J60_CMD_RCR 0x00 00053 #define ENC28J60_CMD_RBM 0x3A 00054 #define ENC28J60_CMD_WCR 0x40 00055 #define ENC28J60_CMD_WBM 0x7A 00056 #define ENC28J60_CMD_BFS 0x80 00057 #define ENC28J60_CMD_BFC 0xA0 00058 #define ENC28J60_CMD_SRC 0xFF 00059 00060 //ENC28J60 register types 00061 #define ETH_REG_TYPE 0x0000 00062 #define MAC_REG_TYPE 0x1000 00063 #define MII_REG_TYPE 0x2000 00064 #define PHY_REG_TYPE 0x3000 00065 00066 //ENC28J60 banks 00067 #define BANK_0 0x0000 00068 #define BANK_1 0x0100 00069 #define BANK_2 0x0200 00070 #define BANK_3 0x0300 00071 00072 //Related masks 00073 #define REG_TYPE_MASK 0xF000 00074 #define REG_BANK_MASK 0x0F00 00075 #define REG_ADDR_MASK 0x001F 00076 00077 //Bank 0 registers 00078 #define ENC28J60_REG_ERDPTL (ETH_REG_TYPE | BANK_0 | 0x00) 00079 #define ENC28J60_REG_ERDPTH (ETH_REG_TYPE | BANK_0 | 0x01) 00080 #define ENC28J60_REG_EWRPTL (ETH_REG_TYPE | BANK_0 | 0x02) 00081 #define ENC28J60_REG_EWRPTH (ETH_REG_TYPE | BANK_0 | 0x03) 00082 #define ENC28J60_REG_ETXSTL (ETH_REG_TYPE | BANK_0 | 0x04) 00083 #define ENC28J60_REG_ETXSTH (ETH_REG_TYPE | BANK_0 | 0x05) 00084 #define ENC28J60_REG_ETXNDL (ETH_REG_TYPE | BANK_0 | 0x06) 00085 #define ENC28J60_REG_ETXNDH (ETH_REG_TYPE | BANK_0 | 0x07) 00086 #define ENC28J60_REG_ERXSTL (ETH_REG_TYPE | BANK_0 | 0x08) 00087 #define ENC28J60_REG_ERXSTH (ETH_REG_TYPE | BANK_0 | 0x09) 00088 #define ENC28J60_REG_ERXNDL (ETH_REG_TYPE | BANK_0 | 0x0A) 00089 #define ENC28J60_REG_ERXNDH (ETH_REG_TYPE | BANK_0 | 0x0B) 00090 #define ENC28J60_REG_ERXRDPTL (ETH_REG_TYPE | BANK_0 | 0x0C) 00091 #define ENC28J60_REG_ERXRDPTH (ETH_REG_TYPE | BANK_0 | 0x0D) 00092 #define ENC28J60_REG_ERXWRPTL (ETH_REG_TYPE | BANK_0 | 0x0E) 00093 #define ENC28J60_REG_ERXWRPTH (ETH_REG_TYPE | BANK_0 | 0x0F) 00094 #define ENC28J60_REG_EDMASTL (ETH_REG_TYPE | BANK_0 | 0x10) 00095 #define ENC28J60_REG_EDMASTH (ETH_REG_TYPE | BANK_0 | 0x11) 00096 #define ENC28J60_REG_EDMANDL (ETH_REG_TYPE | BANK_0 | 0x12) 00097 #define ENC28J60_REG_EDMANDH (ETH_REG_TYPE | BANK_0 | 0x13) 00098 #define ENC28J60_REG_EDMADSTL (ETH_REG_TYPE | BANK_0 | 0x14) 00099 #define ENC28J60_REG_EDMADSTH (ETH_REG_TYPE | BANK_0 | 0x15) 00100 #define ENC28J60_REG_EDMACSL (ETH_REG_TYPE | BANK_0 | 0x16) 00101 #define ENC28J60_REG_EDMACSH (ETH_REG_TYPE | BANK_0 | 0x17) 00102 #define ENC28J60_REG_EIE (ETH_REG_TYPE | BANK_0 | 0x1B) 00103 #define ENC28J60_REG_EIR (ETH_REG_TYPE | BANK_0 | 0x1C) 00104 #define ENC28J60_REG_ESTAT (ETH_REG_TYPE | BANK_0 | 0x1D) 00105 #define ENC28J60_REG_ECON2 (ETH_REG_TYPE | BANK_0 | 0x1E) 00106 #define ENC28J60_REG_ECON1 (ETH_REG_TYPE | BANK_0 | 0x1F) 00107 00108 //Bank 1 registers 00109 #define ENC28J60_REG_EHT0 (ETH_REG_TYPE | BANK_1 | 0x00) 00110 #define ENC28J60_REG_EHT1 (ETH_REG_TYPE | BANK_1 | 0x01) 00111 #define ENC28J60_REG_EHT2 (ETH_REG_TYPE | BANK_1 | 0x02) 00112 #define ENC28J60_REG_EHT3 (ETH_REG_TYPE | BANK_1 | 0x03) 00113 #define ENC28J60_REG_EHT4 (ETH_REG_TYPE | BANK_1 | 0x04) 00114 #define ENC28J60_REG_EHT5 (ETH_REG_TYPE | BANK_1 | 0x05) 00115 #define ENC28J60_REG_EHT6 (ETH_REG_TYPE | BANK_1 | 0x06) 00116 #define ENC28J60_REG_EHT7 (ETH_REG_TYPE | BANK_1 | 0x07) 00117 #define ENC28J60_REG_EPMM0 (ETH_REG_TYPE | BANK_1 | 0x08) 00118 #define ENC28J60_REG_EPMM1 (ETH_REG_TYPE | BANK_1 | 0x09) 00119 #define ENC28J60_REG_EPMM2 (ETH_REG_TYPE | BANK_1 | 0x0A) 00120 #define ENC28J60_REG_EPMM3 (ETH_REG_TYPE | BANK_1 | 0x0B) 00121 #define ENC28J60_REG_EPMM4 (ETH_REG_TYPE | BANK_1 | 0x0C) 00122 #define ENC28J60_REG_EPMM5 (ETH_REG_TYPE | BANK_1 | 0x0D) 00123 #define ENC28J60_REG_EPMM6 (ETH_REG_TYPE | BANK_1 | 0x0E) 00124 #define ENC28J60_REG_EPMM7 (ETH_REG_TYPE | BANK_1 | 0x0F) 00125 #define ENC28J60_REG_EPMCSL (ETH_REG_TYPE | BANK_1 | 0x10) 00126 #define ENC28J60_REG_EPMCSH (ETH_REG_TYPE | BANK_1 | 0x11) 00127 #define ENC28J60_REG_EPMOL (ETH_REG_TYPE | BANK_1 | 0x14) 00128 #define ENC28J60_REG_EPMOH (ETH_REG_TYPE | BANK_1 | 0x15) 00129 #define ENC28J60_REG_EWOLIE (ETH_REG_TYPE | BANK_1 | 0x16) 00130 #define ENC28J60_REG_EWOLIR (ETH_REG_TYPE | BANK_1 | 0x17) 00131 #define ENC28J60_REG_ERXFCON (ETH_REG_TYPE | BANK_1 | 0x18) 00132 #define ENC28J60_REG_EPKTCNT (ETH_REG_TYPE | BANK_1 | 0x19) 00133 00134 //Bank 2 registers 00135 #define ENC28J60_REG_MACON1 (MAC_REG_TYPE | BANK_2 | 0x00) 00136 #define ENC28J60_REG_MACON2 (MAC_REG_TYPE | BANK_2 | 0x01) 00137 #define ENC28J60_REG_MACON3 (MAC_REG_TYPE | BANK_2 | 0x02) 00138 #define ENC28J60_REG_MACON4 (MAC_REG_TYPE | BANK_2 | 0x03) 00139 #define ENC28J60_REG_MABBIPG (MAC_REG_TYPE | BANK_2 | 0x04) 00140 #define ENC28J60_REG_MAIPGL (MAC_REG_TYPE | BANK_2 | 0x06) 00141 #define ENC28J60_REG_MAIPGH (MAC_REG_TYPE | BANK_2 | 0x07) 00142 #define ENC28J60_REG_MACLCON1 (MAC_REG_TYPE | BANK_2 | 0x08) 00143 #define ENC28J60_REG_MACLCON2 (MAC_REG_TYPE | BANK_2 | 0x09) 00144 #define ENC28J60_REG_MAMXFLL (MAC_REG_TYPE | BANK_2 | 0x0A) 00145 #define ENC28J60_REG_MAMXFLH (MAC_REG_TYPE | BANK_2 | 0x0B) 00146 #define ENC28J60_REG_MAPHSUP (MAC_REG_TYPE | BANK_2 | 0x0D) 00147 #define ENC28J60_REG_MICON (MII_REG_TYPE | BANK_2 | 0x11) 00148 #define ENC28J60_REG_MICMD (MII_REG_TYPE | BANK_2 | 0x12) 00149 #define ENC28J60_REG_MIREGADR (MII_REG_TYPE | BANK_2 | 0x14) 00150 #define ENC28J60_REG_MIWRL (MII_REG_TYPE | BANK_2 | 0x16) 00151 #define ENC28J60_REG_MIWRH (MII_REG_TYPE | BANK_2 | 0x17) 00152 #define ENC28J60_REG_MIRDL (MII_REG_TYPE | BANK_2 | 0x18) 00153 #define ENC28J60_REG_MIRDH (MII_REG_TYPE | BANK_2 | 0x19) 00154 00155 //Bank 3 registers 00156 #define ENC28J60_REG_MAADR5 (MAC_REG_TYPE | BANK_3 | 0x00) 00157 #define ENC28J60_REG_MAADR6 (MAC_REG_TYPE | BANK_3 | 0x01) 00158 #define ENC28J60_REG_MAADR3 (MAC_REG_TYPE | BANK_3 | 0x02) 00159 #define ENC28J60_REG_MAADR4 (MAC_REG_TYPE | BANK_3 | 0x03) 00160 #define ENC28J60_REG_MAADR1 (MAC_REG_TYPE | BANK_3 | 0x04) 00161 #define ENC28J60_REG_MAADR2 (MAC_REG_TYPE | BANK_3 | 0x05) 00162 #define ENC28J60_REG_EBSTSD (ETH_REG_TYPE | BANK_3 | 0x06) 00163 #define ENC28J60_REG_EBSTCON (ETH_REG_TYPE | BANK_3 | 0x07) 00164 #define ENC28J60_REG_EBSTCSL (ETH_REG_TYPE | BANK_3 | 0x08) 00165 #define ENC28J60_REG_EBSTCSH (ETH_REG_TYPE | BANK_3 | 0x09) 00166 #define ENC28J60_REG_MISTAT (MII_REG_TYPE | BANK_3 | 0x0A) 00167 #define ENC28J60_REG_EREVID (ETH_REG_TYPE | BANK_3 | 0x12) 00168 #define ENC28J60_REG_ECOCON (ETH_REG_TYPE | BANK_3 | 0x15) 00169 #define ENC28J60_REG_EFLOCON (ETH_REG_TYPE | BANK_3 | 0x17) 00170 #define ENC28J60_REG_EPAUSL (ETH_REG_TYPE | BANK_3 | 0x18) 00171 #define ENC28J60_REG_EPAUSH (ETH_REG_TYPE | BANK_3 | 0x19) 00172 00173 //PHY registers 00174 #define ENC28J60_PHY_REG_PHCON1 (PHY_REG_TYPE | 0x00) 00175 #define ENC28J60_PHY_REG_PHSTAT1 (PHY_REG_TYPE | 0x01) 00176 #define ENC28J60_PHY_REG_PHID1 (PHY_REG_TYPE | 0x02) 00177 #define ENC28J60_PHY_REG_PHID2 (PHY_REG_TYPE | 0x03) 00178 #define ENC28J60_PHY_REG_PHCON2 (PHY_REG_TYPE | 0x10) 00179 #define ENC28J60_PHY_REG_PHSTAT2 (PHY_REG_TYPE | 0x11) 00180 #define ENC28J60_PHY_REG_PHIE (PHY_REG_TYPE | 0x12) 00181 #define ENC28J60_PHY_REG_PHIR (PHY_REG_TYPE | 0x13) 00182 #define ENC28J60_PHY_REG_PHLCON (PHY_REG_TYPE | 0x14) 00183 00184 //EIE register 00185 #define EIE_INTIE (1 << 7) 00186 #define EIE_PKTIE (1 << 6) 00187 #define EIE_DMAIE (1 << 5) 00188 #define EIE_LINKIE (1 << 4) 00189 #define EIE_TXIE (1 << 3) 00190 #define EIE_WOLIE (1 << 2) 00191 #define EIE_TXERIE (1 << 1) 00192 #define EIE_RXERIE (1 << 0) 00193 00194 //EIR register 00195 #define EIR_PKTIF (1 << 6) 00196 #define EIR_DMAIF (1 << 5) 00197 #define EIR_LINKIF (1 << 4) 00198 #define EIR_TXIF (1 << 3) 00199 #define EIR_WOLIF (1 << 2) 00200 #define EIR_TXERIF (1 << 1) 00201 #define EIR_RXERIF (1 << 0) 00202 00203 //ESTAT register 00204 #define ESTAT_INT (1 << 7) 00205 #define ESTAT_LATECOL (1 << 4) 00206 #define ESTAT_RXBUSY (1 << 2) 00207 #define ESTAT_TXABRT (1 << 1) 00208 #define ESTAT_CLKRDY (1 << 0) 00209 00210 //ECON2 register 00211 #define ECON2_AUTOINC (1 << 7) 00212 #define ECON2_PKTDEC (1 << 6) 00213 #define ECON2_PWRSV (1 << 5) 00214 #define ECON2_VRPS (1 << 3) 00215 00216 //ECON1 register 00217 #define ECON1_TXRST (1 << 7) 00218 #define ECON1_RXRST (1 << 6) 00219 #define ECON1_DMAST (1 << 5) 00220 #define ECON1_CSUMEN (1 << 4) 00221 #define ECON1_TXRTS (1 << 3) 00222 #define ECON1_RXEN (1 << 2) 00223 #define ECON1_BSEL1 (1 << 1) 00224 #define ECON1_BSEL0 (1 << 0) 00225 00226 //ERXFCON register 00227 #define ERXFCON_UCEN (1 << 7) 00228 #define ERXFCON_ANDOR (1 << 6) 00229 #define ERXFCON_CRCEN (1 << 5) 00230 #define ERXFCON_PMEN (1 << 4) 00231 #define ERXFCON_MPEN (1 << 3) 00232 #define ERXFCON_HTEN (1 << 2) 00233 #define ERXFCON_MCEN (1 << 1) 00234 #define ERXFCON_BCEN (1 << 0) 00235 00236 //MACON1 register 00237 #define MACON1_LOOPBK (1 << 4) 00238 #define MACON1_TXPAUS (1 << 3) 00239 #define MACON1_RXPAUS (1 << 2) 00240 #define MACON1_PASSALL (1 << 1) 00241 #define MACON1_MARXEN (1 << 0) 00242 00243 //MACON2 register 00244 #define MACON2_MARST (1 << 7) 00245 #define MACON2_RNDRST (1 << 6) 00246 #define MACON2_MARXRST (1 << 3) 00247 #define MACON2_RFUNRST (1 << 2) 00248 #define MACON2_MATXRST (1 << 1) 00249 #define MACON2_TFUNRST (1 << 0) 00250 00251 //MACON3 register 00252 #define MACON3_PADCFG2 (1 << 7) 00253 #define MACON3_PADCFG1 (1 << 6) 00254 #define MACON3_PADCFG0 (1 << 5) 00255 #define MACON3_TXCRCEN (1 << 4) 00256 #define MACON3_PHDRLEN (1 << 3) 00257 #define MACON3_HFRMLEN (1 << 2) 00258 #define MACON3_FRMLNEN (1 << 1) 00259 #define MACON3_FULDPX (1 << 0) 00260 00261 #define MACON3_PADCFG(x) ((x) << 5) 00262 00263 //MACON4 register 00264 #define MACON4_DEFER (1 << 6) 00265 #define MACON4_BPEN (1 << 5) 00266 #define MACON4_NOBKOFF (1 << 4) 00267 #define MACON4_LONGPRE (1 << 1) 00268 #define MACON4_PUREPRE (1 << 0) 00269 00270 //MAPHSUP register 00271 #define MAPHSUP_RSTINTFC (1 << 7) 00272 #define MAPHSUP_RSTRMII (1 << 3) 00273 00274 //MICON register 00275 #define MICON_RSTMII (1 << 7) 00276 00277 //MICMD register 00278 #define MICMD_MIISCAN (1 << 1) 00279 #define MICMD_MIIRD (1 << 0) 00280 00281 //EBSTCON register 00282 #define EBSTCON_PSV2 (1 << 7) 00283 #define EBSTCON_PSV1 (1 << 6) 00284 #define EBSTCON_PSV0 (1 << 5) 00285 #define EBSTCON_PSEL (1 << 4) 00286 #define EBSTCON_TMSEL1 (1 << 3) 00287 #define EBSTCON_TMSEL0 (1 << 2) 00288 #define EBSTCON_TME (1 << 1) 00289 #define EBSTCON_BISTST (1 << 0) 00290 00291 //MISTAT register 00292 #define MISTAT_NVALID (1 << 2) 00293 #define MISTAT_SCAN (1 << 1) 00294 #define MISTAT_BUSY (1 << 0) 00295 00296 //ECOCON register 00297 #define ECOCON_COCON2 (1 << 2) 00298 #define ECOCON_COCON1 (1 << 1) 00299 #define ECOCON_COCON0 (1 << 0) 00300 00301 //EFLOCON register 00302 #define EFLOCON_FULDPXS (1 << 2) 00303 #define EFLOCON_FCEN1 (1 << 1) 00304 #define EFLOCON_FCEN0 (1 << 0) 00305 00306 //PHCON1 register 00307 #define PHCON1_PRST (1 << 15) 00308 #define PHCON1_PLOOPBK (1 << 14) 00309 #define PHCON1_PPWRSV (1 << 11) 00310 #define PHCON1_PDPXMD (1 << 8) 00311 00312 //PHSTAT1 register 00313 #define PHSTAT1_PFDPX (1 << 12) 00314 #define PHSTAT1_PHDPX (1 << 11) 00315 #define PHSTAT1_LLSTAT (1 << 2) 00316 #define PHSTAT1_JBSTAT (1 << 1) 00317 00318 //PHCON2 register 00319 #define PHCON2_FRCLINK (1 << 14) 00320 #define PHCON2_TXDIS (1 << 13) 00321 #define PHCON2_JABBER (1 << 10) 00322 #define PHCON2_HDLDIS (1 << 8) 00323 00324 //PHSTAT2 register 00325 #define PHSTAT2_TXSTAT (1 << 13) 00326 #define PHSTAT2_RXSTAT (1 << 12) 00327 #define PHSTAT2_COLSTAT (1 << 11) 00328 #define PHSTAT2_LSTAT (1 << 10) 00329 #define PHSTAT2_DPXSTAT (1 << 9) 00330 #define PHSTAT2_PLRITY (1 << 4) 00331 00332 //PHIE register 00333 #define PHIE_PLNKIE (1 << 4) 00334 #define PHIE_PGEIE (1 << 1) 00335 00336 //PHIR register 00337 #define PHIR_PLNKIF (1 << 4) 00338 #define PHIR_PGIF (1 << 2) 00339 00340 //PHLCON register 00341 #define PHLCON_LACFG3 (1 << 11) 00342 #define PHLCON_LACFG2 (1 << 10) 00343 #define PHLCON_LACFG1 (1 << 9) 00344 #define PHLCON_LACFG0 (1 << 8) 00345 #define PHLCON_LBCFG3 (1 << 7) 00346 #define PHLCON_LBCFG2 (1 << 6) 00347 #define PHLCON_LBCFG1 (1 << 5) 00348 #define PHLCON_LBCFG0 (1 << 4) 00349 #define PHLCON_LFRQ1 (1 << 3) 00350 #define PHLCON_LFRQ0 (1 << 2) 00351 #define PHLCON_STRCH (1 << 1) 00352 00353 #define PHLCON_LACFG(x) ((x) << 8) 00354 #define PHLCON_LBCFG(x) ((x) << 4) 00355 #define PHLCON_LFRQ(x) ((x) << 2) 00356 00357 //Per-packet control byte 00358 #define TX_CTRL_PHUGEEN (1 << 3) 00359 #define TX_CTRL_PPADEN (1 << 2) 00360 #define TX_CTRL_PCRCEN (1 << 1) 00361 #define TX_CTRL_POVERRIDE (1 << 0) 00362 00363 //Receive status vector 00364 #define RSV_VLAN_TYPE 0x4000 00365 #define RSV_UNKNOWN_OPCODE 0x2000 00366 #define RSV_PAUSE_CONTROL_FRAME 0x1000 00367 #define RSV_CONTROL_FRAME 0x0800 00368 #define RSV_DRIBBLE_NIBBLE 0x0400 00369 #define RSV_BROADCAST_PACKET 0x0200 00370 #define RSV_MULTICAST_PACKET 0x0100 00371 #define RSV_RECEIVED_OK 0x0080 00372 #define RSV_LENGTH_OUT_OF_RANGE 0x0040 00373 #define RSV_LENGTH_CHECK_ERROR 0x0020 00374 #define RSV_CRC_ERROR 0x0010 00375 #define RSV_CARRIER_EVENT 0x0004 00376 #define RSV_DROP_EVENT 0x0001 00377 00378 00379 /** 00380 * @brief ENC28J60 driver context 00381 **/ 00382 00383 typedef struct 00384 { 00385 uint16_t currentBank; ///<Current bank 00386 uint16_t nextPacket; ///<Next packet in the receive buffer 00387 uint8_t *rxBuffer; ///<Receive buffer 00388 } Enc28j60Context; 00389 00390 00391 //ENC28J60 driver 00392 extern const NicDriver enc28j60Driver; 00393 00394 //ENC28J60 related functions 00395 error_t enc28j60Init(NetInterface *interface); 00396 00397 void enc28j60Tick(NetInterface *interface); 00398 00399 void enc28j60EnableIrq(NetInterface *interface); 00400 void enc28j60DisableIrq(NetInterface *interface); 00401 bool_t enc28j60IrqHandler(NetInterface *interface); 00402 void enc28j60EventHandler(NetInterface *interface); 00403 00404 error_t enc28j60SendPacket(NetInterface *interface, 00405 const NetBuffer *buffer, size_t offset); 00406 00407 error_t enc28j60ReceivePacket(NetInterface *interface); 00408 00409 error_t enc28j60SetMulticastFilter(NetInterface *interface); 00410 00411 void enc28j60SoftReset(NetInterface *interface); 00412 void enc28j60SelectBank(NetInterface *interface, uint16_t address); 00413 00414 void enc28j60WriteReg(NetInterface *interface, uint16_t address, uint8_t data); 00415 uint8_t enc28j60ReadReg(NetInterface *interface, uint16_t address); 00416 00417 void enc28j60WritePhyReg(NetInterface *interface, uint16_t address, uint16_t data); 00418 uint16_t enc28j60ReadPhyReg(NetInterface *interface, uint16_t address); 00419 00420 void enc28j60WriteBuffer(NetInterface *interface, 00421 const NetBuffer *buffer, size_t offset); 00422 00423 void enc28j60ReadBuffer(NetInterface *interface, 00424 uint8_t *data, size_t length); 00425 00426 void enc28j60SetBit(NetInterface *interface, uint16_t address, uint16_t mask); 00427 void enc28j60ClearBit(NetInterface *interface, uint16_t address, uint16_t mask); 00428 00429 uint32_t enc28j60CalcCrc(const void *data, size_t length); 00430 00431 void enc28j60DumpReg(NetInterface *interface); 00432 void enc28j60DumpPhyReg(NetInterface *interface); 00433 00434 #endif 00435
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