dp83848.h

00001 /**
00002  * @file dp83848.h
00003  * @brief DP83848 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _DP83848_H
00030 #define _DP83848_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef DP83848_PHY_ADDR
00037    #define DP83848_PHY_ADDR 1
00038 #elif (DP83848_PHY_ADDR < 0 || DP83848_PHY_ADDR > 31)
00039    #error DP83848_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //DP83848 registers
00043 #define DP83848_PHY_REG_BMCR       0x00
00044 #define DP83848_PHY_REG_BMSR       0x01
00045 #define DP83848_PHY_REG_PHYIDR1    0x02
00046 #define DP83848_PHY_REG_PHYIDR2    0x03
00047 #define DP83848_PHY_REG_ANAR       0x04
00048 #define DP83848_PHY_REG_ANLPAR     0x05
00049 #define DP83848_PHY_REG_ANER       0x06
00050 #define DP83848_PHY_REG_ANNPTR     0x07
00051 #define DP83848_PHY_REG_PHYSTS     0x10
00052 #define DP83848_PHY_REG_MICR       0x11
00053 #define DP83848_PHY_REG_MISR       0x12
00054 #define DP83848_PHY_REG_FCSCR      0x14
00055 #define DP83848_PHY_REG_RECR       0x15
00056 #define DP83848_PHY_REG_PCSR       0x16
00057 #define DP83848_PHY_REG_RBR        0x17
00058 #define DP83848_PHY_REG_LEDCR      0x18
00059 #define DP83848_PHY_REG_PHYCR      0x19
00060 #define DP83848_PHY_REG_10BTSCR    0x1A
00061 #define DP83848_PHY_REG_CDCTRL1    0x1B
00062 #define DP83848_PHY_REG_EDCR       0x1D
00063 
00064 //BMCR register
00065 #define BMCR_RESET                 (1 << 15)
00066 #define BMCR_LOOPBACK              (1 << 14)
00067 #define BMCR_SPEED_SEL             (1 << 13)
00068 #define BMCR_AN_EN                 (1 << 12)
00069 #define BMCR_POWER_DOWN            (1 << 11)
00070 #define BMCR_ISOLATE               (1 << 10)
00071 #define BMCR_RESTART_AN            (1 << 9)
00072 #define BMCR_DUPLEX_MODE           (1 << 8)
00073 #define BMCR_COL_TEST              (1 << 7)
00074 
00075 //BMSR register
00076 #define BMSR_100BT4                (1 << 15)
00077 #define BMSR_100BTX_FD             (1 << 14)
00078 #define BMSR_100BTX                (1 << 13)
00079 #define BMSR_10BT_FD               (1 << 12)
00080 #define BMSR_10BT                  (1 << 11)
00081 #define BMSR_NO_PREAMBLE           (1 << 6)
00082 #define BMSR_AN_COMPLETE           (1 << 5)
00083 #define BMSR_REMOTE_FAULT          (1 << 4)
00084 #define BMSR_AN_ABLE               (1 << 3)
00085 #define BMSR_LINK_STATUS           (1 << 2)
00086 #define BMSR_JABBER_DETECT         (1 << 1)
00087 #define BMSR_EXTENDED_CAP          (1 << 0)
00088 
00089 //ANAR register
00090 #define ANAR_NP                    (1 << 15)
00091 #define ANAR_RF                    (1 << 13)
00092 #define ANAR_ASM_DIR               (1 << 11)
00093 #define ANAR_PAUSE                 (1 << 10)
00094 #define ANAR_100BT4                (1 << 9)
00095 #define ANAR_100BTX_FD             (1 << 8)
00096 #define ANAR_100BTX                (1 << 7)
00097 #define ANAR_10BT_FD               (1 << 6)
00098 #define ANAR_10BT                  (1 << 5)
00099 #define ANAR_SELECTOR4             (1 << 4)
00100 #define ANAR_SELECTOR3             (1 << 3)
00101 #define ANAR_SELECTOR2             (1 << 2)
00102 #define ANAR_SELECTOR1             (1 << 1)
00103 #define ANAR_SELECTOR0             (1 << 0)
00104 
00105 //ANLPAR register
00106 #define ANLPAR_NP                  (1 << 15)
00107 #define ANLPAR_ACK                 (1 << 14)
00108 #define ANLPAR_RF                  (1 << 13)
00109 #define ANLPAR_ASM_DIR             (1 << 11)
00110 #define ANLPAR_PAUSE               (1 << 10)
00111 #define ANLPAR_100BT4              (1 << 9)
00112 #define ANLPAR_100BTX_FD           (1 << 8)
00113 #define ANLPAR_100BTX              (1 << 7)
00114 #define ANLPAR_10BT_FD             (1 << 6)
00115 #define ANLPAR_10BT                (1 << 5)
00116 #define ANLPAR_SELECTOR4           (1 << 4)
00117 #define ANLPAR_SELECTOR3           (1 << 3)
00118 #define ANLPAR_SELECTOR2           (1 << 2)
00119 #define ANLPAR_SELECTOR1           (1 << 1)
00120 #define ANLPAR_SELECTOR0           (1 << 0)
00121 
00122 //ANER register
00123 #define ANER_PDF                   (1 << 4)
00124 #define ANER_LP_NP_ABLE            (1 << 3)
00125 #define ANER_NP_ABLE               (1 << 2)
00126 #define ANER_PAGE_RX               (1 << 1)
00127 #define ANER_LP_AN_ABLE            (1 << 0)
00128 
00129 //ANNPTR register
00130 #define ANNPTR_NP                  (1 << 15)
00131 #define ANNPTR_MP                  (1 << 13)
00132 #define ANNPTR_ACK2                (1 << 12)
00133 #define ANNPTR_TOG_TX              (1 << 11)
00134 #define ANNPTR_CODE10              (1 << 10)
00135 #define ANNPTR_CODE9               (1 << 9)
00136 #define ANNPTR_CODE8               (1 << 8)
00137 #define ANNPTR_CODE7               (1 << 7)
00138 #define ANNPTR_CODE6               (1 << 6)
00139 #define ANNPTR_CODE5               (1 << 5)
00140 #define ANNPTR_CODE4               (1 << 4)
00141 #define ANNPTR_CODE3               (1 << 3)
00142 #define ANNPTR_CODE2               (1 << 2)
00143 #define ANNPTR_CODE1               (1 << 1)
00144 #define ANNPTR_CODE0               (1 << 0)
00145 
00146 //PHYSTS register
00147 #define PHYSTS_MDIX_MODE           (1 << 14)
00148 #define PHYSTS_RX_ERROR_LATCH      (1 << 13)
00149 #define PHYSTS_POLARITY_STATUS     (1 << 12)
00150 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
00151 #define PHYSTS_SIGNAL_DETECT       (1 << 10)
00152 #define PHYSTS_DESCRAMBLER_LOCK    (1 << 9)
00153 #define PHYSTS_PAGE_RECEIVED       (1 << 8)
00154 #define PHYSTS_MII_INTERRUPT       (1 << 7)
00155 #define PHYSTS_REMOTE_FAULT        (1 << 6)
00156 #define PHYSTS_JABBER_DETECT       (1 << 5)
00157 #define PHYSTS_AN_COMPLETE         (1 << 4)
00158 #define PHYSTS_LOOPBACK_STATUS     (1 << 3)
00159 #define PHYSTS_DUPLEX_STATUS       (1 << 2)
00160 #define PHYSTS_SPEED_STATUS        (1 << 1)
00161 #define PHYSTS_LINK_STATUS         (1 << 0)
00162 
00163 //MICR register
00164 #define MICR_TINT                  (1 << 2)
00165 #define MICR_INTEN                 (1 << 1)
00166 #define MICR_INT_OE                (1 << 0)
00167 
00168 //MISR register
00169 #define MISR_ED_INT                (1 << 14)
00170 #define MISR_LINK_INT              (1 << 13)
00171 #define MISR_SPD_INT               (1 << 12)
00172 #define MISR_DUP_INT               (1 << 11)
00173 #define MISR_ANC_INT               (1 << 10)
00174 #define MISR_FHF_INT               (1 << 9)
00175 #define MISR_RHF_INT               (1 << 8)
00176 #define MISR_ED_INT_EN             (1 << 6)
00177 #define MISR_LINK_INT_EN           (1 << 5)
00178 #define MISR_SPD_INT_EN            (1 << 4)
00179 #define MISR_DUP_INT_EN            (1 << 3)
00180 #define MISR_ANC_INT_EN            (1 << 2)
00181 #define MISR_FHF_INT_EN            (1 << 1)
00182 #define MISR_RHF_INT_EN            (1 << 0)
00183 
00184 //FCSCR register
00185 #define FCSCR_FCSCNT7              (1 << 7)
00186 #define FCSCR_FCSCNT6              (1 << 6)
00187 #define FCSCR_FCSCNT5              (1 << 5)
00188 #define FCSCR_FCSCNT4              (1 << 4)
00189 #define FCSCR_FCSCNT3              (1 << 3)
00190 #define FCSCR_FCSCNT2              (1 << 2)
00191 #define FCSCR_FCSCNT1              (1 << 1)
00192 #define FCSCR_FCSCNT0              (1 << 0)
00193 
00194 //RECR register
00195 #define RECR_RXERCNT7              (1 << 7)
00196 #define RECR_RXERCNT6              (1 << 6)
00197 #define RECR_RXERCNT5              (1 << 5)
00198 #define RECR_RXERCNT4              (1 << 4)
00199 #define RECR_RXERCNT3              (1 << 3)
00200 #define RECR_RXERCNT2              (1 << 2)
00201 #define RECR_RXERCNT1              (1 << 1)
00202 #define RECR_RXERCNT0              (1 << 0)
00203 
00204 //PCSR register
00205 #define PCSR_TQ_EN                 (1 << 10)
00206 #define PCSR_SD_FORCE_PMA          (1 << 9)
00207 #define PCSR_SD_OPTION             (1 << 8)
00208 #define PCSR_DESC_TIME             (1 << 7)
00209 #define PCSR_FORCE_100_OK          (1 << 5)
00210 #define PCSR_NRZI_BYPASS           (1 << 2)
00211 
00212 //RBR register
00213 #define RBR_RMII_MODE              (1 << 5)
00214 #define RBR_RMII_REV1_0            (1 << 4)
00215 #define RBR_RX_OVF_STS             (1 << 3)
00216 #define RBR_RX_UNF_STS             (1 << 2)
00217 #define RBR_ELAST_BUF1             (1 << 1)
00218 #define RBR_ELAST_BUF0             (1 << 0)
00219 
00220 //LEDCR register
00221 #define LEDCR_DRV_SPDLED           (1 << 5)
00222 #define LEDCR_DRV_LNKLED           (1 << 4)
00223 #define LEDCR_DRV_ACTLED           (1 << 3)
00224 #define LEDCR_SPDLED               (1 << 2)
00225 #define LEDCR_LNKLED               (1 << 1)
00226 #define LEDCR_ACTLED               (1 << 0)
00227 
00228 //PHYCR register
00229 #define PHYCR_MDIX_EN              (1 << 15)
00230 #define PHYCR_FORCE_MDIX           (1 << 14)
00231 #define PHYCR_PAUSE_RX             (1 << 13)
00232 #define PHYCR_PAUSE_TX             (1 << 12)
00233 #define PHYCR_BIST_FE              (1 << 11)
00234 #define PHYCR_PSR_15               (1 << 10)
00235 #define PHYCR_BIST_STATUS          (1 << 9)
00236 #define PHYCR_BIST_START           (1 << 8)
00237 #define PHYCR_BP_STRETCH           (1 << 7)
00238 #define PHYCR_LED_CNFG1            (1 << 6)
00239 #define PHYCR_LED_CNFG0            (1 << 5)
00240 #define PHYCR_PHYADDR4             (1 << 4)
00241 #define PHYCR_PHYADDR3             (1 << 3)
00242 #define PHYCR_PHYADDR2             (1 << 2)
00243 #define PHYCR_PHYADDR1             (1 << 1)
00244 #define PHYCR_PHYADDR0             (1 << 0)
00245 
00246 //10BTSCR register
00247 #define _10BTSCR_10BT_SERIAL       (1 << 15)
00248 #define _10BTSCR_SQUELCH2          (1 << 11)
00249 #define _10BTSCR_SQUELCH1          (1 << 10)
00250 #define _10BTSCR_SQUELCH0          (1 << 9)
00251 #define _10BTSCR_LOOPBACK_10_DIS   (1 << 8)
00252 #define _10BTSCR_LP_DIS            (1 << 7)
00253 #define _10BTSCR_FORCE_LINK_10     (1 << 6)
00254 #define _10BTSCR_POLARITY          (1 << 4)
00255 #define _10BTSCR_HEARTBEAT_DIS     (1 << 1)
00256 #define _10BTSCR_JABBER_DIS        (1 << 0)
00257 
00258 //CDCTRL1 register
00259 #define CDCTRL1_BIST_ERROR_COUNT7  (1 << 15)
00260 #define CDCTRL1_BIST_ERROR_COUNT6  (1 << 14)
00261 #define CDCTRL1_BIST_ERROR_COUNT5  (1 << 13)
00262 #define CDCTRL1_BIST_ERROR_COUNT4  (1 << 12)
00263 #define CDCTRL1_BIST_ERROR_COUNT3  (1 << 11)
00264 #define CDCTRL1_BIST_ERROR_COUNT2  (1 << 10)
00265 #define CDCTRL1_BIST_ERROR_COUNT1  (1 << 9)
00266 #define CDCTRL1_BIST_ERROR_COUNT0  (1 << 8)
00267 #define CDCTRL1_BIST_CONT_MODE     (1 << 5)
00268 #define CDCTRL1_CDPATTEN_10        (1 << 4)
00269 #define CDCTRL1_10MEG_PATT_GAP     (1 << 2)
00270 #define CDCTRL1_CDPATTSEL1         (1 << 1)
00271 #define CDCTRL1_CDPATTSEL0         (1 << 0)
00272 
00273 //EDCR register
00274 #define EDCR_ED_EN                 (1 << 15)
00275 #define EDCR_ED_AUTO_UP            (1 << 14)
00276 #define EDCR_ED_AUTO_DOWN          (1 << 13)
00277 #define EDCR_ED_MAN                (1 << 12)
00278 #define EDCR_ED_BURST_DIS          (1 << 11)
00279 #define EDCR_ED_PWR_STATE          (1 << 10)
00280 #define EDCR_ED_ERR_MET            (1 << 9)
00281 #define EDCR_ED_DATA_MET           (1 << 8)
00282 #define EDCR_ED_ERR_COUNT3         (1 << 7)
00283 #define EDCR_ED_ERR_COUNT2         (1 << 6)
00284 #define EDCR_ED_ERR_COUNT1         (1 << 5)
00285 #define EDCR_ED_ERR_COUNT0         (1 << 4)
00286 #define EDCR_ED_DATA_COUNT3        (1 << 3)
00287 #define EDCR_ED_DATA_COUNT2        (1 << 2)
00288 #define EDCR_ED_DATA_COUNT1        (1 << 1)
00289 #define EDCR_ED_DATA_COUNT0        (1 << 0)
00290 
00291 //DP83848 Ethernet PHY driver
00292 extern const PhyDriver dp83848PhyDriver;
00293 
00294 //DP83848 related functions
00295 error_t dp83848Init(NetInterface *interface);
00296 
00297 void dp83848Tick(NetInterface *interface);
00298 
00299 void dp83848EnableIrq(NetInterface *interface);
00300 void dp83848DisableIrq(NetInterface *interface);
00301 
00302 void dp83848EventHandler(NetInterface *interface);
00303 
00304 void dp83848WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00305 uint16_t dp83848ReadPhyReg(NetInterface *interface, uint8_t address);
00306 
00307 void dp83848DumpPhyReg(NetInterface *interface);
00308 
00309 #endif
00310