dp83620.h

00001 /**
00002  * @file dp83620.h
00003  * @brief DP83620 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _DP83620_H
00030 #define _DP83620_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef DP83620_PHY_ADDR
00037    #define DP83620_PHY_ADDR 1
00038 #elif (DP83620_PHY_ADDR < 0 || DP83620_PHY_ADDR > 31)
00039    #error DP83620_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //DP83620 registers
00043 #define DP83620_PHY_REG_BMCR       0x00
00044 #define DP83620_PHY_REG_BMSR       0x01
00045 #define DP83620_PHY_REG_PHYIDR1    0x02
00046 #define DP83620_PHY_REG_PHYIDR2    0x03
00047 #define DP83620_PHY_REG_ANAR       0x04
00048 #define DP83620_PHY_REG_ANLPAR     0x05
00049 #define DP83620_PHY_REG_ANER       0x06
00050 #define DP83620_PHY_REG_ANNPTR     0x07
00051 #define DP83620_PHY_REG_PHYSTS     0x10
00052 #define DP83620_PHY_REG_MICR       0x11
00053 #define DP83620_PHY_REG_MISR       0x12
00054 #define DP83620_PHY_REG_PAGESEL    0x13
00055 
00056 //Extended registers (page 0)
00057 #define DP83620_PHY_REG_FCSCR      0x14
00058 #define DP83620_PHY_REG_RECR       0x15
00059 #define DP83620_PHY_REG_PCSR       0x16
00060 #define DP83620_PHY_REG_RBR        0x17
00061 #define DP83620_PHY_REG_LEDCR      0x18
00062 #define DP83620_PHY_REG_PHYCR      0x19
00063 #define DP83620_PHY_REG_10BTSCR    0x1A
00064 #define DP83620_PHY_REG_CDCTRL1    0x1B
00065 #define DP83620_PHY_REG_PHYCR2     0x1C
00066 #define DP83620_PHY_REG_EDCR       0x1D
00067 #define DP83620_PHY_REG_PCFCR      0x1F
00068 
00069 //Extended registers (page 1)
00070 #define DP83620_PHY_REG_SD_CNFG    0x1E
00071 
00072 //Extended registers (page 2)
00073 #define DP83620_PHY_REG_LEN100_DET 0x14
00074 #define DP83620_PHY_REG_FREQ100    0x15
00075 #define DP83620_PHY_REG_TDR_CTRL   0x16
00076 #define DP83620_PHY_REG_TDR_WIN    0x17
00077 #define DP83620_PHY_REG_TDR_PEAK   0x18
00078 #define DP83620_PHY_REG_TDR_THR    0x19
00079 #define DP83620_PHY_REG_VAR_CTRL   0x1A
00080 #define DP83620_PHY_REG_VAR_DAT    0x1B
00081 #define DP83620_PHY_REG_LQMR       0x1D
00082 #define DP83620_PHY_REG_LQDR       0x1E
00083 #define DP83620_PHY_REG_LQMR2      0x1F
00084 
00085 //Extended registers (page 5)
00086 #define DP83620_PHY_REG_PSF_CFG    0x18
00087 
00088 //BMCR register
00089 #define BMCR_RESET                 (1 << 15)
00090 #define BMCR_LOOPBACK              (1 << 14)
00091 #define BMCR_SPEED_SEL             (1 << 13)
00092 #define BMCR_AN_EN                 (1 << 12)
00093 #define BMCR_POWER_DOWN            (1 << 11)
00094 #define BMCR_ISOLATE               (1 << 10)
00095 #define BMCR_RESTART_AN            (1 << 9)
00096 #define BMCR_DUPLEX_MODE           (1 << 8)
00097 #define BMCR_COL_TEST              (1 << 7)
00098 #define BMCR_UNIDIRECTIONAL_EN     (1 << 5)
00099 
00100 //BMSR register
00101 #define BMSR_100BT4                (1 << 15)
00102 #define BMSR_100BTX_FD             (1 << 14)
00103 #define BMSR_100BTX                (1 << 13)
00104 #define BMSR_10BT_FD               (1 << 12)
00105 #define BMSR_10BT                  (1 << 11)
00106 #define BMSR_UNIDIRECTIONAL_ABLE   (1 << 7)
00107 #define BMSR_NO_PREAMBLE           (1 << 6)
00108 #define BMSR_AN_COMPLETE           (1 << 5)
00109 #define BMSR_REMOTE_FAULT          (1 << 4)
00110 #define BMSR_AN_ABLE               (1 << 3)
00111 #define BMSR_LINK_STATUS           (1 << 2)
00112 #define BMSR_JABBER_DETECT         (1 << 1)
00113 #define BMSR_EXTENDED_CAP          (1 << 0)
00114 
00115 //ANAR register
00116 #define ANAR_NP                    (1 << 15)
00117 #define ANAR_RF                    (1 << 13)
00118 #define ANAR_ASM_DIR               (1 << 11)
00119 #define ANAR_PAUSE                 (1 << 10)
00120 #define ANAR_100BT4                (1 << 9)
00121 #define ANAR_100BTX_FD             (1 << 8)
00122 #define ANAR_100BTX                (1 << 7)
00123 #define ANAR_10BT_FD               (1 << 6)
00124 #define ANAR_10BT                  (1 << 5)
00125 #define ANAR_SELECTOR4             (1 << 4)
00126 #define ANAR_SELECTOR3             (1 << 3)
00127 #define ANAR_SELECTOR2             (1 << 2)
00128 #define ANAR_SELECTOR1             (1 << 1)
00129 #define ANAR_SELECTOR0             (1 << 0)
00130 
00131 //ANLPAR register
00132 #define ANLPAR_NP                  (1 << 15)
00133 #define ANLPAR_ACK                 (1 << 14)
00134 #define ANLPAR_RF                  (1 << 13)
00135 #define ANLPAR_ASM_DIR             (1 << 11)
00136 #define ANLPAR_PAUSE               (1 << 10)
00137 #define ANLPAR_100BT4              (1 << 9)
00138 #define ANLPAR_100BTX_FD           (1 << 8)
00139 #define ANLPAR_100BTX              (1 << 7)
00140 #define ANLPAR_10BT_FD             (1 << 6)
00141 #define ANLPAR_10BT                (1 << 5)
00142 #define ANLPAR_SELECTOR4           (1 << 4)
00143 #define ANLPAR_SELECTOR3           (1 << 3)
00144 #define ANLPAR_SELECTOR2           (1 << 2)
00145 #define ANLPAR_SELECTOR1           (1 << 1)
00146 #define ANLPAR_SELECTOR0           (1 << 0)
00147 
00148 //ANER register
00149 #define ANER_PDF                   (1 << 4)
00150 #define ANER_LP_NP_ABLE            (1 << 3)
00151 #define ANER_NP_ABLE               (1 << 2)
00152 #define ANER_PAGE_RX               (1 << 1)
00153 #define ANER_LP_AN_ABLE            (1 << 0)
00154 
00155 //ANNPTR register
00156 #define ANNPTR_NP                  (1 << 15)
00157 #define ANNPTR_MP                  (1 << 13)
00158 #define ANNPTR_ACK2                (1 << 12)
00159 #define ANNPTR_TOG_TX              (1 << 11)
00160 #define ANNPTR_CODE10              (1 << 10)
00161 #define ANNPTR_CODE9               (1 << 9)
00162 #define ANNPTR_CODE8               (1 << 8)
00163 #define ANNPTR_CODE7               (1 << 7)
00164 #define ANNPTR_CODE6               (1 << 6)
00165 #define ANNPTR_CODE5               (1 << 5)
00166 #define ANNPTR_CODE4               (1 << 4)
00167 #define ANNPTR_CODE3               (1 << 3)
00168 #define ANNPTR_CODE2               (1 << 2)
00169 #define ANNPTR_CODE1               (1 << 1)
00170 #define ANNPTR_CODE0               (1 << 0)
00171 
00172 //PHYSTS register
00173 #define PHYSTS_MDIX_MODE           (1 << 14)
00174 #define PHYSTS_RX_ERROR_LATCH      (1 << 13)
00175 #define PHYSTS_POLARITY_STATUS     (1 << 12)
00176 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
00177 #define PHYSTS_SIGNAL_DETECT       (1 << 10)
00178 #define PHYSTS_DESCRAMBLER_LOCK    (1 << 9)
00179 #define PHYSTS_PAGE_RECEIVED       (1 << 8)
00180 #define PHYSTS_MII_INTERRUPT       (1 << 7)
00181 #define PHYSTS_REMOTE_FAULT        (1 << 6)
00182 #define PHYSTS_JABBER_DETECT       (1 << 5)
00183 #define PHYSTS_AN_COMPLETE         (1 << 4)
00184 #define PHYSTS_LOOPBACK_STATUS     (1 << 3)
00185 #define PHYSTS_DUPLEX_STATUS       (1 << 2)
00186 #define PHYSTS_SPEED_STATUS        (1 << 1)
00187 #define PHYSTS_LINK_STATUS         (1 << 0)
00188 
00189 //MICR register
00190 #define MICR_TINT                  (1 << 2)
00191 #define MICR_INTEN                 (1 << 1)
00192 #define MICR_INT_OE                (1 << 0)
00193 
00194 //MISR register
00195 #define MISR_ED_INT                (1 << 14)
00196 #define MISR_LINK_INT              (1 << 13)
00197 #define MISR_SPD_INT               (1 << 12)
00198 #define MISR_DUP_INT               (1 << 11)
00199 #define MISR_ANC_INT               (1 << 10)
00200 #define MISR_FHF_INT               (1 << 9)
00201 #define MISR_RHF_INT               (1 << 8)
00202 #define MISR_LQ_INT_EN             (1 << 7)
00203 #define MISR_ED_INT_EN             (1 << 6)
00204 #define MISR_LINK_INT_EN           (1 << 5)
00205 #define MISR_SPD_INT_EN            (1 << 4)
00206 #define MISR_DUP_INT_EN            (1 << 3)
00207 #define MISR_ANC_INT_EN            (1 << 2)
00208 #define MISR_FHF_INT_EN            (1 << 1)
00209 #define MISR_RHF_INT_EN            (1 << 0)
00210 
00211 //PAGESEL register
00212 #define PAGESEL_PAGE_SEL2          (1 << 2)
00213 #define PAGESEL_PAGE_SEL1          (1 << 1)
00214 #define PAGESEL_PAGE_SEL0          (1 << 0)
00215 
00216 //FCSCR register
00217 #define FCSCR_FCSCNT7              (1 << 7)
00218 #define FCSCR_FCSCNT6              (1 << 6)
00219 #define FCSCR_FCSCNT5              (1 << 5)
00220 #define FCSCR_FCSCNT4              (1 << 4)
00221 #define FCSCR_FCSCNT3              (1 << 3)
00222 #define FCSCR_FCSCNT2              (1 << 2)
00223 #define FCSCR_FCSCNT1              (1 << 1)
00224 #define FCSCR_FCSCNT0              (1 << 0)
00225 
00226 //RECR register
00227 #define RECR_RXERCNT7              (1 << 7)
00228 #define RECR_RXERCNT6              (1 << 6)
00229 #define RECR_RXERCNT5              (1 << 5)
00230 #define RECR_RXERCNT4              (1 << 4)
00231 #define RECR_RXERCNT3              (1 << 3)
00232 #define RECR_RXERCNT2              (1 << 2)
00233 #define RECR_RXERCNT1              (1 << 1)
00234 #define RECR_RXERCNT0              (1 << 0)
00235 
00236 //PCSR register
00237 #define PCSR_AUTO_CROSSOVER        (1 << 15)
00238 #define PCSR_FREE_CLK              (1 << 11)
00239 #define PCSR_TQ_EN                 (1 << 10)
00240 #define PCSR_SD_FORCE_PMA          (1 << 9)
00241 #define PCSR_SD_OPTION             (1 << 8)
00242 #define PCSR_DESC_TIME             (1 << 7)
00243 #define PCSR_FX_EN                 (1 << 6)
00244 #define PCSR_FORCE_100_OK          (1 << 5)
00245 #define PCSR_FEFI_EN               (1 << 3)
00246 #define PCSR_NRZI_BYPASS           (1 << 2)
00247 #define PCSR_SCRAM_BYPASS          (1 << 1)
00248 #define PCSR_DESCRAM_BYPASS        (1 << 0)
00249 
00250 //RBR register
00251 #define RBR_RMII_MASTER            (1 << 14)
00252 #define RBR_DIS_TX_OPT             (1 << 13)
00253 #define RBR_PMD_LOOP               (1 << 8)
00254 #define RBR_SCMII_RX               (1 << 7)
00255 #define RBR_SCMII_TX               (1 << 6)
00256 #define RBR_RMII_MODE              (1 << 5)
00257 #define RBR_RMII_REV1_0            (1 << 4)
00258 #define RBR_RX_OVF_STS             (1 << 3)
00259 #define RBR_RX_UNF_STS             (1 << 2)
00260 #define RBR_ELAST_BUF1             (1 << 1)
00261 #define RBR_ELAST_BUF0             (1 << 0)
00262 
00263 //LEDCR register
00264 #define LEDCR_DIS_SPDLED           (1 << 11)
00265 #define LEDCR_DIS_LNKLED           (1 << 10)
00266 #define LEDCR_DIS_ACTLED           (1 << 9)
00267 #define LEDCR_LEDACT_RX            (1 << 8)
00268 #define LEDCR_BLINK_FREQ1          (1 << 7)
00269 #define LEDCR_BLINK_FREQ0          (1 << 6)
00270 #define LEDCR_DRV_SPDLED           (1 << 5)
00271 #define LEDCR_DRV_LNKLED           (1 << 4)
00272 #define LEDCR_DRV_ACTLED           (1 << 3)
00273 #define LEDCR_SPDLED               (1 << 2)
00274 #define LEDCR_LNKLED               (1 << 1)
00275 #define LEDCR_ACTLED               (1 << 0)
00276 
00277 #define LEDCR_BLINK_FREQ_6HZ       (0 << 6)
00278 #define LEDCR_BLINK_FREQ_12HZ      (1 << 6)
00279 #define LEDCR_BLINK_FREQ_24HZ      (2 << 6)
00280 #define LEDCR_BLINK_FREQ_48HZ      (3 << 6)
00281 
00282 //PHYCR register
00283 #define PHYCR_MDIX_EN              (1 << 15)
00284 #define PHYCR_FORCE_MDIX           (1 << 14)
00285 #define PHYCR_PAUSE_RX             (1 << 13)
00286 #define PHYCR_PAUSE_TX             (1 << 12)
00287 #define PHYCR_BIST_FE              (1 << 11)
00288 #define PHYCR_PSR_15               (1 << 10)
00289 #define PHYCR_BIST_STATUS          (1 << 9)
00290 #define PHYCR_BIST_START           (1 << 8)
00291 #define PHYCR_BP_STRETCH           (1 << 7)
00292 #define PHYCR_LED_CNFG1            (1 << 6)
00293 #define PHYCR_LED_CNFG0            (1 << 5)
00294 #define PHYCR_PHYADDR4             (1 << 4)
00295 #define PHYCR_PHYADDR3             (1 << 3)
00296 #define PHYCR_PHYADDR2             (1 << 2)
00297 #define PHYCR_PHYADDR1             (1 << 1)
00298 #define PHYCR_PHYADDR0             (1 << 0)
00299 
00300 //10BTSCR register
00301 #define _10BTSCR_10BT_SERIAL       (1 << 15)
00302 #define _10BTSCR_SQUELCH2          (1 << 11)
00303 #define _10BTSCR_SQUELCH1          (1 << 10)
00304 #define _10BTSCR_SQUELCH0          (1 << 9)
00305 #define _10BTSCR_LOOPBACK_10_DIS   (1 << 8)
00306 #define _10BTSCR_LP_DIS            (1 << 7)
00307 #define _10BTSCR_FORCE_LINK_10     (1 << 6)
00308 #define _10BTSCR_POLARITY          (1 << 4)
00309 #define _10BTSCR_AUTOPOL_DIS       (1 << 3)
00310 #define _10BTSCR_10BT_SCALE_MSB    (1 << 2)
00311 #define _10BTSCR_HEARTBEAT_DIS     (1 << 1)
00312 #define _10BTSCR_JABBER_DIS        (1 << 0)
00313 
00314 //CDCTRL1 register
00315 #define CDCTRL1_BIST_ERROR_COUNT7  (1 << 15)
00316 #define CDCTRL1_BIST_ERROR_COUNT6  (1 << 14)
00317 #define CDCTRL1_BIST_ERROR_COUNT5  (1 << 13)
00318 #define CDCTRL1_BIST_ERROR_COUNT4  (1 << 12)
00319 #define CDCTRL1_BIST_ERROR_COUNT3  (1 << 11)
00320 #define CDCTRL1_BIST_ERROR_COUNT2  (1 << 10)
00321 #define CDCTRL1_BIST_ERROR_COUNT1  (1 << 9)
00322 #define CDCTRL1_BIST_ERROR_COUNT0  (1 << 8)
00323 #define CDCTRL1_MII_CLOCK_EN       (1 << 6)
00324 #define CDCTRL1_BIST_CONT          (1 << 5)
00325 #define CDCTRL1_CDPATTEN_10        (1 << 4)
00326 #define CDCTRL1_MDIO_PULL_EN       (1 << 3)
00327 #define CDCTRL1_PATT_GAP_10M       (1 << 2)
00328 #define CDCTRL1_CDPATTSEL1         (1 << 1)
00329 #define CDCTRL1_CDPATTSEL0         (1 << 0)
00330 
00331 //PHYCR2 register
00332 #define PHYCR2_SYNC_ENET_EN        (1 << 13)
00333 #define PHYCR2_CLK_OUT RXCLK       (1 << 12)
00334 #define PHYCR2_BC_WRITE            (1 << 11)
00335 #define PHYCR2_PHYTER_COMP         (1 << 10)
00336 #define PHYCR2_SOFT_RESET          (1 << 9)
00337 #define PHYCR2_CLK_OUT_DIS         (1 << 1)
00338 
00339 //EDCR register
00340 #define EDCR_ED_EN                 (1 << 15)
00341 #define EDCR_ED_AUTO_UP            (1 << 14)
00342 #define EDCR_ED_AUTO_DOWN          (1 << 13)
00343 #define EDCR_ED_MAN                (1 << 12)
00344 #define EDCR_ED_BURST_DIS          (1 << 11)
00345 #define EDCR_ED_PWR_STATE          (1 << 10)
00346 #define EDCR_ED_ERR_MET            (1 << 9)
00347 #define EDCR_ED_DATA_MET           (1 << 8)
00348 #define EDCR_ED_ERR_COUNT3         (1 << 7)
00349 #define EDCR_ED_ERR_COUNT2         (1 << 6)
00350 #define EDCR_ED_ERR_COUNT1         (1 << 5)
00351 #define EDCR_ED_ERR_COUNT0         (1 << 4)
00352 #define EDCR_ED_DATA_COUNT3        (1 << 3)
00353 #define EDCR_ED_DATA_COUNT2        (1 << 2)
00354 #define EDCR_ED_DATA_COUNT1        (1 << 1)
00355 #define EDCR_ED_DATA_COUNT0        (1 << 0)
00356 
00357 //PCFCR register
00358 #define PCFCR_PCF_STS_ERR          (1 << 15)
00359 #define PCFCR_PCF_STS_OK           (1 << 14)
00360 #define PCFCR_PCF_DA_SEL           (1 << 8)
00361 #define PCFCR_PCF_INT_CTL1         (1 << 7)
00362 #define PCFCR_PCF_INT_CTL0         (1 << 6)
00363 #define PCFCR_PCF_BC_DIS           (1 << 5)
00364 #define PCFCR_PCF_BUF3             (1 << 4)
00365 #define PCFCR_PCF_BUF2             (1 << 3)
00366 #define PCFCR_PCF_BUF1             (1 << 2)
00367 #define PCFCR_PCF_BUF0             (1 << 1)
00368 #define PCFCR_PCF_EN               (1 << 0)
00369 
00370 //SD_CNFG register
00371 #define SD_CNFG_SD_TIME            (1 << 8)
00372 
00373 //LEN100_DET register
00374 #define LEN100_DET_CABLE_LEN7      (1 << 7)
00375 #define LEN100_DET_CABLE_LEN6      (1 << 6)
00376 #define LEN100_DET_CABLE_LEN5      (1 << 5)
00377 #define LEN100_DET_CABLE_LEN4      (1 << 4)
00378 #define LEN100_DET_CABLE_LEN3      (1 << 3)
00379 #define LEN100_DET_CABLE_LEN2      (1 << 2)
00380 #define LEN100_DET_CABLE_LEN1      (1 << 1)
00381 #define LEN100_DET_CABLE_LEN0      (1 << 0)
00382 
00383 //FREQ100 register
00384 #define FREQ100_SAMPLE_FREQ        (1 << 15)
00385 #define FREQ100_SEL_FC             (1 << 8)
00386 #define FREQ100_FREQ_OFFSET7       (1 << 7)
00387 #define FREQ100_FREQ_OFFSET6       (1 << 6)
00388 #define FREQ100_FREQ_OFFSET5       (1 << 5)
00389 #define FREQ100_FREQ_OFFSET4       (1 << 4)
00390 #define FREQ100_FREQ_OFFSET3       (1 << 3)
00391 #define FREQ100_FREQ_OFFSET2       (1 << 2)
00392 #define FREQ100_FREQ_OFFSET1       (1 << 1)
00393 #define FREQ100_FREQ_OFFSET0       (1 << 0)
00394 
00395 //TDR_CTRL register
00396 #define TDR_CTRL_TDR_ENABLE        (1 << 15)
00397 #define TDR_CTRL_TDR_100MB         (1 << 14)
00398 #define TDR_CTRL_TX_CHANNEL        (1 << 13)
00399 #define TDR_CTRL_RX_CHANNEL        (1 << 12)
00400 #define TDR_CTRL_SEND_TDR          (1 << 11)
00401 #define TDR_CTRL_TDR_WIDTH2        (1 << 10)
00402 #define TDR_CTRL_TDR_WIDTH1        (1 << 9)
00403 #define TDR_CTRL_TDR_WIDTH0        (1 << 8)
00404 #define TDR_CTRL_TDR_MIN_MODE      (1 << 7)
00405 #define TDR_CTRL_RX_THRESHOLD5     (1 << 5)
00406 #define TDR_CTRL_RX_THRESHOLD4     (1 << 4)
00407 #define TDR_CTRL_RX_THRESHOLD3     (1 << 3)
00408 #define TDR_CTRL_RX_THRESHOLD2     (1 << 2)
00409 #define TDR_CTRL_RX_THRESHOLD1     (1 << 1)
00410 #define TDR_CTRL_RX_THRESHOLD0     (1 << 0)
00411 
00412 //TDR_WIN register
00413 #define TDR_WIN_TDR_START7         (1 << 15)
00414 #define TDR_WIN_TDR_START6         (1 << 14)
00415 #define TDR_WIN_TDR_START5         (1 << 13)
00416 #define TDR_WIN_TDR_START4         (1 << 12)
00417 #define TDR_WIN_TDR_START3         (1 << 11)
00418 #define TDR_WIN_TDR_START2         (1 << 10)
00419 #define TDR_WIN_TDR_START1         (1 << 9)
00420 #define TDR_WIN_TDR_START0         (1 << 8)
00421 #define TDR_WIN_TDR_STOP7          (1 << 7)
00422 #define TDR_WIN_TDR_STOP6          (1 << 6)
00423 #define TDR_WIN_TDR_STOP5          (1 << 5)
00424 #define TDR_WIN_TDR_STOP4          (1 << 4)
00425 #define TDR_WIN_TDR_STOP3          (1 << 3)
00426 #define TDR_WIN_TDR_STOP2          (1 << 2)
00427 #define TDR_WIN_TDR_STOP1          (1 << 1)
00428 #define TDR_WIN_TDR_STOP0          (1 << 0)
00429 
00430 //TDR_PEAK register
00431 #define TDR_PEAK_TDR_PEAK5         (1 << 13)
00432 #define TDR_PEAK_TDR_PEAK4         (1 << 12)
00433 #define TDR_PEAK_TDR_PEAK3         (1 << 11)
00434 #define TDR_PEAK_TDR_PEAK2         (1 << 10)
00435 #define TDR_PEAK_TDR_PEAK1         (1 << 9)
00436 #define TDR_PEAK_TDR_PEAK0         (1 << 8)
00437 #define TDR_PEAK_TDR_PEAK_TIME7    (1 << 7)
00438 #define TDR_PEAK_TDR_PEAK_TIME6    (1 << 6)
00439 #define TDR_PEAK_TDR_PEAK_TIME5    (1 << 5)
00440 #define TDR_PEAK_TDR_PEAK_TIME4    (1 << 4)
00441 #define TDR_PEAK_TDR_PEAK_TIME3    (1 << 3)
00442 #define TDR_PEAK_TDR_PEAK_TIME2    (1 << 2)
00443 #define TDR_PEAK_TDR_PEAK_TIME1    (1 << 1)
00444 #define TDR_PEAK_TDR_PEAK_TIME0    (1 << 0)
00445 
00446 //TDR_THR register
00447 #define TDR_THR_TDR_THR_MET        (1 << 8)
00448 #define TDR_THR_TDR_THR_TIME7      (1 << 7)
00449 #define TDR_THR_TDR_THR_TIME6      (1 << 6)
00450 #define TDR_THR_TDR_THR_TIME5      (1 << 5)
00451 #define TDR_THR_TDR_THR_TIME4      (1 << 4)
00452 #define TDR_THR_TDR_THR_TIME3      (1 << 3)
00453 #define TDR_THR_TDR_THR_TIME2      (1 << 2)
00454 #define TDR_THR_TDR_THR_TIME1      (1 << 1)
00455 #define TDR_THR_TDR_THR_TIME0      (1 << 0)
00456 
00457 //VAR_CTRL register
00458 #define VAR_CTRL_VAR_RDY           (1 << 15)
00459 #define VAR_CTRL_VAR_FREEZE        (1 << 3)
00460 #define VAR_CTRL_VAR_TIMER1        (1 << 2)
00461 #define VAR_CTRL_VAR_TIMER0        (1 << 1)
00462 #define VAR_CTRL_VAR_ENABLE        (1 << 0)
00463 
00464 //LQMR register
00465 #define LQMR_LQM_ENABLE            (1 << 15)
00466 #define LQMR_RESTART_ON_FC         (1 << 14)
00467 #define LQMR_RESTART_ON_FREQ       (1 << 13)
00468 #define LQMR_RESTART_ON_DBLW       (1 << 12)
00469 #define LQMR_RESTART_ON_DAGC       (1 << 11)
00470 #define LQMR_RESTART_ON_C1         (1 << 10)
00471 #define LQMR_FC_HI_WARN            (1 << 9)
00472 #define LQMR_FC_LO_WARN            (1 << 8)
00473 #define LQMR_FREQ_HI_WARN          (1 << 7)
00474 #define LQMR_FREQ_LO_WARN          (1 << 6)
00475 #define LQMR_DBLW_HI_WARN          (1 << 5)
00476 #define LQMR_DBLW_LO_WARN          (1 << 4)
00477 #define LQMR_DAGC_HI_WARN          (1 << 3)
00478 #define LQMR_DAGC_LO_WARN          (1 << 2)
00479 #define LQMR_C1_HI_WARN            (1 << 1)
00480 #define LQMR_C1_LO_WARN            (1 << 0)
00481 
00482 //LQDR register
00483 #define LQDR_SAMPLE_PARAM          (1 << 13)
00484 #define LQDR_WRITE_LQ_THR          (1 << 12)
00485 #define LQDR_LQ_PARAM_SEL2         (1 << 11)
00486 #define LQDR_LQ_PARAM_SEL1         (1 << 10)
00487 #define LQDR_LQ_PARAM_SEL0         (1 << 9)
00488 #define LQDR_LQ_THR_SEL            (1 << 8)
00489 #define LQDR_LQ_THR_DATA7          (1 << 7)
00490 #define LQDR_LQ_THR_DATA6          (1 << 6)
00491 #define LQDR_LQ_THR_DATA5          (1 << 5)
00492 #define LQDR_LQ_THR_DATA4          (1 << 4)
00493 #define LQDR_LQ_THR_DATA3          (1 << 3)
00494 #define LQDR_LQ_THR_DATA2          (1 << 2)
00495 #define LQDR_LQ_THR_DATA1          (1 << 1)
00496 #define LQDR_LQ_THR_DATA0          (1 << 0)
00497 
00498 //LQMR2 register
00499 #define LQMR2_RESTART_ON_VAR       (1 << 10)
00500 #define LQMR2_VAR_HI_WARN          (1 << 1)
00501 
00502 //PSF_CFG register
00503 #define PSF_CFG_MAC_SRC_ADD1       (1 << 12)
00504 #define PSF_CFG_MAC_SRC_ADD0       (1 << 11)
00505 #define PSF_CFG_MIN_PRE2           (1 << 10)
00506 #define PSF_CFG_MIN_PRE1           (1 << 9)
00507 #define PSF_CFG_MIN_PRE0           (1 << 8)
00508 #define PSF_CFG_PSF_ENDIAN         (1 << 7)
00509 #define PSF_CFG_PSF_IPV4           (1 << 6)
00510 #define PSF_CFG_PSF_PCF_RD         (1 << 5)
00511 #define PSF_CFG_PSF_ERR_EN         (1 << 4)
00512 
00513 //DP83620 Ethernet PHY driver
00514 extern const PhyDriver dp83620PhyDriver;
00515 
00516 //DP83620 related functions
00517 error_t dp83620Init(NetInterface *interface);
00518 
00519 void dp83620Tick(NetInterface *interface);
00520 
00521 void dp83620EnableIrq(NetInterface *interface);
00522 void dp83620DisableIrq(NetInterface *interface);
00523 
00524 void dp83620EventHandler(NetInterface *interface);
00525 
00526 void dp83620WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00527 uint16_t dp83620ReadPhyReg(NetInterface *interface, uint8_t address);
00528 
00529 void dp83620DumpPhyReg(NetInterface *interface);
00530 
00531 #endif
00532