dm9161.h

00001 /**
00002  * @file dm9161.h
00003  * @brief DM9161 Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _DM9161_H
00030 #define _DM9161_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef DM9161_PHY_ADDR
00037    #define DM9161_PHY_ADDR 0
00038 #elif (DM9161_PHY_ADDR < 0 || DM9161_PHY_ADDR > 31)
00039    #error DM9161_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //DM9161 registers
00043 #define DM9161_PHY_REG_BMCR      0x00
00044 #define DM9161_PHY_REG_BMSR      0x01
00045 #define DM9161_PHY_REG_PHYIDR1   0x02
00046 #define DM9161_PHY_REG_PHYIDR2   0x03
00047 #define DM9161_PHY_REG_ANAR      0x04
00048 #define DM9161_PHY_REG_ANLPAR    0x05
00049 #define DM9161_PHY_REG_ANER      0x06
00050 #define DM9161_PHY_REG_DSCR      0x10
00051 #define DM9161_PHY_REG_DSCSR     0x11
00052 #define DM9161_PHY_REG_10BTCSR   0x12
00053 #define DM9161_PHY_REG_MDINTR    0x15
00054 #define DM9161_PHY_REG_RECR      0x16
00055 #define DM9161_PHY_REG_DISCR     0x17
00056 #define DM9161_PHY_REG_RLSR      0x18
00057 
00058 //BMCR register
00059 #define BMCR_RESET               (1 << 15)
00060 #define BMCR_LOOPBACK            (1 << 14)
00061 #define BMCR_SPEED_SEL           (1 << 13)
00062 #define BMCR_AN_EN               (1 << 12)
00063 #define BMCR_POWER_DOWN          (1 << 11)
00064 #define BMCR_ISOLATE             (1 << 10)
00065 #define BMCR_RESTART_AN          (1 << 9)
00066 #define BMCR_DUPLEX_MODE         (1 << 8)
00067 #define BMCR_COL_TEST            (1 << 7)
00068 
00069 //BMSR register
00070 #define BMSR_100BT4              (1 << 15)
00071 #define BMSR_100BTX_FD           (1 << 14)
00072 #define BMSR_100BTX              (1 << 13)
00073 #define BMSR_10BT_FD             (1 << 12)
00074 #define BMSR_10BT                (1 << 11)
00075 #define BMSR_NO_PREAMBLE         (1 << 6)
00076 #define BMSR_AN_COMPLETE         (1 << 5)
00077 #define BMSR_REMOTE_FAULT        (1 << 4)
00078 #define BMSR_AN_ABLE             (1 << 3)
00079 #define BMSR_LINK_STATUS         (1 << 2)
00080 #define BMSR_JABBER_DETECT       (1 << 1)
00081 #define BMSR_EXTENDED_CAP        (1 << 0)
00082 
00083 //ANAR register
00084 #define ANAR_NP                  (1 << 15)
00085 #define ANAR_ACK                 (1 << 14)
00086 #define ANAR_RF                  (1 << 13)
00087 #define ANAR_FCS                 (1 << 10)
00088 #define ANAR_100BT4              (1 << 9)
00089 #define ANAR_100BTX_FD           (1 << 8)
00090 #define ANAR_100BTX              (1 << 7)
00091 #define ANAR_10BT_FD             (1 << 6)
00092 #define ANAR_10BT                (1 << 5)
00093 #define ANAR_SELECTOR4           (1 << 4)
00094 #define ANAR_SELECTOR3           (1 << 3)
00095 #define ANAR_SELECTOR2           (1 << 2)
00096 #define ANAR_SELECTOR1           (1 << 1)
00097 #define ANAR_SELECTOR0           (1 << 0)
00098 
00099 //ANLPAR register
00100 #define ANLPAR_NP                (1 << 15)
00101 #define ANLPAR_ACK               (1 << 14)
00102 #define ANLPAR_RF                (1 << 13)
00103 #define ANLPAR_FCS               (1 << 10)
00104 #define ANLPAR_100BT4            (1 << 9)
00105 #define ANLPAR_100BTX_FD         (1 << 8)
00106 #define ANLPAR_100BTX            (1 << 7)
00107 #define ANLPAR_10BT_FD           (1 << 6)
00108 #define ANLPAR_10BT              (1 << 5)
00109 #define ANLPAR_SELECTOR4         (1 << 4)
00110 #define ANLPAR_SELECTOR3         (1 << 3)
00111 #define ANLPAR_SELECTOR2         (1 << 2)
00112 #define ANLPAR_SELECTOR1         (1 << 1)
00113 #define ANLPAR_SELECTOR0         (1 << 0)
00114 
00115 //ANER register
00116 #define ANER_PDF                 (1 << 4)
00117 #define ANER_LP_NP_ABLE          (1 << 3)
00118 #define ANER_NP_ABLE             (1 << 2)
00119 #define ANER_PAGE_RX             (1 << 1)
00120 #define ANER_LP_AN_ABLE          (1 << 0)
00121 
00122 //DSCR register
00123 #define DSCR_BP_4B5B             (1 << 15)
00124 #define DSCR_BP_SCR              (1 << 14)
00125 #define DSCR_BP_ALIGN            (1 << 13)
00126 #define DSCR_BP_ADPOK            (1 << 12)
00127 #define DSCR_REPEATER            (1 << 11)
00128 #define DSCR_TX                  (1 << 10)
00129 #define DSCR_FEF                 (1 << 9)
00130 #define DSCR_RMII_EN             (1 << 8)
00131 #define DSCR_F_LINK_100          (1 << 7)
00132 #define DSCR_SPLED_CTL           (1 << 6)
00133 #define DSCR_COLLED_CTL          (1 << 5)
00134 #define DSCR_RPDCTR_EN           (1 << 4)
00135 #define DSCR_SMRST               (1 << 3)
00136 #define DSCR_MFPSC               (1 << 2)
00137 #define DSCR_SLEEP               (1 << 1)
00138 #define DSCR_RLOUT               (1 << 0)
00139 
00140 //DSCSR register
00141 #define DSCSR_100FDX             (1 << 15)
00142 #define DSCSR_100HDX             (1 << 14)
00143 #define DSCSR_10FDX              (1 << 13)
00144 #define DSCSR_10HDX              (1 << 12)
00145 #define DSCSR_PHYADR4            (1 << 8)
00146 #define DSCSR_PHYADR3            (1 << 7)
00147 #define DSCSR_PHYADR2            (1 << 6)
00148 #define DSCSR_PHYADR1            (1 << 5)
00149 #define DSCSR_PHYADR0            (1 << 4)
00150 #define DSCSR_ANMB3              (1 << 3)
00151 #define DSCSR_ANMB2              (1 << 2)
00152 #define DSCSR_ANMB1              (1 << 1)
00153 #define DSCSR_ANMB0              (1 << 0)
00154 
00155 //10BTCSR register
00156 #define _10BTCSR_LP_EN           (1 << 14)
00157 #define _10BTCSR_HBE             (1 << 13)
00158 #define _10BTCSR_SQUELCH         (1 << 12)
00159 #define _10BTCSR_JABEN           (1 << 11)
00160 #define _10BTCSR_10BT_SER        (1 << 10)
00161 #define _10BTCSR_POLR            (1 << 0)
00162 
00163 //MDINTR register
00164 #define MDINTR_INTR_PEND         (1 << 15)
00165 #define MDINTR_FDX_MASK          (1 << 11)
00166 #define MDINTR_SPD_MASK          (1 << 10)
00167 #define MDINTR_LINK_MASK         (1 << 9)
00168 #define MDINTR_INTR_MASK         (1 << 8)
00169 #define MDINTR_FDX_CHANGE        (1 << 4)
00170 #define MDINTR_SPD_CHANGE        (1 << 3)
00171 #define MDINTR_LINK_CHANGE       (1 << 2)
00172 #define MDINTR_INTR_STATUS       (1 << 0)
00173 
00174 //RLSR register
00175 #define RLSR_LH_LEDST            (1 << 13)
00176 #define RLSR_LH_CSTS             (1 << 12)
00177 #define RLSR_LH_RMII             (1 << 11)
00178 #define RLSR_LH_SCRAM            (1 << 10)
00179 #define RLSR_LH_REPTR            (1 << 9)
00180 #define RLSR_LH_TSTMOD           (1 << 8)
00181 #define RLSR_LH_OP2              (1 << 7)
00182 #define RLSR_LH_OP1              (1 << 6)
00183 #define RLSR_LH_OP0              (1 << 5)
00184 #define RLSR_LH_PH4              (1 << 4)
00185 #define RLSR_LH_PH3              (1 << 3)
00186 #define RLSR_LH_PH2              (1 << 2)
00187 #define RLSR_LH_PH1              (1 << 1)
00188 #define RLSR_LH_PH0              (1 << 0)
00189 
00190 //Auto-negotiation state machine
00191 #define DSCSR_ANMB_MASK                      0x000F
00192 #define DSCSR_ANMB_IDLE                      0x0000
00193 #define DSCSR_ANMB_ABILITY_MATCH             0x0001
00194 #define DSCSR_ANMB_ACK_MATCH                 0x0002
00195 #define DSCSR_ANMB_ACK_MATCH_FAILED          0x0003
00196 #define DSCSR_ANMB_CONSIST_MATCH             0x0004
00197 #define DSCSR_ANMB_CONSIST_MATCH_FAILED      0x0005
00198 #define DSCSR_ANMB_SIGNAL_LINK_READY         0x0006
00199 #define DSCSR_ANMB_SIGNAL_LINK_READY_FAILED  0x0007
00200 #define DSCSR_ANMB_AN_SUCCESS                0x0008
00201 
00202 //DM9161 Ethernet PHY driver
00203 extern const PhyDriver dm9161PhyDriver;
00204 
00205 //DM9161 related functions
00206 error_t dm9161Init(NetInterface *interface);
00207 
00208 void dm9161Tick(NetInterface *interface);
00209 
00210 void dm9161EnableIrq(NetInterface *interface);
00211 void dm9161DisableIrq(NetInterface *interface);
00212 
00213 void dm9161EventHandler(NetInterface *interface);
00214 
00215 void dm9161WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00216 uint16_t dm9161ReadPhyReg(NetInterface *interface, uint8_t address);
00217 
00218 void dm9161DumpPhyReg(NetInterface *interface);
00219 
00220 #endif
00221