dm9000.h

00001 /**
00002  * @file dm9000.h
00003  * @brief DM9000A/B Ethernet controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _DM9000_H
00030 #define _DM9000_H
00031 
00032 //Dependencies
00033 #include "core/ethernet.h"
00034 
00035 //Loopback mode
00036 #ifndef DM9000_LOOPBACK_MODE
00037    #define DM9000_LOOPBACK_MODE DISABLED
00038 #elif (DM9000_LOOPBACK_MODE != ENABLED && DM9000_LOOPBACK_MODE != DISABLED)
00039    #error DM9000_LOOPBACK_MODE parameter is not valid
00040 #endif
00041 
00042 //DM9000 index register
00043 #ifndef DM9000_INDEX_REG
00044    #define DM9000_INDEX_REG *((volatile uint16_t *) 0x30000000)
00045 #endif
00046 
00047 //DM9000 data register
00048 #ifndef DM9000_DATA_REG
00049    #define DM9000_DATA_REG *((volatile uint16_t *) 0x30001000)
00050 #endif
00051 
00052 //DM9000 bus timing
00053 #define AT91C_SMC2_NWS_2        (2 << 0)
00054 #define AT91C_SMC2_TDF_2        (2 << 8)
00055 #define AT91C_SMC2_BAT_16       (1 << 12)
00056 #define AT91C_SMC2_DRP_STANDARD (0 << 15)
00057 #define AT91C_SMC2_RWSETUP_1    (1 << 24)
00058 #define AT91C_SMC2_RWHOLD_1     (1 << 28)
00059 
00060 //DM9000 identifiers
00061 #define DM9000_VID             0x0A46
00062 #define DM9000_PID             0x9000
00063 #define DM9000A_CHIP_REV       0x19
00064 #define DM9000B_CHIP_REV       0x1A
00065 
00066 //DM9000 registers
00067 #define DM9000_REG_NCR         0x00
00068 #define DM9000_REG_NSR         0x01
00069 #define DM9000_REG_TCR         0x02
00070 #define DM9000_REG_TSR1        0x03
00071 #define DM9000_REG_TSR2        0x04
00072 #define DM9000_REG_RCR         0x05
00073 #define DM9000_REG_RSR         0x06
00074 #define DM9000_REG_ROCR        0x07
00075 #define DM9000_REG_BPTR        0x08
00076 #define DM9000_REG_FCTR        0x09
00077 #define DM9000_REG_FCR         0x0A
00078 #define DM9000_REG_EPCR        0x0B
00079 #define DM9000_REG_EPAR        0x0C
00080 #define DM9000_REG_EPDRL       0x0D
00081 #define DM9000_REG_EPDRH       0x0E
00082 #define DM9000_REG_WCR         0x0F
00083 #define DM9000_REG_PAR0        0x10
00084 #define DM9000_REG_PAR1        0x11
00085 #define DM9000_REG_PAR2        0x12
00086 #define DM9000_REG_PAR3        0x13
00087 #define DM9000_REG_PAR4        0x14
00088 #define DM9000_REG_PAR5        0x15
00089 #define DM9000_REG_MAR0        0x16
00090 #define DM9000_REG_MAR1        0x17
00091 #define DM9000_REG_MAR2        0x18
00092 #define DM9000_REG_MAR3        0x19
00093 #define DM9000_REG_MAR4        0x1A
00094 #define DM9000_REG_MAR5        0x1B
00095 #define DM9000_REG_MAR6        0x1C
00096 #define DM9000_REG_MAR7        0x1D
00097 #define DM9000_REG_GPCR        0x1E
00098 #define DM9000_REG_GPR         0x1F
00099 #define DM9000_REG_TRPAL       0x22
00100 #define DM9000_REG_TRPAH       0x23
00101 #define DM9000_REG_RWPAL       0x24
00102 #define DM9000_REG_RWPAH       0x25
00103 #define DM9000_REG_VIDL        0x28
00104 #define DM9000_REG_VIDH        0x29
00105 #define DM9000_REG_PIDL        0x2A
00106 #define DM9000_REG_PIDH        0x2B
00107 #define DM9000_REG_CHIPR       0x2C
00108 #define DM9000_REG_TCR2        0x2D
00109 #define DM9000_REG_OCR         0x2E
00110 #define DM9000_REG_SMCR        0x2F
00111 #define DM9000_REG_ETXCSR      0x30
00112 #define DM9000_REG_TCSCR       0x31
00113 #define DM9000_REG_RCSCSR      0x32
00114 #define DM9000_REG_MPAR        0x33
00115 #define DM9000_REG_LEDCR       0x34
00116 #define DM9000_REG_BUSCR       0x38
00117 #define DM9000_REG_INTCR       0x39
00118 #define DM9000_REG_SCCR        0x50
00119 #define DM9000_REG_RSCCR       0x51
00120 #define DM9000_REG_MRCMDX      0xF0
00121 #define DM9000_REG_MRCMDX1     0xF1
00122 #define DM9000_REG_MRCMD       0xF2
00123 #define DM9000_REG_MRRL        0xF4
00124 #define DM9000_REG_MRRH        0xF5
00125 #define DM9000_REG_MWCMDX      0xF6
00126 #define DM9000_REG_MWCMD       0xF8
00127 #define DM9000_REG_MWRL        0xFA
00128 #define DM9000_REG_MWRH        0xFB
00129 #define DM9000_REG_TXPLL       0xFC
00130 #define DM9000_REG_TXPLH       0xFD
00131 #define DM9000_REG_ISR         0xFE
00132 #define DM9000_REG_IMR         0xFF
00133 
00134 //DM9000 PHY registers
00135 #define DM9000_PHY_REG_BMCR    0x00
00136 #define DM9000_PHY_REG_BMSR    0x01
00137 #define DM9000_PHY_REG_PHYIDR1 0x02
00138 #define DM9000_PHY_REG_PHYIDR2 0x03
00139 #define DM9000_PHY_REG_ANAR    0x04
00140 #define DM9000_PHY_REG_ANLPAR  0x05
00141 #define DM9000_PHY_REG_ANER    0x06
00142 #define DM9000_PHY_REG_DSCR    0x10
00143 #define DM9000_PHY_REG_DSCSR   0x11
00144 #define DM9000_PHY_REG_10BTCSR 0x12
00145 #define DM9000_PHY_REG_PWDOR   0x13
00146 #define DM9000_PHY_REG_SCR     0x14
00147 #define DM9000_PHY_REG_DSP     0x1B
00148 #define DM9000_PHY_REG_PSCR    0x1D
00149 
00150 //NCR register
00151 #define NCR_WAKEEN         (1 << 6)
00152 #define NCR_FCOL           (1 << 4)
00153 #define NCR_FDX            (1 << 3)
00154 #define NCR_LBK            (3 << 1)
00155 #define NCR_RST            (1 << 0)
00156 
00157 //NSR register
00158 #define NSR_SPEED          (1 << 7)
00159 #define NSR_LINKST         (1 << 6)
00160 #define NSR_WAKEST         (1 << 5)
00161 #define NSR_TX2END         (1 << 3)
00162 #define NSR_TX1END         (1 << 2)
00163 #define NSR_RXOV           (1 << 1)
00164 
00165 //TCR register
00166 #define TCR_TJDIS          (1 << 6)
00167 #define TCR_EXCECM         (1 << 5)
00168 #define TCR_PAD_DIS2       (1 << 4)
00169 #define TCR_CRC_DIS2       (1 << 3)
00170 #define TCR_PAD_DIS1       (1 << 2)
00171 #define TCR_CRC_DIS1       (1 << 1)
00172 #define TCR_TXREQ          (1 << 0)
00173 
00174 //TSR1 and TSR2 registers
00175 #define TSR_TJTO           (1 << 7)
00176 #define TSR_LC             (1 << 6)
00177 #define TSR_NC             (1 << 5)
00178 #define TSR_LCOL           (1 << 4)
00179 #define TSR_COL            (1 << 3)
00180 #define TSR_EC             (1 << 2)
00181 
00182 //RCR register
00183 #define RCR_WTDIS          (1 << 6)
00184 #define RCR_DIS_LONG       (1 << 5)
00185 #define RCR_DIS_CRC        (1 << 4)
00186 #define RCR_ALL            (1 << 3)
00187 #define RCR_RUNT           (1 << 2)
00188 #define RCR_PRMSC          (1 << 1)
00189 #define RCR_RXEN           (1 << 0)
00190 
00191 //RSR register
00192 #define RSR_RF             (1 << 7)
00193 #define RSR_MF             (1 << 6)
00194 #define RSR_LCS            (1 << 5)
00195 #define RSR_RWTO           (1 << 4)
00196 #define RSR_PLE            (1 << 3)
00197 #define RSR_AE             (1 << 2)
00198 #define RSR_CE             (1 << 1)
00199 #define RSR_FOE            (1 << 0)
00200 
00201 //ROCR register
00202 #define ROCR_ROC           (127 << 0)
00203 #define ROCR_RXFU          (1 << 7)
00204 
00205 //BPTR register
00206 #define BPTR_BPHW          (15 << 4)
00207 #define BPTR_JPT           (15 << 0)
00208 
00209 //FCTR register
00210 #define FCTR_HWOT          (15 << 4)
00211 #define FCTR_LWOT          (15 << 0)
00212 
00213 //FCR register
00214 #define FCR_TXP0           (1 << 7)
00215 #define FCR_TXPF           (1 << 6)
00216 #define FCR_TXPEN          (1 << 5)
00217 #define FCR_BKPA           (1 << 4)
00218 #define FCR_BKPM           (1 << 3)
00219 #define FCR_RXPS           (1 << 2)
00220 #define FCR_RXPCS          (1 << 1)
00221 #define FCR_FLCE           (1 << 0)
00222 
00223 //EPCR register
00224 #define EPCR_REEP          (1 << 5)
00225 #define EPCR_WEP           (1 << 4)
00226 #define EPCR_EPOS          (1 << 3)
00227 #define EPCR_ERPRR         (1 << 2)
00228 #define EPCR_ERPRW         (1 << 1)
00229 #define EPCR_ERRE          (1 << 0)
00230 
00231 //EPAR register
00232 #define EPAR_PHY_ADR       (3 << 6)
00233 #define EPAR_EROA          (31 << 0)
00234 
00235 //WCR register
00236 #define WCR_LINKEN         (1 << 5)
00237 #define WCR_SAMPLEEN       (1 << 4)
00238 #define WCR_MAGICEN        (1 << 3)
00239 #define WCR_LINKST         (1 << 2)
00240 #define WCR_SAMPLEST       (1 << 1)
00241 #define WCR_MAGICST        (1 << 0)
00242 
00243 //GPCR register
00244 #define GPCR_GPC6          (1 << 6)
00245 #define GPCR_GPC5          (1 << 5)
00246 #define GPCR_GPC4          (1 << 4)
00247 #define GPCR_GPC3          (1 << 3)
00248 #define GPCR_GPC2          (1 << 2)
00249 #define GPCR_GPC1          (1 << 1)
00250 
00251 //GPR register
00252 #define GPR_GPO6           (1 << 6)
00253 #define GPR_GPO5           (1 << 5)
00254 #define GPR_GPO4           (1 << 4)
00255 #define GPR_GPIO3          (1 << 3)
00256 #define GPR_GPIO2          (1 << 2)
00257 #define GPR_GPIO1          (1 << 1)
00258 #define GPR_PHYPD          (1 << 0)
00259 
00260 //TCR2 register
00261 #define TCR2_LED           (1 << 7)
00262 #define TCR2_RLCP          (1 << 6)
00263 #define TCR2_DTU           (1 << 5)
00264 #define TCR2_ONEPM         (1 << 4)
00265 #define TCR2_IFGS          (15 << 0)
00266 
00267 //OCR register
00268 #define OCR_SCC            (3 << 6)
00269 #define OCR_SOE            (1 << 4)
00270 #define OCR_SCS            (1 << 3)
00271 #define OCR_PHYOP          (7 << 0)
00272 
00273 //SMCR register
00274 #define SMCR_SM_EN         (1 << 7)
00275 #define SMCR_FLC           (1 << 2)
00276 #define SMCR_FB1           (1 << 1)
00277 #define SMCR_FB0           (1 << 0)
00278 
00279 //ETXCSR register
00280 #define ETXCSR_ETE         (1 << 7)
00281 #define ETXCSR_ETS2        (1 << 6)
00282 #define ETXCSR_ETS1        (1 << 5)
00283 #define ETXCSR_ETT         (3 << 0)
00284 
00285 //TCSCR register
00286 #define TCSCR_UDPCSE       (1 << 2)
00287 #define TCSCR_TCPCSE       (1 << 1)
00288 #define TCSCR_IPCSE        (1 << 0)
00289 
00290 //RCSCSR register
00291 #define RCSCSR_UDPS        (1 << 7)
00292 #define RCSCSR_TCPS        (1 << 6)
00293 #define RCSCSR_IPS         (1 << 5)
00294 #define RCSCSR_UDPP        (1 << 4)
00295 #define RCSCSR_TCPP        (1 << 3)
00296 #define RCSCSR_IPP         (1 << 2)
00297 #define RCSCSR_RCSEN       (1 << 1)
00298 #define RCSCSR_DCSE        (1 << 0)
00299 
00300 //MPAR register
00301 #define MPAR_ADR_EN        (1 << 7)
00302 #define MPAR_EPHYADR       (31 << 0)
00303 
00304 //LEDC register
00305 #define LEDCR_GPIO         (1 << 1)
00306 #define LEDCR_MII          (1 << 0)
00307 
00308 //BUSCR register
00309 #define BUSCR_CURR         (3 << 5)
00310 #define BUSCR_EST          (1 << 3)
00311 #define BUSCR_IOW_SPIKE    (1 << 1)
00312 #define BUSCR_IOR_SPIKE    (1 << 0)
00313 
00314 //INTCR register
00315 #define INTCR_INT_TYPE     (1 << 1)
00316 #define INTCR_INT_POL      (1 << 0)
00317 
00318 //SCCR register
00319 #define SCCR_DIS_CLK       (1 << 0)
00320 
00321 //ISR register
00322 #define ISR_IOMODE         (1 << 7)
00323 #define ISR_LNKCHG         (1 << 5)
00324 #define ISR_UDRUN          (1 << 4)
00325 #define ISR_ROO            (1 << 3)
00326 #define ISR_ROS            (1 << 2)
00327 #define ISR_PT             (1 << 1)
00328 #define ISR_PR             (1 << 0)
00329 
00330 //IMR register
00331 #define IMR_PAR            (1 << 7)
00332 #define IMR_LNKCHGI        (1 << 5)
00333 #define IMR_UDRUNI         (1 << 4)
00334 #define IMR_ROOI           (1 << 3)
00335 #define IMR_ROI            (1 << 2)
00336 #define IMR_PTI            (1 << 1)
00337 #define IMR_PRI            (1 << 0)
00338 
00339 //PHY BMCR register
00340 #define BMCR_RST           (1 << 15)
00341 #define BMCR_LOOPBACK      (1 << 14)
00342 #define BMCR_SPEED_SEL     (1 << 13)
00343 #define BMCR_AN_EN         (1 << 12)
00344 #define BMCR_PD            (1 << 11)
00345 #define BMCR_ISOLATE       (1 << 10)
00346 #define BMCR_RESTART_AN    (1 << 9)
00347 #define BMCR_DUPLEX_MODE   (1 << 8)
00348 #define BMCR_COL_TEST      (1 << 7)
00349 
00350 //Loopback mode
00351 #define DM9000_LBK_NORMAL  (0 << 1)
00352 #define DM9000_LBK_MAC     (1 << 1)
00353 #define DM9000_LBK_PHY     (2 << 1)
00354 
00355 
00356 /**
00357  * @brief DM9000 driver context
00358  **/
00359 
00360 typedef struct
00361 {
00362    uint_t queuedPackets; ///<Number of packets in transmission buffer
00363    uint8_t *txBuffer;    ///<Transmit buffer
00364    uint8_t *rxBuffer;    ///<Receive buffer
00365 } Dm9000Context;
00366 
00367 
00368 //DM9000 driver
00369 extern const NicDriver dm9000Driver;
00370 
00371 //DM9000 related functions
00372 error_t dm9000Init(NetInterface *interface);
00373 
00374 void dm9000Tick(NetInterface *interface);
00375 
00376 void dm9000EnableIrq(NetInterface *interface);
00377 void dm9000DisableIrq(NetInterface *interface);
00378 bool_t dm9000IrqHandler(NetInterface *interface);
00379 void dm9000EventHandler(NetInterface *interface);
00380 
00381 error_t dm9000SendPacket(NetInterface *interface,
00382    const NetBuffer *buffer, size_t offset);
00383 
00384 error_t dm9000ReceivePacket(NetInterface *interface);
00385 
00386 error_t dm9000SetMulticastFilter(NetInterface *interface);
00387 
00388 void dm9000WriteReg(uint8_t address, uint8_t data);
00389 uint8_t dm9000ReadReg(uint8_t address);
00390 
00391 void dm9000WritePhyReg(uint8_t address, uint16_t data);
00392 uint16_t dm9000ReadPhyReg(uint8_t address);
00393 
00394 uint32_t dm9000CalcCrc(const void *data, size_t length);
00395 
00396 #endif
00397